xcvr_test_system

2017.11.13.11:23:30 Datasheet
Overview
  clk_50  xcvr_test_system

All Components
   data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   freq_counter_0 freq_counter 1.0
   mm_bridge_0 altera_avalon_mm_bridge 16.930
Memory Map
  data_pattern_checker_0
csr_slave 
  data_pattern_generator_0
csr_slave 
  freq_counter_0
csr 

clk_50

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
mm_bridge_0 m0   data_pattern_checker_0
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset
xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
mm_bridge_0 m0   data_pattern_generator_0
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset
xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

freq_counter_0

freq_counter v1.0
mm_bridge_0 m0   freq_counter_0
  csr
clk_50 clk  
  clock
clk_reset  
  reset
xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_0

altera_avalon_mm_bridge v16.930
clk_50 clk   mm_bridge_0
  clk
clk_reset  
  reset
m0   freq_counter_0
  csr
m0   data_pattern_generator_0
  csr_slave
m0   data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

rx_fifo

fifo v16.930
xcvr_user_rx_fifo_converter_0 fifo_output   rx_fifo
  fifo_output
fifo_input   xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

tx_fifo

fifo v16.930
xcvr_user_tx_fifo_converter_0 fifo_output   tx_fifo
  fifo_output
fifo_input   xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
data_pattern_generator_0 conduit_pattern_out_clk   xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
tx_clkout2_sample   freq_counter_0
  sample_clock
rx_clkout2_a   data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
rx_fifo fifo_input   xcvr_user_rx_fifo_converter_0
  fifo_input
xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
data_pattern_checker_pattern_in_fifo_read   data_pattern_checker_0
  conduit_pattern_in
fifo_output   rx_fifo
  fifo_output


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
tx_fifo fifo_input   xcvr_user_tx_fifo_converter_0
  fifo_input
xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
data_pattern_generator_pattern_out_fifo_write   data_pattern_generator_0
  conduit_pattern_out
fifo_output   tx_fifo
  fifo_output


Parameters

generateLegacySim false
  

Software Assignments

(none)
generation took 0.00 seconds rendering took 0.01 seconds