fmc_cmos_system

2017.11.13.11:14:11 Datasheet
Overview
  clkin  fmc_cmos_system
  fmc_cmos_system_0_clk_50 

All Components
   mm_bridge_0 altera_avalon_mm_bridge 17.1
   nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pio_0 altera_avalon_pio 17.1
   fmc_cmos_system_0 cmos_test_system 1.0
   fmc_cmos_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_cmos_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_cmos_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
Memory Map
  nativePHY_loopback_cont_0
csr 
  pio_0
s1 
  fmc_cmos_system_0
mm_bridge_0_s0 
  fmc_cmos_system_0_data_pattern_checker_0
csr_slave 
  fmc_cmos_system_0_data_pattern_generator_0
csr_slave 

clkin

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_0

altera_avalon_mm_bridge v17.1
clkin clk   mm_bridge_0
  clk
clk_reset  
  reset
m0   nativePHY_loopback_cont_0
  csr
m0   fmc_cmos_system_0_mm_bridge_0
  s0
m0   pio_0
  s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
mm_bridge_0 m0   nativePHY_loopback_cont_0
  csr
clkin clk  
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pio_0

altera_avalon_pio v17.1
mm_bridge_0 m0   pio_0
  s1
clkin clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 32
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 4294967295

xcvr_st_converter_0

xcvr_st_converter v1.0
clkin clk   xcvr_st_converter_0
  rx_clkout
clk  
  tx_clkout
fmc_cmos_system_0_data_pattern_checker_0 conduit_pattern_in  
  rx_data_a
conduit_pattern_in_clk  
  rx_clkout_a
fmc_cmos_system_0_data_pattern_generator_0 conduit_pattern_out  
  tx_data_a
conduit_pattern_out_clk  
  tx_clkout_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0

cmos_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0_clk_50

clock_source vnull
clkin clk   fmc_cmos_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_cmos_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_cmos_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_cmos_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_cmos_system_0_mm_bridge_0 m0   fmc_cmos_system_0_data_pattern_checker_0
  csr_slave
fmc_cmos_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
conduit_pattern_in   xcvr_st_converter_0
  rx_data_a
conduit_pattern_in_clk  
  rx_clkout_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_cmos_system_0_mm_bridge_0 m0   fmc_cmos_system_0_data_pattern_generator_0
  csr_slave
fmc_cmos_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
conduit_pattern_out   xcvr_st_converter_0
  tx_data_a
conduit_pattern_out_clk  
  tx_clkout_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_cmos_system_0_clk_50 clk   fmc_cmos_system_0_mm_bridge_0
  clk
clk_reset  
  reset
mm_bridge_0 m0  
  s0
m0   fmc_cmos_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_cmos_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)
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