bup_qsys_msgdma_tx

2017.11.28.20:27:03 Datasheet
Overview

All Components
   msgdma_rx_0 altera_msgdma 17.1
Memory Map
msgdma_rx_0
 descriptor_read_master  descriptor_write_master  mm_read
  msgdma_rx_0
csr 
prefetcher_csr 

msgdma_rx_0

altera_msgdma v17.1


Parameters

MODE 1
DATA_WIDTH 32
USE_FIX_ADDRESS_WIDTH 0
FIX_ADDRESS_WIDTH 32
EXPOSE_ST_PORT 0
DATA_FIFO_DEPTH 128
DESCRIPTOR_FIFO_DEPTH 128
RESPONSE_PORT 2
MAX_BYTE 262144
TRANSFER_TYPE Aligned Accesses
BURST_ENABLE 0
MAX_BURST_COUNT 2
BURST_WRAPPING_SUPPORT 0
ENHANCED_FEATURES 0
STRIDE_ENABLE 0
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
PACKET_ENABLE 1
ERROR_ENABLE 1
ERROR_WIDTH 1
CHANNEL_ENABLE 0
CHANNEL_WIDTH 8
PREFETCHER_ENABLE 1
PREFETCHER_READ_BURST_ENABLE 0
PREFETCHER_DATA_WIDTH 32
PREFETCHER_MAX_READ_BURST_COUNT 2
generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
CHANNEL_ENABLE 0
CHANNEL_ENABLE_DERIVED 0
CHANNEL_WIDTH 8
DATA_FIFO_DEPTH 128
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 128
DMA_MODE 1
ENHANCED_FEATURES 0
ERROR_ENABLE 1
ERROR_ENABLE_DERIVED 1
ERROR_WIDTH 1
MAX_BURST_COUNT 2
MAX_BYTE 262144
MAX_STRIDE 1
PACKET_ENABLE 1
PACKET_ENABLE_DERIVED 1
PREFETCHER_ENABLE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_PORT 2
STRIDE_ENABLE 0
STRIDE_ENABLE_DERIVED 0
TRANSFER_TYPE Aligned Accesses
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