ed_synth

2017.11.08.15:13:10 Datasheet
Overview
  clk_50m  ed_synth
  mSGDMA_0_clk 
  mSGDMA_0_clk_0 

All Components
   emif_s10_0 altera_emif_s10 17.1
   freq_counter_0 freq_counter 1.0
   master_driver_msgdma_0 master_driver_msgdma 1.0
   product_info_0 product_info 1.0
   mSGDMA_0 mSGDMA 1.0
   mSGDMA_0_dispatcher_read modular_sgdma_dispatcher 17.1
   mSGDMA_0_dispatcher_write modular_sgdma_dispatcher 17.1
   mSGDMA_0_freq_counter_0 freq_counter 1.0
   mSGDMA_0_mm_bridge_slv altera_avalon_mm_bridge 17.1
   mSGDMA_0_prbs_pattern_checker prbs_pattern_checker 1.1
   mSGDMA_0_prbs_pattern_generator prbs_pattern_generator 1.1
   mSGDMA_0_status_mon_0 status_mon 1.0
   mSGDMA_0_timer_0 altera_avalon_timer 17.1
Memory Map
master_0 master_driver_msgdma_0 mSGDMA_0 mSGDMA_0_dma_read_master mSGDMA_0_dma_write_master
 master  avalon_master  dma_read_master  dma_write_master  Data_Read_Master  Data_Write_Master
  emif_s10_0
ctrl_amm_0  0x00000000 0x00000000 0x00000000 0x00000000
  freq_counter_0
csr  0x00004000
  master_driver_msgdma_0
csr  0x00100000
  product_info_0
avalon_slave_0  0x00000000
  mSGDMA_0
mm_bridge_slv 
  mSGDMA_0_dispatcher_read
CSR  0x00200080
Descriptor_Slave  0x002000b0
  mSGDMA_0_dispatcher_write
CSR  0x00200060
Descriptor_Slave  0x002000a0
  mSGDMA_0_freq_counter_0
csr  0x00290000
  mSGDMA_0_prbs_pattern_checker
csr  0x00200000
  mSGDMA_0_prbs_pattern_generator
csr  0x00200040
  mSGDMA_0_status_mon_0
slv  0x00281200
  mSGDMA_0_timer_0
s1  0x00281000

clk_50m

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_s10_0

altera_emif_s10 v17.1
mSGDMA_0_dma_read_master Data_Read_Master   emif_s10_0
  ctrl_amm_0
mSGDMA_0_dma_write_master Data_Write_Master  
  ctrl_amm_0
local_reset_combiner local_reset_req_out_0  
  local_reset_req
mSGDMA_0_status_mon_0 status  
  status
emif_usr_clk   mSGDMA_0_clk
  clk_in
emif_usr_reset_n  
  clk_in_reset
pll_ref_clk_out   local_reset_combiner
  generic_clk
local_reset_status  
  local_reset_status_in_0
pll_locked  
  generic_conduit_reset_n
pll_ref_clk_out   freq_counter_0
  sample_clock
emif_usr_reset_n   master_driver_msgdma_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

freq_counter_0

freq_counter v1.0
master_0 master   freq_counter_0
  csr
clk_50m clk  
  clock
clk_reset  
  reset
emif_s10_0 pll_ref_clk_out  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

local_reset_combiner

altera_emif_local_reset_combiner v17.1
emif_s10_0 pll_ref_clk_out   local_reset_combiner
  generic_clk
local_reset_status  
  local_reset_status_in_0
pll_locked  
  generic_conduit_reset_n
local_reset_req_out_0   emif_s10_0
  local_reset_req


Parameters

generateLegacySim false
  

Software Assignments

(none)

master_0

altera_jtag_avalon_master v17.1
clk_50m clk   master_0
  clk
clk_reset  
  clk_reset
master   product_info_0
  avalon_slave_0
master   freq_counter_0
  csr
master   master_driver_msgdma_0
  csr


Parameters

generateLegacySim false
  

Software Assignments

(none)

master_driver_msgdma_0

master_driver_msgdma v1.0
master_0 master   master_driver_msgdma_0
  csr
clk_50m clk  
  clock
emif_s10_0 emif_usr_reset_n  
  reset
avalon_master   mSGDMA_0_mm_bridge_slv
  s0
cal_fail   mSGDMA_0_status_mon_0
  cal_fail_mon
cal_success  
  cal_success_mon
interrupt_receiver   mSGDMA_0_dispatcher_read
  csr_irq
interrupt_receiver   mSGDMA_0_dispatcher_write
  csr_irq
reset_source   mSGDMA_0_clk
  clk_in_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

product_info_0

product_info v1.0
master_0 master   product_info_0
  avalon_slave_0
clk_50m clk  
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0

mSGDMA v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_clk

clock_source vnull
emif_s10_0 emif_usr_clk   mSGDMA_0_clk
  clk_in
emif_usr_reset_n  
  clk_in_reset
master_driver_msgdma_0 reset_source  
  clk_in_reset
clk   mSGDMA_0_dma_read_master
  Clock
clk_reset  
  Clock_reset
clk   mSGDMA_0_dma_write_master
  Clock
clk_reset  
  Clock_reset
clk   mSGDMA_0_timing_adapter
  clk
clk_reset  
  reset
clk   mSGDMA_0_mm_bridge_slv
  clk
clk_reset  
  reset
clk   mSGDMA_0_dispatcher_read
  clock
clk_reset  
  clock_reset
clk   mSGDMA_0_dispatcher_write
  clock
clk_reset  
  clock_reset
clk   mSGDMA_0_status_mon_0
  clock
clk_reset  
  reset_n
clk   mSGDMA_0_prbs_pattern_checker
  clock
clk_reset  
  reset
clk   mSGDMA_0_prbs_pattern_generator
  clock
clk_reset  
  reset
clk   mSGDMA_0_freq_counter_0
  sample_clock
clk_reset   mSGDMA_0_timer_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_clk_0

clock_source vnull
clk_50m clk   mSGDMA_0_clk_0
  clk_in
clk_reset  
  clk_in_reset
clk   mSGDMA_0_timer_0
  clk
clk   mSGDMA_0_freq_counter_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_dispatcher_read

modular_sgdma_dispatcher v17.1
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_dispatcher_read
  CSR
m0  
  Descriptor_Slave
mSGDMA_0_dma_read_master Response_Source  
  Read_Response_Sink
mSGDMA_0_clk clk  
  clock
clk_reset  
  clock_reset
master_driver_msgdma_0 interrupt_receiver  
  csr_irq
Read_Command_Source   mSGDMA_0_dma_read_master
  Command_Sink


Parameters

generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
DATA_FIFO_DEPTH 32
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
MAX_BURST_COUNT 2
MAX_BYTE 1024
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_FIFO_DEPTH 2048
RESPONSE_PORT 0
STRIDE_ENABLE 0
TRANSFER_TYPE Aligned Accesses

mSGDMA_0_dispatcher_write

modular_sgdma_dispatcher v17.1
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_dispatcher_write
  CSR
m0  
  Descriptor_Slave
mSGDMA_0_dma_write_master Response_Source  
  Write_Response_Sink
mSGDMA_0_clk clk  
  clock
clk_reset  
  clock_reset
master_driver_msgdma_0 interrupt_receiver  
  csr_irq
Write_Command_Source   mSGDMA_0_dma_write_master
  Command_Sink


Parameters

generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
DATA_FIFO_DEPTH 32
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
MAX_BURST_COUNT 2
MAX_BYTE 1024
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_FIFO_DEPTH 2048
RESPONSE_PORT 2
STRIDE_ENABLE 0
TRANSFER_TYPE Aligned Accesses

mSGDMA_0_dma_read_master

dma_read_master v17.1
mSGDMA_0_dispatcher_read Read_Command_Source   mSGDMA_0_dma_read_master
  Command_Sink
mSGDMA_0_clk clk  
  Clock
clk_reset  
  Clock_reset
Data_Source   mSGDMA_0_prbs_pattern_checker
  st_pattern_input
Response_Source   mSGDMA_0_dispatcher_read
  Read_Response_Sink
Data_Read_Master   emif_s10_0
  ctrl_amm_0


Parameters

generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_dma_write_master

dma_write_master v17.1
mSGDMA_0_dispatcher_write Write_Command_Source   mSGDMA_0_dma_write_master
  Command_Sink
mSGDMA_0_timing_adapter out  
  Data_Sink
mSGDMA_0_clk clk  
  Clock
clk_reset  
  Clock_reset
Response_Source   mSGDMA_0_dispatcher_write
  Write_Response_Sink
Data_Write_Master   emif_s10_0
  ctrl_amm_0


Parameters

generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_freq_counter_0

freq_counter v1.0
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_freq_counter_0
  csr
mSGDMA_0_clk_0 clk  
  clock
clk_reset  
  reset
mSGDMA_0_clk clk  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_mm_bridge_slv

altera_avalon_mm_bridge v17.1
mSGDMA_0_clk clk   mSGDMA_0_mm_bridge_slv
  clk
clk_reset  
  reset
master_driver_msgdma_0 avalon_master  
  s0
m0   mSGDMA_0_dispatcher_read
  CSR
m0  
  Descriptor_Slave
m0   mSGDMA_0_dispatcher_write
  CSR
m0  
  Descriptor_Slave
m0   mSGDMA_0_freq_counter_0
  csr
m0   mSGDMA_0_prbs_pattern_checker
  csr
m0   mSGDMA_0_prbs_pattern_generator
  csr
m0   mSGDMA_0_timer_0
  s1
m0   mSGDMA_0_status_mon_0
  slv


Parameters

generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_prbs_pattern_checker

prbs_pattern_checker v1.1
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_prbs_pattern_checker
  csr
mSGDMA_0_dma_read_master Data_Source  
  st_pattern_input
mSGDMA_0_clk clk  
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_prbs_pattern_generator

prbs_pattern_generator v1.1
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_prbs_pattern_generator
  csr
mSGDMA_0_clk clk  
  clock
clk_reset  
  reset
st_pattern_output   mSGDMA_0_timing_adapter
  in


Parameters

generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_status_mon_0

status_mon v1.0
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_status_mon_0
  slv
mSGDMA_0_clk clk  
  clock
clk_reset  
  reset_n
master_driver_msgdma_0 cal_fail  
  cal_fail_mon
cal_success  
  cal_success_mon
status   emif_s10_0
  status


Parameters

generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_timer_0

altera_avalon_timer v17.1
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_timer_0
  s1
mSGDMA_0_clk_0 clk  
  clk
mSGDMA_0_clk clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0

mSGDMA_0_timing_adapter

timing_adapter v17.1
mSGDMA_0_prbs_pattern_generator st_pattern_output   mSGDMA_0_timing_adapter
  in
mSGDMA_0_clk clk  
  clk
clk_reset  
  reset
out   mSGDMA_0_dma_write_master
  Data_Sink


Parameters

generateLegacySim false
  

Software Assignments

(none)
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