pfl2

2017.05.14.19:50:33 Datasheet
Overview

Memory Map

parallel_flash_loader_2_0

altera_parallel_flash_loader_2 v17.0


Parameters

INTENDED_DEVICE_FAMILY MAXV
OPERATING_MODE Flash Programming and FPGA Configuration
FLASH_TYPE_UI CFI Parallel Flash
TRISTATE_CHECKBOX true
NUM_FLASH 1
FLASH_DEVICE_DENSITY CFI 1 Gbit
FLASH_DATA_WIDTH_UI 16 bits
FLASH_NRESET_CHECK true
FLASH_NRESET true
ENHANCED_FLASH_PROGRAMMING_UI Area
FIFO_SIZE_UI 16
DISABLE_CRC_CHECK true
CLOCK_FREQUENCY 50.0
FLASH_ACCESS_TIME 100
OPTION_BIT_ADDRESS 786432
FPGA_CONF_SCHEME AvST x16
SAFE_MODE Retry same page
SAFE_MODE_REVERT_ADDR_UI 0
RECONFIGURE_CHECKBOX true
RSU_WATCHDOG_CHECKBOX false
RSU_WATCHDOG_ENABLE false
RSU_WATCHDOG_COUNTER_UI 100.0
READ_MODES Normal Mode
LATENCY_COUNT 5
READY_LATENCY 4
ADDR_WIDTH 26
FLASH_DATA_WIDTH 16
N_FLASH 1
FLASH_NRESET_CHECKBOX 1
EXTRA_ADDR_BYTE 0
FIFO_SIZE 16
DISABLE_CRC_CHECKBOX false
CLK_DIVISOR 4
PAGE_CLK_DIVISOR 1
FLASH_NRESET_COUNTER 2500
NORMAL_MODE 1
BURST_MODE 0
PAGE_MODE 0
BURST_MODE_SPANSION 0
BURST_MODE_INTEL 0
BURST_MODE_LATENCY_COUNT 5
BURST_MODE_NUMONYX 0
FLASH_BURST_EXTRA_CYCLE 0
FLASH_STATIC_WAIT_WIDTH 15
CONF_DATA_WIDTH 16
OPTION_START_ADDR 786432
CONF_WAIT_TIMER_WIDTH 19
SAFE_MODE_HALT 0
SAFE_MODE_RETRY 1
SAFE_MODE_REVERT 0
SAFE_MODE_REVERT_ADDR 0
PFL_RSU_WATCHDOG_ENABLED false
RSU_WATCHDOG_COUNTER 100000000
READY_SYNC_STAGES 2
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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