pcie_xcvr_test_xcvr_native_s10_htile_0

2017.11.13.11:14:15 Datasheet
Overview

All Components
   pcie_xcvr_test_xcvr_native_s10_htile_0 altera_xcvr_native_s10_htile 17.1
Memory Map
  pcie_xcvr_test_xcvr_native_s10_htile_0
reconfig_avmm 

pcie_xcvr_test_xcvr_native_s10_htile_0

altera_xcvr_native_s10_htile v17.1


Parameters

rcfg_enable 1
rcfg_jtag_enable 1
rcfg_separate_avmm_busy 0
set_capability_reg_enable 1
set_user_identifier 0
set_csr_soft_logic_enable 1
rcfg_file_prefix altera_xcvr_rcfg_10
rcfg_sv_file_enable 0
rcfg_h_file_enable 0
rcfg_mif_file_enable 0
rcfg_multi_enable 0
set_rcfg_emb_strm_enable 0
rcfg_reduced_files_enable 0
rcfg_profile_cnt 2
rcfg_profile_select 1
rcfg_profile_data0
rcfg_profile_data1
rcfg_profile_data2
rcfg_profile_data3
rcfg_profile_data4
rcfg_profile_data5
rcfg_profile_data6
rcfg_profile_data7
message_level error
reduced_reset_sim_time 0
channel_type GX
protocol_mode basic_enh
pma_mode basic
duplex_mode duplex
channels 1
set_data_rate 8000
rcfg_iface_enable 0
enable_simple_interface 1
enable_double_rate_transfer 0
bonded_mode not_bonded
set_pcs_bonding_master Auto
pcs_bonding_master 0
pcs_reset_sequencing_mode not_bonded
tx_pma_clk_div 1
plls 1
pll_select 0
enable_port_tx_pma_iqtxrx_clkout 0
enable_port_tx_pma_elecidle 0
cdr_refclk_cnt 1
cdr_refclk_select 0
set_cdr_refclk_freq 100.000000
rx_ppm_detect_threshold 1000
enable_port_rx_pma_iqtxrx_clkout 0
enable_port_rx_pma_clkslip 0
enable_port_rx_is_lockedtodata 1
enable_port_rx_is_lockedtoref 1
enable_ports_rx_manual_cdr_mode 0
enable_ports_rx_prbs 0
enable_port_rx_seriallpbken 1
enh_pcs_pma_width 64
enh_pld_pcs_width 64
enh_low_latency_enable 0
enh_tx_frmgen_enable 0
enh_tx_frmgen_mfrm_length 2048
enh_tx_frmgen_burst_enable 0
enable_port_tx_enh_frame 0
enable_port_tx_enh_frame_diag_status 0
enable_port_tx_enh_frame_burst_en 0
enh_rx_frmsync_enable 0
enh_rx_frmsync_mfrm_length 2048
enable_port_rx_enh_frame 0
enable_port_rx_enh_frame_lock 0
enable_port_rx_enh_frame_diag_status 0
enh_tx_crcgen_enable 0
enh_tx_crcerr_enable 0
enh_rx_crcchk_enable 0
enable_port_rx_enh_crc32_err 0
enable_port_rx_enh_highber 0
enable_port_rx_enh_highber_clr_cnt 0
enable_port_rx_enh_clr_errblk_count 0
enh_tx_64b66b_enable 0
enh_rx_64b66b_enable 0
enh_tx_sh_err 0
enh_tx_scram_enable 0
enh_tx_scram_seed 0
enh_rx_descram_enable 0
enh_tx_dispgen_enable 0
enh_rx_dispchk_enable 0
enh_tx_randomdispbit_enable 0
enh_rx_blksync_enable 0
enable_port_rx_enh_blk_lock 0
enh_tx_bitslip_enable 0
enh_tx_polinv_enable 0
enh_rx_bitslip_enable 0
enh_rx_polinv_enable 0
enable_port_tx_enh_bitslip 0
enable_port_rx_enh_bitslip 0
enh_rx_krfec_err_mark_enable 0
enh_rx_krfec_err_mark_type 10G
enh_tx_krfec_burst_err_enable 0
enh_tx_krfec_burst_err_len 1
enable_port_krfec_tx_enh_frame 0
enable_port_krfec_rx_enh_frame 0
enable_port_krfec_rx_enh_frame_diag_status 0
enable_debug_ports 0
tx_fifo_mode Phase compensation
tx_fifo_pfull 10
tx_fifo_pempty 2
enable_port_tx_fifo_full 0
enable_port_tx_fifo_empty 0
enable_port_tx_fifo_pfull 0
enable_port_tx_fifo_pempty 0
enable_port_tx_dll_lock 0
rx_fifo_mode Phase compensation
rx_fifo_pfull 10
rx_fifo_pempty 2
rx_fifo_align_del 0
rx_fifo_control_del 0
enable_port_rx_data_valid 0
enable_port_rx_fifo_full 0
enable_port_rx_fifo_empty 0
enable_port_rx_fifo_pfull 0
enable_port_rx_fifo_pempty 0
enable_port_rx_fifo_del 0
enable_port_rx_fifo_insert 0
enable_port_rx_fifo_rd_en 0
enable_port_rx_fifo_align_clr 0
tx_clkout_sel pcs_clkout
enable_port_tx_clkout2 1
tx_clkout2_sel pma_div_clkout
tx_pma_div_clkout_divider 2
tx_coreclkin_clock_network dedicated
rx_clkout_sel pcs_clkout
enable_port_rx_clkout2 1
rx_clkout2_sel pma_div_clkout
rx_pma_div_clkout_divider 2
rx_coreclkin_clock_network dedicated
enable_port_latency_measurement 0
generate_docs 1
enable_tx_coreclkin2 0
rcfg_shared 0
set_prbs_soft_logic_enable 1
enable_rcfg_tx_digitalreset_release_ctrl 0
tx_pll_type ATX
tx_pll_refclk 125.0
use_tx_clkout2 0
use_rx_clkout2 0
enable_fast_sim 0
design_example_filename top
anlg_voltage 1_0V
anlg_link sr
qsf_assignments_enable 0
qsf_assignments_list
tx_pma_analog_mode user_custom
rx_pma_analog_mode user_custom
tx_pma_optimal_settings 1
tx_pma_output_swing_ctrl 12
tx_pma_pre_emp_sign_pre_tap_1t negative
tx_pma_pre_emp_switching_ctrl_pre_tap_1t 0
tx_pma_pre_emp_sign_1st_post_tap negative
tx_pma_pre_emp_switching_ctrl_1st_post_tap 0
tx_pma_slew_rate_ctrl 0
tx_pma_term_sel r_r1
tx_pma_compensation_en enable
rx_pma_optimal_settings 1
rx_pma_adapt_mode manual
rx_pma_term_sel r_r1
rx_ctle_ac_gain 0
rx_ctle_eq_gain 0
rx_vga_dc_gain 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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