fmc_xcvr_system

2017.11.13.11:25:56 Datasheet
Overview
  clk_100  fmc_xcvr_system
  clk_50 
  fmc_cmos_system_0_clkin 
  fmc_cmos_system_0_fmc_cmos_system_0_clk_50 
  fmc_xcvr_system_bank_4c_0_clk_100 
  fmc_xcvr_system_bank_4c_0_clk_50 
  fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4c_1_clk_100 
  fmc_xcvr_system_bank_4c_1_clk_50 
  fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4c_2_clk_100 
  fmc_xcvr_system_bank_4c_2_clk_50 
  fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4c_3_clk_100 
  fmc_xcvr_system_bank_4c_3_clk_50 
  fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4c_4_clk_100 
  fmc_xcvr_system_bank_4c_4_clk_50 
  fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4c_5_clk_100 
  fmc_xcvr_system_bank_4c_5_clk_50 
  fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4d_0_clk_100 
  fmc_xcvr_system_bank_4d_0_clk_50 
  fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4d_1_clk_100 
  fmc_xcvr_system_bank_4d_1_clk_50 
  fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4d_2_clk_100 
  fmc_xcvr_system_bank_4d_2_clk_50 
  fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4d_3_clk_100 
  fmc_xcvr_system_bank_4d_3_clk_50 
  fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4d_4_clk_100 
  fmc_xcvr_system_bank_4d_4_clk_50 
  fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4d_5_clk_100 
  fmc_xcvr_system_bank_4d_5_clk_50 
  fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4e_0_clk_100 
  fmc_xcvr_system_bank_4e_0_clk_50 
  fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4e_1_clk_100 
  fmc_xcvr_system_bank_4e_1_clk_50 
  fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4e_2_clk_100 
  fmc_xcvr_system_bank_4e_2_clk_50 
  fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_clk_50 
  fmc_xcvr_system_bank_4e_3_clk_100 
  fmc_xcvr_system_bank_4e_3_clk_50 
  fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_clk_50 

All Components
   product_info_0 product_info 1.0
   xcvr_atx_pll_4c altera_xcvr_atx_pll_s10_htile 17.1
   fmc_cmos_system_0 fmc_cmos_system 1.0
   fmc_cmos_system_0_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_cmos_system_0_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_cmos_system_0_pio_0 altera_avalon_pio 17.1
   fmc_cmos_system_0_fmc_cmos_system_0 cmos_test_system 1.0
   fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_cmos_system_0_fmc_cmos_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4c_0 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4c_0_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4c_0_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4c_0_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4c_1 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4c_1_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4c_1_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4c_1_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4c_2 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4c_2_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4c_2_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4c_2_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4c_3 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4c_3_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4c_3_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4c_3_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4c_4 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4c_4_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4c_4_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4c_4_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4c_5 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4c_5_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4c_5_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4c_5_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4d_0 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4d_0_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4d_0_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4d_0_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4d_1 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4d_1_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4d_1_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4d_1_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4d_2 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4d_2_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4d_2_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4d_2_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4d_3 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4d_3_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4d_3_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4d_3_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4d_4 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4d_4_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4d_4_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4d_4_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4d_5 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4d_5_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4d_5_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4d_5_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4e_0 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4e_0_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4e_0_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4e_0_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4e_1 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4e_1_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4e_1_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4e_1_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4e_2 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4e_2_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4e_2_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4e_2_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   fmc_xcvr_system_bank_4e_3 fmc_xcvr_test 1.0
   fmc_xcvr_system_bank_4e_3_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   fmc_xcvr_system_bank_4e_3_mm_bridge_0 altera_avalon_mm_bridge 17.1
   fmc_xcvr_system_bank_4e_3_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0 xcvr_test_system 1.0
   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
Memory Map
master_0 fmc_xcvr_system_bank_4c_0_default_pma_settings_conf_0 fmc_xcvr_system_bank_4c_1_default_pma_settings_conf_0 fmc_xcvr_system_bank_4c_2_default_pma_settings_conf_0 fmc_xcvr_system_bank_4c_3_default_pma_settings_conf_0 fmc_xcvr_system_bank_4c_4_default_pma_settings_conf_0 fmc_xcvr_system_bank_4c_5_default_pma_settings_conf_0 fmc_xcvr_system_bank_4d_0_default_pma_settings_conf_0 fmc_xcvr_system_bank_4d_1_default_pma_settings_conf_0 fmc_xcvr_system_bank_4d_2_default_pma_settings_conf_0 fmc_xcvr_system_bank_4d_3_default_pma_settings_conf_0 fmc_xcvr_system_bank_4d_4_default_pma_settings_conf_0 fmc_xcvr_system_bank_4d_5_default_pma_settings_conf_0 fmc_xcvr_system_bank_4e_0_default_pma_settings_conf_0 fmc_xcvr_system_bank_4e_1_default_pma_settings_conf_0 fmc_xcvr_system_bank_4e_2_default_pma_settings_conf_0 fmc_xcvr_system_bank_4e_3_default_pma_settings_conf_0
 master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master
  product_info_0
avalon_slave_0  0x00000000
  xcvr_atx_pll_4c
reconfig_avmm0  0x01000000
  fmc_cmos_system_0
mm_bridge_0_s0 
  fmc_cmos_system_0_nativePHY_loopback_cont_0
csr  0x02000300
  fmc_cmos_system_0_pio_0
s1  0x02000400
  fmc_cmos_system_0_fmc_cmos_system_0
mm_bridge_0_s0 
  fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_checker_0
csr_slave  0x02011020
  fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_generator_0
csr_slave  0x02011000
  fmc_xcvr_system_bank_4c_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4c_0_default_pma_settings_conf_0
avalon_slave  0x00012000
  fmc_xcvr_system_bank_4c_0_nativePHY_loopback_cont_0
csr  0x00013000
  fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0
reconfig_avmm  0x00010000 0x00000000
  fmc_xcvr_system_bank_4c_0_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00015020
  fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00015000
  fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_freq_counter_0
csr  0x00015200
  fmc_xcvr_system_bank_4c_1
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4c_1_default_pma_settings_conf_0
avalon_slave  0x00022000
  fmc_xcvr_system_bank_4c_1_nativePHY_loopback_cont_0
csr  0x00023000
  fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0
reconfig_avmm  0x00020000 0x00000000
  fmc_xcvr_system_bank_4c_1_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00025020
  fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00025000
  fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_freq_counter_0
csr  0x00025200
  fmc_xcvr_system_bank_4c_2
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4c_2_default_pma_settings_conf_0
avalon_slave  0x00032000
  fmc_xcvr_system_bank_4c_2_nativePHY_loopback_cont_0
csr  0x00033000
  fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0
reconfig_avmm  0x00030000 0x00000000
  fmc_xcvr_system_bank_4c_2_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00035020
  fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00035000
  fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_freq_counter_0
csr  0x00035200
  fmc_xcvr_system_bank_4c_3
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4c_3_default_pma_settings_conf_0
avalon_slave  0x00042000
  fmc_xcvr_system_bank_4c_3_nativePHY_loopback_cont_0
csr  0x00043000
  fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0
reconfig_avmm  0x00040000 0x00000000
  fmc_xcvr_system_bank_4c_3_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00045020
  fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00045000
  fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_freq_counter_0
csr  0x00045200
  fmc_xcvr_system_bank_4c_4
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4c_4_default_pma_settings_conf_0
avalon_slave  0x00052000
  fmc_xcvr_system_bank_4c_4_nativePHY_loopback_cont_0
csr  0x00053000
  fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0
reconfig_avmm  0x00050000 0x00000000
  fmc_xcvr_system_bank_4c_4_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00055020
  fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00055000
  fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_freq_counter_0
csr  0x00055200
  fmc_xcvr_system_bank_4c_5
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4c_5_default_pma_settings_conf_0
avalon_slave  0x00062000
  fmc_xcvr_system_bank_4c_5_nativePHY_loopback_cont_0
csr  0x00063000
  fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0
reconfig_avmm  0x00060000 0x00000000
  fmc_xcvr_system_bank_4c_5_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00065020
  fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00065000
  fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_freq_counter_0
csr  0x00065200
  fmc_xcvr_system_bank_4d_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4d_0_default_pma_settings_conf_0
avalon_slave  0x00072000
  fmc_xcvr_system_bank_4d_0_nativePHY_loopback_cont_0
csr  0x00073000
  fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0
reconfig_avmm  0x00070000 0x00000000
  fmc_xcvr_system_bank_4d_0_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00075020
  fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00075000
  fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_freq_counter_0
csr  0x00075200
  fmc_xcvr_system_bank_4d_1
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4d_1_default_pma_settings_conf_0
avalon_slave  0x00082000
  fmc_xcvr_system_bank_4d_1_nativePHY_loopback_cont_0
csr  0x00083000
  fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0
reconfig_avmm  0x00080000 0x00000000
  fmc_xcvr_system_bank_4d_1_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00085020
  fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00085000
  fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_freq_counter_0
csr  0x00085200
  fmc_xcvr_system_bank_4d_2
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4d_2_default_pma_settings_conf_0
avalon_slave  0x00092000
  fmc_xcvr_system_bank_4d_2_nativePHY_loopback_cont_0
csr  0x00093000
  fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0
reconfig_avmm  0x00090000 0x00000000
  fmc_xcvr_system_bank_4d_2_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00095020
  fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00095000
  fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_freq_counter_0
csr  0x00095200
  fmc_xcvr_system_bank_4d_3
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4d_3_default_pma_settings_conf_0
avalon_slave  0x000a2000
  fmc_xcvr_system_bank_4d_3_nativePHY_loopback_cont_0
csr  0x000a3000
  fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0
reconfig_avmm  0x000a0000 0x00000000
  fmc_xcvr_system_bank_4d_3_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x000a5020
  fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x000a5000
  fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_freq_counter_0
csr  0x000a5200
  fmc_xcvr_system_bank_4d_4
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4d_4_default_pma_settings_conf_0
avalon_slave  0x000b2000
  fmc_xcvr_system_bank_4d_4_nativePHY_loopback_cont_0
csr  0x000b3000
  fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0
reconfig_avmm  0x000b0000 0x00000000
  fmc_xcvr_system_bank_4d_4_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x000b5020
  fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x000b5000
  fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_freq_counter_0
csr  0x000b5200
  fmc_xcvr_system_bank_4d_5
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4d_5_default_pma_settings_conf_0
avalon_slave  0x000c2000
  fmc_xcvr_system_bank_4d_5_nativePHY_loopback_cont_0
csr  0x000c3000
  fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0
reconfig_avmm  0x000c0000 0x00000000
  fmc_xcvr_system_bank_4d_5_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x000c5020
  fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x000c5000
  fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_freq_counter_0
csr  0x000c5200
  fmc_xcvr_system_bank_4e_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4e_0_default_pma_settings_conf_0
avalon_slave  0x000d2000
  fmc_xcvr_system_bank_4e_0_nativePHY_loopback_cont_0
csr  0x000d3000
  fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0
reconfig_avmm  0x000d0000 0x00000000
  fmc_xcvr_system_bank_4e_0_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x000d5020
  fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x000d5000
  fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_freq_counter_0
csr  0x000d5200
  fmc_xcvr_system_bank_4e_1
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4e_1_default_pma_settings_conf_0
avalon_slave  0x000e2000
  fmc_xcvr_system_bank_4e_1_nativePHY_loopback_cont_0
csr  0x000e3000
  fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0
reconfig_avmm  0x000e0000 0x00000000
  fmc_xcvr_system_bank_4e_1_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x000e5020
  fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x000e5000
  fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_freq_counter_0
csr  0x000e5200
  fmc_xcvr_system_bank_4e_2
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4e_2_default_pma_settings_conf_0
avalon_slave  0x000f2000
  fmc_xcvr_system_bank_4e_2_nativePHY_loopback_cont_0
csr  0x000f3000
  fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0
reconfig_avmm  0x000f0000 0x00000000
  fmc_xcvr_system_bank_4e_2_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x000f5020
  fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x000f5000
  fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_freq_counter_0
csr  0x000f5200
  fmc_xcvr_system_bank_4e_3
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4e_3_default_pma_settings_conf_0
avalon_slave  0x00102000
  fmc_xcvr_system_bank_4e_3_nativePHY_loopback_cont_0
csr  0x00103000
  fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0
reconfig_avmm  0x00100000 0x00000000
  fmc_xcvr_system_bank_4e_3_xcvr_test_system_0
mm_bridge_0_s0 
  fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00105020
  fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00105000
  fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_freq_counter_0
csr  0x00105200

atx_pll_4c_refclk

altera_clock_bridge v17.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

clk_100

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

clk_50

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_pll_status

pll_status_interconnect v1.0
xcvr_atx_pll_4c pll_locked   fmc_xcvr_system_pll_status
  pll_locked
fmc_xcvr_system_bank_4c_0_pll_locked_status pll_locked  
  pll_locked_a
fmc_xcvr_system_bank_4c_2_pll_locked_status pll_locked  
  pll_locked_c
fmc_xcvr_system_bank_4c_4_pll_locked_status pll_locked  
  pll_locked_e
fmc_xcvr_system_bank_4d_0_pll_locked_status pll_locked  
  pll_locked_g
fmc_xcvr_system_bank_4d_2_pll_locked_status pll_locked  
  pll_locked_i
fmc_xcvr_system_bank_4d_4_pll_locked_status pll_locked  
  pll_locked_k
fmc_xcvr_system_bank_4e_0_pll_locked_status pll_locked  
  pll_locked_m
fmc_xcvr_system_bank_4e_2_pll_locked_status pll_locked  
  pll_locked_o
pll_locked_b   fmc_xcvr_system_bank_4c_1_pll_locked_status
  pll_locked
pll_locked_d   fmc_xcvr_system_bank_4c_3_pll_locked_status
  pll_locked
pll_locked_f   fmc_xcvr_system_bank_4c_5_pll_locked_status
  pll_locked
pll_locked_h   fmc_xcvr_system_bank_4d_1_pll_locked_status
  pll_locked
pll_locked_j   fmc_xcvr_system_bank_4d_3_pll_locked_status
  pll_locked
pll_locked_l   fmc_xcvr_system_bank_4d_5_pll_locked_status
  pll_locked
pll_locked_n   fmc_xcvr_system_bank_4e_1_pll_locked_status
  pll_locked
pll_locked_p   fmc_xcvr_system_bank_4e_3_pll_locked_status
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

master_0

altera_jtag_avalon_master v17.1
clk_50 clk   master_0
  clk
clk_reset  
  clk_reset
master   product_info_0
  avalon_slave_0
master_reset  
  reset
master   fmc_cmos_system_0_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4c_0_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4c_1_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4c_2_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4c_3_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4c_4_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4c_5_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4d_0_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4d_1_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4d_2_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4d_3_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4d_4_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4d_5_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4e_0_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4e_1_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4e_2_mm_bridge_0
  s0
master   fmc_xcvr_system_bank_4e_3_mm_bridge_0
  s0
master   xcvr_atx_pll_4c
  reconfig_avmm0
master_reset   fmc_xcvr_system_bank_4c_0_clk_100
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4c_1_clk_100
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4c_2_clk_100
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4c_3_clk_100
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4c_4_clk_100
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4c_5_clk_100
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4d_0_clk_100
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4d_2_clk_100
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4d_3_clk_100
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4d_4_clk_100
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4d_5_clk_100
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4e_2_clk_100
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4e_3_clk_100
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4c_0_clk_50
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4c_1_clk_50
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4c_2_clk_50
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4c_3_clk_50
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4c_4_clk_50
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4c_5_clk_50
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4d_1_clk_50
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4d_2_clk_50
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4d_3_clk_50
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4d_4_clk_50
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4d_5_clk_50
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4e_1_clk_50
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4e_2_clk_50
  clk_in_reset
master_reset   fmc_xcvr_system_bank_4e_3_clk_50
  clk_in_reset
master_reset   fmc_cmos_system_0_clkin
  clk_in_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

product_info_0

product_info v1.0
master_0 master   product_info_0
  avalon_slave_0
master_reset  
  reset
clk_50 clk  
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_atx_pll_4c

altera_xcvr_atx_pll_s10_htile v17.1
master_0 master   xcvr_atx_pll_4c
  reconfig_avmm0
clk_100 clk  
  reconfig_clk0
clk_reset  
  reconfig_reset0
atx_pll_4c_refclk out_clk  
  pll_refclk0
pll_locked   fmc_xcvr_system_pll_status
  pll_locked
mcgb_serial_clk   fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk   fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk   fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk   fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk   fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk   fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk   fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0
  tx_serial_clk0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0

fmc_cmos_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0_clkin

clock_source vnull
clk_50 clk   fmc_cmos_system_0_clkin
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_cmos_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_cmos_system_0_pio_0
  clk
clk_reset  
  reset
clk   fmc_cmos_system_0_fmc_cmos_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_cmos_system_0_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset
clk   fmc_cmos_system_0_xcvr_st_converter_0
  rx_clkout
clk  
  tx_clkout


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_cmos_system_0_clkin clk   fmc_cmos_system_0_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_cmos_system_0_nativePHY_loopback_cont_0
  csr
m0   fmc_cmos_system_0_fmc_cmos_system_0_mm_bridge_0
  s0
m0   fmc_cmos_system_0_pio_0
  s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_cmos_system_0_mm_bridge_0 m0   fmc_cmos_system_0_nativePHY_loopback_cont_0
  csr
fmc_cmos_system_0_clkin clk  
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0_pio_0

altera_avalon_pio v17.1
fmc_cmos_system_0_mm_bridge_0 m0   fmc_cmos_system_0_pio_0
  s1
fmc_cmos_system_0_clkin clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 32
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 4294967295

fmc_cmos_system_0_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_cmos_system_0_clkin clk   fmc_cmos_system_0_xcvr_st_converter_0
  rx_clkout
clk  
  tx_clkout
fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_checker_0 conduit_pattern_in  
  rx_data_a
conduit_pattern_in_clk  
  rx_clkout_a
fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_generator_0 conduit_pattern_out  
  tx_data_a
conduit_pattern_out_clk  
  tx_clkout_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0_fmc_cmos_system_0

cmos_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0_fmc_cmos_system_0_clk_50

clock_source vnull
fmc_cmos_system_0_clkin clk   fmc_cmos_system_0_fmc_cmos_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_cmos_system_0_fmc_cmos_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_cmos_system_0_fmc_cmos_system_0_mm_bridge_0 m0   fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_checker_0
  csr_slave
fmc_cmos_system_0_fmc_cmos_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
conduit_pattern_in   fmc_cmos_system_0_xcvr_st_converter_0
  rx_data_a
conduit_pattern_in_clk  
  rx_clkout_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_cmos_system_0_fmc_cmos_system_0_mm_bridge_0 m0   fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_generator_0
  csr_slave
fmc_cmos_system_0_fmc_cmos_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
conduit_pattern_out   fmc_cmos_system_0_xcvr_st_converter_0
  tx_data_a
conduit_pattern_out_clk  
  tx_clkout_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_cmos_system_0_fmc_cmos_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_cmos_system_0_fmc_cmos_system_0_clk_50 clk   fmc_cmos_system_0_fmc_cmos_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_cmos_system_0_mm_bridge_0 m0  
  s0
m0   fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_cmos_system_0_fmc_cmos_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4c_0_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4c_0_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4c_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_0_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4c_0_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_0_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4c_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_0_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4c_0_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4c_0_clk_50 clk   fmc_xcvr_system_bank_4c_0_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4c_0_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4c_0_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4c_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_0_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4c_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4c_0_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4c_0_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4c_0_pll_locked_status
  pll_locked_a
pll_locked_output   fmc_xcvr_system_bank_4c_0_nativePHY_loopback_cont_0
  pll_locked
pll_locked   fmc_xcvr_system_pll_status
  pll_locked_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4c_0_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4c_0_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4c_0_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4c_0_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4c_0_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c tx_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4c_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4c_0_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4c_0_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4c_0_clk_50 clk   fmc_xcvr_system_bank_4c_0_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4c_0_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4c_0_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4c_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4c_0_clk_50 clk   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_0_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4c_0_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4c_0_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4c_0_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4c_0_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4c_0_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4c_0_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4c_1_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4c_1_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4c_1_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_1_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_1_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4c_1_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_1_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4c_1_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_1_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4c_1_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4c_1_clk_50 clk   fmc_xcvr_system_bank_4c_1_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4c_1_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4c_1_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4c_1_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_1_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4c_1_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4c_1_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4c_1_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4c_1_pll_locked_status
  pll_locked_a
fmc_xcvr_system_pll_status pll_locked_b  
  pll_locked
pll_locked_output   fmc_xcvr_system_bank_4c_1_nativePHY_loopback_cont_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4c_1_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4c_1_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4c_1_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4c_1_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4c_1_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c tx_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4c_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4c_1_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4c_1_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4c_1_clk_50 clk   fmc_xcvr_system_bank_4c_1_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4c_1_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4c_1_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4c_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4c_1_clk_50 clk   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_1_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4c_1_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4c_1_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4c_1_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4c_1_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4c_1_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4c_1_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4c_2_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4c_2_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4c_2_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_2_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_2_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4c_2_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_2_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4c_2_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_2_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4c_2_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4c_2_clk_50 clk   fmc_xcvr_system_bank_4c_2_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4c_2_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4c_2_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4c_2_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_2_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4c_2_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4c_2_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4c_2_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4c_2_pll_locked_status
  pll_locked_a
pll_locked_output   fmc_xcvr_system_bank_4c_2_nativePHY_loopback_cont_0
  pll_locked
pll_locked   fmc_xcvr_system_pll_status
  pll_locked_c


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4c_2_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4c_2_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4c_2_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4c_2_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4c_2_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c tx_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4c_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4c_2_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4c_2_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4c_2_clk_50 clk   fmc_xcvr_system_bank_4c_2_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4c_2_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4c_2_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4c_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4c_2_clk_50 clk   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_2_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4c_2_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4c_2_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4c_2_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4c_2_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4c_2_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4c_2_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4c_3_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4c_3_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4c_3_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_3_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_3_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4c_3_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_3_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4c_3_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_3_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4c_3_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4c_3_clk_50 clk   fmc_xcvr_system_bank_4c_3_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4c_3_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4c_3_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4c_3_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_3_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4c_3_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4c_3_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4c_3_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4c_3_pll_locked_status
  pll_locked_a
fmc_xcvr_system_pll_status pll_locked_d  
  pll_locked
pll_locked_output   fmc_xcvr_system_bank_4c_3_nativePHY_loopback_cont_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4c_3_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4c_3_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4c_3_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4c_3_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4c_3_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c tx_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4c_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4c_3_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4c_3_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4c_3_clk_50 clk   fmc_xcvr_system_bank_4c_3_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4c_3_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4c_3_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4c_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4c_3_clk_50 clk   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_3_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4c_3_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4c_3_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4c_3_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4c_3_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4c_3_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4c_3_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4c_4_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4c_4_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4c_4_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_4_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_4_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4c_4_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_4_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4c_4_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_4_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4c_4_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4c_4_clk_50 clk   fmc_xcvr_system_bank_4c_4_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4c_4_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4c_4_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4c_4_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_4_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4c_4_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4c_4_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4c_4_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4c_4_pll_locked_status
  pll_locked_a
pll_locked_output   fmc_xcvr_system_bank_4c_4_nativePHY_loopback_cont_0
  pll_locked
pll_locked   fmc_xcvr_system_pll_status
  pll_locked_e


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4c_4_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4c_4_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4c_4_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4c_4_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4c_4_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c tx_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4c_4_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4c_4_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4c_4_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4c_4_clk_50 clk   fmc_xcvr_system_bank_4c_4_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4c_4_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4c_4_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4c_4_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4c_4_clk_50 clk   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_4_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4c_4_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4c_4_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4c_4_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4c_4_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4c_4_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4c_4_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4c_5_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4c_5_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4c_5_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_5_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_5_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4c_5_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_5_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4c_5_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_5_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4c_5_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4c_5_clk_50 clk   fmc_xcvr_system_bank_4c_5_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4c_5_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4c_5_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4c_5_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_5_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4c_5_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4c_5_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4c_5_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4c_5_pll_locked_status
  pll_locked_a
fmc_xcvr_system_pll_status pll_locked_f  
  pll_locked
pll_locked_output   fmc_xcvr_system_bank_4c_5_nativePHY_loopback_cont_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4c_5_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4c_5_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4c_5_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4c_5_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4c_5_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c tx_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4c_5_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4c_5_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4c_5_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4c_5_clk_50 clk   fmc_xcvr_system_bank_4c_5_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4c_5_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4c_5_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4c_5_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4c_5_clk_50 clk   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4c_5_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4c_5_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4c_5_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4c_5_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4c_5_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4c_5_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4c_5_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4d_0_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4d_0_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4d_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_0_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4d_0_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_0_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4d_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_0_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4d_0_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4d_0_clk_50 clk   fmc_xcvr_system_bank_4d_0_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4d_0_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4d_0_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4d_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_0_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4d_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4d_0_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4d_0_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4d_0_pll_locked_status
  pll_locked_a
pll_locked_output   fmc_xcvr_system_bank_4d_0_nativePHY_loopback_cont_0
  pll_locked
pll_locked   fmc_xcvr_system_pll_status
  pll_locked_g


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4d_0_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4d_0_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4d_0_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4d_0_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4d_0_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4d_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4d_0_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4d_0_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4d_0_clk_50 clk   fmc_xcvr_system_bank_4d_0_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4d_0_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4d_0_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4d_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4d_0_clk_50 clk   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_0_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4d_0_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4d_0_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4d_0_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4d_0_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4d_0_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4d_0_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4d_1_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4d_1_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4d_1_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_1_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_1_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4d_1_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_1_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4d_1_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_1_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4d_1_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4d_1_clk_50 clk   fmc_xcvr_system_bank_4d_1_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4d_1_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4d_1_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4d_1_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_1_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4d_1_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4d_1_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4d_1_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4d_1_pll_locked_status
  pll_locked_a
fmc_xcvr_system_pll_status pll_locked_h  
  pll_locked
pll_locked_output   fmc_xcvr_system_bank_4d_1_nativePHY_loopback_cont_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4d_1_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4d_1_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4d_1_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4d_1_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4d_1_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4d_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4d_1_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4d_1_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4d_1_clk_50 clk   fmc_xcvr_system_bank_4d_1_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4d_1_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4d_1_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4d_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4d_1_clk_50 clk   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_1_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4d_1_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4d_1_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4d_1_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4d_1_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4d_1_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4d_1_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4d_2_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4d_2_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4d_2_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_2_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_2_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4d_2_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_2_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4d_2_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_2_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4d_2_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4d_2_clk_50 clk   fmc_xcvr_system_bank_4d_2_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4d_2_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4d_2_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4d_2_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_2_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4d_2_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4d_2_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4d_2_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4d_2_pll_locked_status
  pll_locked_a
pll_locked_output   fmc_xcvr_system_bank_4d_2_nativePHY_loopback_cont_0
  pll_locked
pll_locked   fmc_xcvr_system_pll_status
  pll_locked_i


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4d_2_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4d_2_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4d_2_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4d_2_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4d_2_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4d_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4d_2_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4d_2_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4d_2_clk_50 clk   fmc_xcvr_system_bank_4d_2_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4d_2_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4d_2_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4d_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4d_2_clk_50 clk   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_2_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4d_2_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4d_2_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4d_2_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4d_2_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4d_2_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4d_2_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4d_3_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4d_3_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4d_3_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_3_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_3_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4d_3_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_3_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4d_3_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_3_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4d_3_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4d_3_clk_50 clk   fmc_xcvr_system_bank_4d_3_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4d_3_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4d_3_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4d_3_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_3_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4d_3_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4d_3_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4d_3_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4d_3_pll_locked_status
  pll_locked_a
fmc_xcvr_system_pll_status pll_locked_j  
  pll_locked
pll_locked_output   fmc_xcvr_system_bank_4d_3_nativePHY_loopback_cont_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4d_3_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4d_3_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4d_3_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4d_3_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4d_3_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4d_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4d_3_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4d_3_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4d_3_clk_50 clk   fmc_xcvr_system_bank_4d_3_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4d_3_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4d_3_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4d_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4d_3_clk_50 clk   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_3_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4d_3_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4d_3_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4d_3_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4d_3_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4d_3_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4d_3_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4d_4_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4d_4_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4d_4_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_4_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_4_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4d_4_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_4_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4d_4_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_4_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4d_4_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4d_4_clk_50 clk   fmc_xcvr_system_bank_4d_4_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4d_4_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4d_4_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4d_4_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_4_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4d_4_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4d_4_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4d_4_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4d_4_pll_locked_status
  pll_locked_a
pll_locked_output   fmc_xcvr_system_bank_4d_4_nativePHY_loopback_cont_0
  pll_locked
pll_locked   fmc_xcvr_system_pll_status
  pll_locked_k


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4d_4_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4d_4_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4d_4_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4d_4_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4d_4_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4d_4_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4d_4_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4d_4_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4d_4_clk_50 clk   fmc_xcvr_system_bank_4d_4_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4d_4_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4d_4_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4d_4_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4d_4_clk_50 clk   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_4_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4d_4_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4d_4_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4d_4_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4d_4_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4d_4_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4d_4_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4d_5_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4d_5_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4d_5_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_5_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_5_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4d_5_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_5_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4d_5_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_5_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4d_5_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4d_5_clk_50 clk   fmc_xcvr_system_bank_4d_5_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4d_5_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4d_5_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4d_5_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_5_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4d_5_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4d_5_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4d_5_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4d_5_pll_locked_status
  pll_locked_a
fmc_xcvr_system_pll_status pll_locked_l  
  pll_locked
pll_locked_output   fmc_xcvr_system_bank_4d_5_nativePHY_loopback_cont_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4d_5_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4d_5_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4d_5_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4d_5_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4d_5_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4d_5_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4d_5_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4d_5_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4d_5_clk_50 clk   fmc_xcvr_system_bank_4d_5_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4d_5_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4d_5_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4d_5_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4d_5_clk_50 clk   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4d_5_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4d_5_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4d_5_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4d_5_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4d_5_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4d_5_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4d_5_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4e_0_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4e_0_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4e_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_0_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4e_0_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_0_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4e_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_0_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4e_0_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4e_0_clk_50 clk   fmc_xcvr_system_bank_4e_0_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4e_0_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4e_0_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4e_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_0_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4e_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4e_0_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4e_0_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4e_0_pll_locked_status
  pll_locked_a
pll_locked_output   fmc_xcvr_system_bank_4e_0_nativePHY_loopback_cont_0
  pll_locked
pll_locked   fmc_xcvr_system_pll_status
  pll_locked_m


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4e_0_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4e_0_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4e_0_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4e_0_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4e_0_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4e_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4e_0_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4e_0_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4e_0_clk_50 clk   fmc_xcvr_system_bank_4e_0_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4e_0_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4e_0_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4e_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4e_0_clk_50 clk   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4e_0_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4e_0_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4e_0_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4e_0_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4e_0_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4e_0_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4e_0_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4e_1_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4e_1_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4e_1_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_1_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_1_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4e_1_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_1_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4e_1_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_1_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4e_1_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4e_1_clk_50 clk   fmc_xcvr_system_bank_4e_1_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4e_1_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4e_1_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4e_1_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_1_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4e_1_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4e_1_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4e_1_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4e_1_pll_locked_status
  pll_locked_a
fmc_xcvr_system_pll_status pll_locked_n  
  pll_locked
pll_locked_output   fmc_xcvr_system_bank_4e_1_nativePHY_loopback_cont_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4e_1_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4e_1_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4e_1_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4e_1_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4e_1_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4e_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4e_1_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4e_1_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4e_1_clk_50 clk   fmc_xcvr_system_bank_4e_1_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4e_1_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4e_1_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4e_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4e_1_clk_50 clk   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4e_1_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4e_1_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4e_1_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4e_1_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4e_1_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4e_1_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4e_1_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4e_2_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4e_2_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4e_2_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_2_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_2_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4e_2_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_2_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4e_2_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_2_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4e_2_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4e_2_clk_50 clk   fmc_xcvr_system_bank_4e_2_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4e_2_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4e_2_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4e_2_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_2_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4e_2_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4e_2_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4e_2_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4e_2_pll_locked_status
  pll_locked_a
pll_locked_output   fmc_xcvr_system_bank_4e_2_nativePHY_loopback_cont_0
  pll_locked
pll_locked   fmc_xcvr_system_pll_status
  pll_locked_o


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4e_2_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4e_2_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4e_2_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4e_2_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4e_2_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4e_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4e_2_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4e_2_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4e_2_clk_50 clk   fmc_xcvr_system_bank_4e_2_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4e_2_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4e_2_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4e_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4e_2_clk_50 clk   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4e_2_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4e_2_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4e_2_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4e_2_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4e_2_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4e_2_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4e_2_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3

fmc_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_clk_100

clock_source vnull
clk_100 clk   fmc_xcvr_system_bank_4e_3_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   fmc_xcvr_system_bank_4e_3_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_clk_50

clock_source vnull
clk_50 clk   fmc_xcvr_system_bank_4e_3_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_3_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_3_xcvr_reset_control_s10_0
  clock
clk   fmc_xcvr_system_bank_4e_3_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_3_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_default_pma_settings_conf_0

default_pma_settings_conf v1.0
fmc_xcvr_system_bank_4e_3_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_3_default_pma_settings_conf_0
  avalon_slave
fmc_xcvr_system_bank_4e_3_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_mm_bridge_0

altera_avalon_mm_bridge v17.1
fmc_xcvr_system_bank_4e_3_clk_50 clk   fmc_xcvr_system_bank_4e_3_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   fmc_xcvr_system_bank_4e_3_default_pma_settings_conf_0
  avalon_slave
m0   fmc_xcvr_system_bank_4e_3_nativePHY_loopback_cont_0
  csr
m0   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_mm_bridge_0
  s0
m0   fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
fmc_xcvr_system_bank_4e_3_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_3_nativePHY_loopback_cont_0
  csr
fmc_xcvr_system_bank_4e_3_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4e_3_pll_locked_status pll_locked_output  
  pll_locked
fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_pll_locked_status

pll_status_interconnect v1.0
fmc_xcvr_system_bank_4e_3_xcvr_reset_control_s10_0 pll_locked   fmc_xcvr_system_bank_4e_3_pll_locked_status
  pll_locked_a
fmc_xcvr_system_pll_status pll_locked_p  
  pll_locked
pll_locked_output   fmc_xcvr_system_bank_4e_3_nativePHY_loopback_cont_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
fmc_xcvr_system_bank_4e_3_default_pma_settings_conf_0 avalon_master   fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0
  reconfig_avmm
fmc_xcvr_system_bank_4e_3_mm_bridge_0 m0  
  reconfig_avmm
fmc_xcvr_system_bank_4e_3_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
fmc_xcvr_system_bank_4e_3_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
fmc_xcvr_system_bank_4e_3_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
atx_pll_4c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_4c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   fmc_xcvr_system_bank_4e_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout2   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset_stat   fmc_xcvr_system_bank_4e_3_xcvr_reset_control_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_is_lockedtoref   fmc_xcvr_system_bank_4e_3_nativePHY_loopback_cont_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
fmc_xcvr_system_bank_4e_3_clk_50 clk   fmc_xcvr_system_bank_4e_3_xcvr_reset_control_s10_0
  clock
fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
fmc_xcvr_system_bank_4e_3_clk_100 clk_reset  
  reset
pll_locked   fmc_xcvr_system_bank_4e_3_pll_locked_status
  pll_locked_a
rx_analogreset   fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_st_converter_0

xcvr_st_converter v1.0
fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0 rx_clkout   fmc_xcvr_system_bank_4e_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_clkout_a   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_clk_50

clock_source vnull
fmc_xcvr_system_bank_4e_3_clk_50 clk   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_mm_bridge_0 m0   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_freq_counter_0
  csr
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_clk_50 clk   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
fmc_xcvr_system_bank_4e_3_mm_bridge_0 m0  
  s0
m0   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_freq_counter_0
  csr
m0   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_rx_fifo

fifo v16.930
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_tx_fifo

fifo v16.930
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
fmc_xcvr_system_bank_4e_3_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_rx_fifo fifo_input   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
fmc_xcvr_system_bank_4e_3_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   fmc_xcvr_system_bank_4e_3_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_tx_fifo fifo_input   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
fmc_xcvr_system_bank_4e_3_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   fmc_xcvr_system_bank_4e_3_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   fmc_xcvr_system_bank_4e_3_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)
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