q_sys

2017.11.08.15:29:43 Datasheet
Overview
  clk_100  q_sys
  clk_50 
  qsfp_xcvr_test_0_clk_100 
  qsfp_xcvr_test_0_clk_50 
  qsfp_xcvr_test_0_xcvr_test_system_0_clk_50 
  qsfp_xcvr_test_1_clk_100 
  qsfp_xcvr_test_1_clk_50 
  qsfp_xcvr_test_1_xcvr_test_system_0_clk_50 
  qsfp_xcvr_test_3_clk_100 
  qsfp_xcvr_test_3_clk_50 
  qsfp_xcvr_test_3_xcvr_test_system_0_clk_50 
  qsfp_xcvr_test_4_clk_100 
  qsfp_xcvr_test_4_clk_50 
  qsfp_xcvr_test_4_xcvr_test_system_0_clk_50 
  sdi_xcvr_test_0_clk_100 
  sdi_xcvr_test_0_clk_50 
  sdi_xcvr_test_0_xcvr_test_system_0_clk_50 
  sdi_xcvr_test_1_clk_100 
  sdi_xcvr_test_1_clk_50 
  sdi_xcvr_test_1_xcvr_test_system_0_clk_50 

All Components
   product_info_0 product_info 1.0
   qsfp_xcvr_atx_pll altera_xcvr_atx_pll_s10_htile 17.1
   qsfp_xcvr_atx_pll1 altera_xcvr_atx_pll_s10_htile 17.1
   sdi_xcvr_atx_pll altera_xcvr_atx_pll_s10_htile 17.1
   qsfp_xcvr_test_0 qsfp_xcvr_test 1.0
   qsfp_xcvr_test_0_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   qsfp_xcvr_test_0_mm_bridge_0 altera_avalon_mm_bridge 17.1
   qsfp_xcvr_test_0_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   qsfp_xcvr_test_0_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   qsfp_xcvr_test_0_xcvr_test_system_0 xcvr_test_system 1.0
   qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   qsfp_xcvr_test_0_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   qsfp_xcvr_test_0_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   qsfp_xcvr_test_1 qsfp_xcvr_test 1.0
   qsfp_xcvr_test_1_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   qsfp_xcvr_test_1_mm_bridge_0 altera_avalon_mm_bridge 17.1
   qsfp_xcvr_test_1_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   qsfp_xcvr_test_1_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   qsfp_xcvr_test_1_xcvr_test_system_0 xcvr_test_system 1.0
   qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   qsfp_xcvr_test_1_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   qsfp_xcvr_test_1_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   qsfp_xcvr_test_3 qsfp_xcvr_test 1.0
   qsfp_xcvr_test_3_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   qsfp_xcvr_test_3_mm_bridge_0 altera_avalon_mm_bridge 17.1
   qsfp_xcvr_test_3_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   qsfp_xcvr_test_3_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   qsfp_xcvr_test_3_xcvr_test_system_0 xcvr_test_system 1.0
   qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   qsfp_xcvr_test_3_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   qsfp_xcvr_test_3_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   qsfp_xcvr_test_4 qsfp_xcvr_test 1.0
   qsfp_xcvr_test_4_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   qsfp_xcvr_test_4_mm_bridge_0 altera_avalon_mm_bridge 17.1
   qsfp_xcvr_test_4_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   qsfp_xcvr_test_4_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   qsfp_xcvr_test_4_xcvr_test_system_0 xcvr_test_system 1.0
   qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   qsfp_xcvr_test_4_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   qsfp_xcvr_test_4_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   sdi_xcvr_test_0 sdi_xcvr_test 1.0
   sdi_xcvr_test_0_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   sdi_xcvr_test_0_mm_bridge_0 altera_avalon_mm_bridge 17.1
   sdi_xcvr_test_0_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   sdi_xcvr_test_0_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   sdi_xcvr_test_0_xcvr_test_system_0 xcvr_test_system 1.0
   sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   sdi_xcvr_test_0_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   sdi_xcvr_test_0_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   sdi_xcvr_test_1 sdi_xcvr_test 1.0
   sdi_xcvr_test_1_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   sdi_xcvr_test_1_mm_bridge_0 altera_avalon_mm_bridge 17.1
   sdi_xcvr_test_1_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   sdi_xcvr_test_1_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   sdi_xcvr_test_1_xcvr_test_system_0 xcvr_test_system 1.0
   sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   sdi_xcvr_test_1_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   sdi_xcvr_test_1_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
Memory Map
master_0 qsfp_xcvr_test_0_default_pma_settings_conf_0 qsfp_xcvr_test_1_default_pma_settings_conf_0 qsfp_xcvr_test_3_default_pma_settings_conf_0 qsfp_xcvr_test_4_default_pma_settings_conf_0 sdi_xcvr_test_0_default_pma_settings_conf_0 sdi_xcvr_test_1_default_pma_settings_conf_0
 master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master
  product_info_0
avalon_slave_0  0x00000000
  qsfp_xcvr_atx_pll
reconfig_avmm0  0x00100000
  qsfp_xcvr_atx_pll1
reconfig_avmm0  0x00300000
  sdi_xcvr_atx_pll
reconfig_avmm0  0x00200000
  qsfp_xcvr_test_0
mm_bridge_0_s0 
  qsfp_xcvr_test_0_default_pma_settings_conf_0
avalon_slave  0x00014000
  qsfp_xcvr_test_0_nativePHY_loopback_cont_0
csr  0x00015000
  qsfp_xcvr_test_0_xcvr_native_s10_0
reconfig_avmm  0x00010000 0x00000000
  qsfp_xcvr_test_0_xcvr_test_system_0
mm_bridge_0_s0 
  qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00013020
  qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00013000
  qsfp_xcvr_test_0_xcvr_test_system_0_freq_counter_0
csr  0x00013200
  qsfp_xcvr_test_1
mm_bridge_0_s0 
  qsfp_xcvr_test_1_default_pma_settings_conf_0
avalon_slave  0x00024000
  qsfp_xcvr_test_1_nativePHY_loopback_cont_0
csr  0x00025000
  qsfp_xcvr_test_1_xcvr_native_s10_0
reconfig_avmm  0x00020000 0x00000000
  qsfp_xcvr_test_1_xcvr_test_system_0
mm_bridge_0_s0 
  qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00023020
  qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00023000
  qsfp_xcvr_test_1_xcvr_test_system_0_freq_counter_0
csr  0x00023200
  qsfp_xcvr_test_3
mm_bridge_0_s0 
  qsfp_xcvr_test_3_default_pma_settings_conf_0
avalon_slave  0x00034000
  qsfp_xcvr_test_3_nativePHY_loopback_cont_0
csr  0x00035000
  qsfp_xcvr_test_3_xcvr_native_s10_0
reconfig_avmm  0x00030000 0x00000000
  qsfp_xcvr_test_3_xcvr_test_system_0
mm_bridge_0_s0 
  qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00033020
  qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00033000
  qsfp_xcvr_test_3_xcvr_test_system_0_freq_counter_0
csr  0x00033200
  qsfp_xcvr_test_4
mm_bridge_0_s0 
  qsfp_xcvr_test_4_default_pma_settings_conf_0
avalon_slave  0x00044000
  qsfp_xcvr_test_4_nativePHY_loopback_cont_0
csr  0x00045000
  qsfp_xcvr_test_4_xcvr_native_s10_0
reconfig_avmm  0x00040000 0x00000000
  qsfp_xcvr_test_4_xcvr_test_system_0
mm_bridge_0_s0 
  qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00043020
  qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00043000
  qsfp_xcvr_test_4_xcvr_test_system_0_freq_counter_0
csr  0x00043200
  sdi_xcvr_test_0
mm_bridge_0_s0 
  sdi_xcvr_test_0_default_pma_settings_conf_0
avalon_slave  0x00054000
  sdi_xcvr_test_0_nativePHY_loopback_cont_0
csr  0x00055000
  sdi_xcvr_test_0_xcvr_native_s10_0
reconfig_avmm  0x00050000 0x00000000
  sdi_xcvr_test_0_xcvr_test_system_0
mm_bridge_0_s0 
  sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00053020
  sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00053000
  sdi_xcvr_test_0_xcvr_test_system_0_freq_counter_0
csr  0x00053200
  sdi_xcvr_test_1
mm_bridge_0_s0 
  sdi_xcvr_test_1_default_pma_settings_conf_0
avalon_slave  0x00064000
  sdi_xcvr_test_1_nativePHY_loopback_cont_0
csr  0x00065000
  sdi_xcvr_test_1_xcvr_native_s10_0
reconfig_avmm  0x00060000 0x00000000
  sdi_xcvr_test_1_xcvr_test_system_0
mm_bridge_0_s0 
  sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00063020
  sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00063000
  sdi_xcvr_test_1_xcvr_test_system_0_freq_counter_0
csr  0x00063200

clk_100

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

clk_50

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

master_0

altera_jtag_avalon_master v17.1
clk_50 clk   master_0
  clk
clk_reset  
  clk_reset
master   product_info_0
  avalon_slave_0
master   qsfp_xcvr_test_0_mm_bridge_0
  s0
master   qsfp_xcvr_test_1_mm_bridge_0
  s0
master   qsfp_xcvr_test_3_mm_bridge_0
  s0
master   qsfp_xcvr_test_4_mm_bridge_0
  s0
master   sdi_xcvr_test_0_mm_bridge_0
  s0
master   sdi_xcvr_test_1_mm_bridge_0
  s0
master   sdi_xcvr_atx_pll
  reconfig_avmm0
master   qsfp_xcvr_atx_pll
  reconfig_avmm0
master   qsfp_xcvr_atx_pll1
  reconfig_avmm0


Parameters

generateLegacySim false
  

Software Assignments

(none)

product_info_0

product_info v1.0
master_0 master   product_info_0
  avalon_slave_0
clk_50 clk  
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

q_sys_pll_status_interconnect_qsfp

pll_status_interconnect v1.0
qsfp_xcvr_atx_pll pll_locked   q_sys_pll_status_interconnect_qsfp
  pll_locked
pll_locked_a   qsfp_xcvr_test_0_pll_locked
  pll_locked
pll_locked_b   qsfp_xcvr_test_1_pll_locked
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

q_sys_pll_status_interconnect_qsfp1

pll_status_interconnect v1.0
qsfp_xcvr_test_3_pll_locked pll_locked   q_sys_pll_status_interconnect_qsfp1
  pll_locked_a
qsfp_xcvr_test_4_pll_locked pll_locked  
  pll_locked_b
pll_locked   qsfp_xcvr_atx_pll1
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

q_sys_pll_status_interconnect_sdi

pll_status_interconnect v1.0
sdi_xcvr_atx_pll pll_locked   q_sys_pll_status_interconnect_sdi
  pll_locked
sdi_xcvr_test_0_pll_status_interconnect_0 pll_locked  
  pll_locked_a
pll_locked_b   sdi_xcvr_test_1_pll_status_interconnect_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_atx_pll

altera_xcvr_atx_pll_s10_htile v17.1
master_0 master   qsfp_xcvr_atx_pll
  reconfig_avmm0
clk_100 clk  
  reconfig_clk0
clk_reset  
  reconfig_reset0
qsfp_xcvr_atx_pll_refclk out_clk  
  pll_refclk0
pll_locked   q_sys_pll_status_interconnect_qsfp
  pll_locked
tx_serial_clk_gxt   qsfp_xcvr_test_0_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk_gxt   qsfp_xcvr_test_1_xcvr_native_s10_0
  tx_serial_clk0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_atx_pll1

altera_xcvr_atx_pll_s10_htile v17.1
master_0 master   qsfp_xcvr_atx_pll1
  reconfig_avmm0
clk_100 clk  
  reconfig_clk0
clk_reset  
  reconfig_reset0
qsfp_xcvr_atx_pll_refclk out_clk  
  pll_refclk0
q_sys_pll_status_interconnect_qsfp1 pll_locked  
  pll_locked
tx_serial_clk_gxt   qsfp_xcvr_test_3_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk_gxt   qsfp_xcvr_test_4_xcvr_native_s10_0
  tx_serial_clk0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_atx_pll_refclk

altera_clock_bridge v17.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_atx_pll

altera_xcvr_atx_pll_s10_htile v17.1
master_0 master   sdi_xcvr_atx_pll
  reconfig_avmm0
clk_100 clk  
  reconfig_clk0
clk_reset  
  reconfig_reset0
sdi_xcvr_atx_pll_refclk out_clk  
  pll_refclk0
pll_locked   q_sys_pll_status_interconnect_sdi
  pll_locked
tx_serial_clk   sdi_xcvr_test_0_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk   sdi_xcvr_test_1_xcvr_native_s10_0
  tx_serial_clk0


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_atx_pll_refclk

altera_clock_bridge v17.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0

qsfp_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_clk_100

clock_source vnull
clk_100 clk   qsfp_xcvr_test_0_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_0_xcvr_reset_control_s10_0
  clock
clk_reset  
  reset
clk   qsfp_xcvr_test_0_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_clk_50

clock_source vnull
clk_50 clk   qsfp_xcvr_test_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfp_xcvr_test_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_0_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   qsfp_xcvr_test_0_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_default_pma_settings_conf_0

default_pma_settings_conf v1.0
qsfp_xcvr_test_0_mm_bridge_0 m0   qsfp_xcvr_test_0_default_pma_settings_conf_0
  avalon_slave
qsfp_xcvr_test_0_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   qsfp_xcvr_test_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_mm_bridge_0

altera_avalon_mm_bridge v17.1
qsfp_xcvr_test_0_clk_50 clk   qsfp_xcvr_test_0_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   qsfp_xcvr_test_0_default_pma_settings_conf_0
  avalon_slave
m0   qsfp_xcvr_test_0_nativePHY_loopback_cont_0
  csr
m0   qsfp_xcvr_test_0_xcvr_test_system_0_mm_bridge_0
  s0
m0   qsfp_xcvr_test_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
qsfp_xcvr_test_0_mm_bridge_0 m0   qsfp_xcvr_test_0_nativePHY_loopback_cont_0
  csr
qsfp_xcvr_test_0_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   qsfp_xcvr_test_0_pll_locked
  pll_locked_output
rx_is_lockedtoref   qsfp_xcvr_test_0_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_pll_locked

pll_status_interconnect v1.0
qsfp_xcvr_test_0_nativePHY_loopback_cont_0 pll_locked   qsfp_xcvr_test_0_pll_locked
  pll_locked_output
q_sys_pll_status_interconnect_qsfp pll_locked_a  
  pll_locked
pll_locked_a   qsfp_xcvr_test_0_xcvr_reset_control_s10_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
qsfp_xcvr_test_0_default_pma_settings_conf_0 avalon_master   qsfp_xcvr_test_0_xcvr_native_s10_0
  reconfig_avmm
qsfp_xcvr_test_0_mm_bridge_0 m0  
  reconfig_avmm
qsfp_xcvr_test_0_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
qsfp_xcvr_test_0_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
qsfp_xcvr_test_0_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
qsfp_xcvr_test_0_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
qsfp_xcvr_atx_pll_refclk out_clk  
  rx_cdr_refclk0
qsfp_xcvr_atx_pll tx_serial_clk_gxt  
  tx_serial_clk0
rx_clkout   qsfp_xcvr_test_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_cal_busy   qsfp_xcvr_test_0_xcvr_reset_control_s10_0
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
qsfp_xcvr_test_0_clk_100 clk   qsfp_xcvr_test_0_xcvr_reset_control_s10_0
  clock
clk_reset  
  reset
qsfp_xcvr_test_0_pll_locked pll_locked_a  
  pll_locked
qsfp_xcvr_test_0_xcvr_native_s10_0 rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_analogreset   qsfp_xcvr_test_0_xcvr_native_s10_0
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_st_converter_0

xcvr_st_converter v1.0
qsfp_xcvr_test_0_xcvr_native_s10_0 rx_clkout   qsfp_xcvr_test_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   qsfp_xcvr_test_0_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_test_system_0_clk_50

clock_source vnull
qsfp_xcvr_test_0_clk_50 clk   qsfp_xcvr_test_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfp_xcvr_test_0_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
qsfp_xcvr_test_0_xcvr_test_system_0_mm_bridge_0 m0   qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
qsfp_xcvr_test_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
qsfp_xcvr_test_0_xcvr_test_system_0_mm_bridge_0 m0   qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
qsfp_xcvr_test_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
qsfp_xcvr_test_0_xcvr_test_system_0_mm_bridge_0 m0   qsfp_xcvr_test_0_xcvr_test_system_0_freq_counter_0
  csr
qsfp_xcvr_test_0_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
qsfp_xcvr_test_0_xcvr_test_system_0_clk_50 clk   qsfp_xcvr_test_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
qsfp_xcvr_test_0_mm_bridge_0 m0  
  s0
m0   qsfp_xcvr_test_0_xcvr_test_system_0_freq_counter_0
  csr
m0   qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_test_system_0_rx_fifo

fifo v16.930
qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   qsfp_xcvr_test_0_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_test_system_0_tx_fifo

fifo v16.930
qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   qsfp_xcvr_test_0_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
qsfp_xcvr_test_0_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   qsfp_xcvr_test_0_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
qsfp_xcvr_test_0_xcvr_test_system_0_rx_fifo fifo_input   qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
qsfp_xcvr_test_0_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   qsfp_xcvr_test_0_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   qsfp_xcvr_test_0_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
qsfp_xcvr_test_0_xcvr_test_system_0_tx_fifo fifo_input   qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
qsfp_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
qsfp_xcvr_test_0_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   qsfp_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   qsfp_xcvr_test_0_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   qsfp_xcvr_test_0_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1

qsfp_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_clk_100

clock_source vnull
clk_100 clk   qsfp_xcvr_test_1_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_1_xcvr_reset_control_s10_0
  clock
clk_reset  
  reset
clk   qsfp_xcvr_test_1_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_clk_50

clock_source vnull
clk_50 clk   qsfp_xcvr_test_1_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_1_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfp_xcvr_test_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_1_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   qsfp_xcvr_test_1_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_default_pma_settings_conf_0

default_pma_settings_conf v1.0
qsfp_xcvr_test_1_mm_bridge_0 m0   qsfp_xcvr_test_1_default_pma_settings_conf_0
  avalon_slave
qsfp_xcvr_test_1_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   qsfp_xcvr_test_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_mm_bridge_0

altera_avalon_mm_bridge v17.1
qsfp_xcvr_test_1_clk_50 clk   qsfp_xcvr_test_1_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   qsfp_xcvr_test_1_default_pma_settings_conf_0
  avalon_slave
m0   qsfp_xcvr_test_1_nativePHY_loopback_cont_0
  csr
m0   qsfp_xcvr_test_1_xcvr_test_system_0_mm_bridge_0
  s0
m0   qsfp_xcvr_test_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
qsfp_xcvr_test_1_mm_bridge_0 m0   qsfp_xcvr_test_1_nativePHY_loopback_cont_0
  csr
qsfp_xcvr_test_1_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   qsfp_xcvr_test_1_pll_locked
  pll_locked_output
rx_is_lockedtoref   qsfp_xcvr_test_1_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_pll_locked

pll_status_interconnect v1.0
qsfp_xcvr_test_1_nativePHY_loopback_cont_0 pll_locked   qsfp_xcvr_test_1_pll_locked
  pll_locked_output
q_sys_pll_status_interconnect_qsfp pll_locked_b  
  pll_locked
pll_locked_a   qsfp_xcvr_test_1_xcvr_reset_control_s10_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
qsfp_xcvr_test_1_default_pma_settings_conf_0 avalon_master   qsfp_xcvr_test_1_xcvr_native_s10_0
  reconfig_avmm
qsfp_xcvr_test_1_mm_bridge_0 m0  
  reconfig_avmm
qsfp_xcvr_test_1_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
qsfp_xcvr_test_1_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
qsfp_xcvr_test_1_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
qsfp_xcvr_test_1_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
qsfp_xcvr_atx_pll_refclk out_clk  
  rx_cdr_refclk0
qsfp_xcvr_atx_pll tx_serial_clk_gxt  
  tx_serial_clk0
rx_clkout   qsfp_xcvr_test_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_cal_busy   qsfp_xcvr_test_1_xcvr_reset_control_s10_0
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
qsfp_xcvr_test_1_clk_100 clk   qsfp_xcvr_test_1_xcvr_reset_control_s10_0
  clock
clk_reset  
  reset
qsfp_xcvr_test_1_pll_locked pll_locked_a  
  pll_locked
qsfp_xcvr_test_1_xcvr_native_s10_0 rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_analogreset   qsfp_xcvr_test_1_xcvr_native_s10_0
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_st_converter_0

xcvr_st_converter v1.0
qsfp_xcvr_test_1_xcvr_native_s10_0 rx_clkout   qsfp_xcvr_test_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   qsfp_xcvr_test_1_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_test_system_0_clk_50

clock_source vnull
qsfp_xcvr_test_1_clk_50 clk   qsfp_xcvr_test_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfp_xcvr_test_1_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
qsfp_xcvr_test_1_xcvr_test_system_0_mm_bridge_0 m0   qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
qsfp_xcvr_test_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
qsfp_xcvr_test_1_xcvr_test_system_0_mm_bridge_0 m0   qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
qsfp_xcvr_test_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
qsfp_xcvr_test_1_xcvr_test_system_0_mm_bridge_0 m0   qsfp_xcvr_test_1_xcvr_test_system_0_freq_counter_0
  csr
qsfp_xcvr_test_1_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
qsfp_xcvr_test_1_xcvr_test_system_0_clk_50 clk   qsfp_xcvr_test_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
qsfp_xcvr_test_1_mm_bridge_0 m0  
  s0
m0   qsfp_xcvr_test_1_xcvr_test_system_0_freq_counter_0
  csr
m0   qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_test_system_0_rx_fifo

fifo v16.930
qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   qsfp_xcvr_test_1_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_test_system_0_tx_fifo

fifo v16.930
qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   qsfp_xcvr_test_1_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
qsfp_xcvr_test_1_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   qsfp_xcvr_test_1_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
qsfp_xcvr_test_1_xcvr_test_system_0_rx_fifo fifo_input   qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
qsfp_xcvr_test_1_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   qsfp_xcvr_test_1_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   qsfp_xcvr_test_1_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
qsfp_xcvr_test_1_xcvr_test_system_0_tx_fifo fifo_input   qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
qsfp_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
qsfp_xcvr_test_1_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   qsfp_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   qsfp_xcvr_test_1_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   qsfp_xcvr_test_1_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3

qsfp_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_clk_100

clock_source vnull
clk_100 clk   qsfp_xcvr_test_3_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_3_xcvr_reset_control_s10_0
  clock
clk_reset  
  reset
clk   qsfp_xcvr_test_3_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_clk_50

clock_source vnull
clk_50 clk   qsfp_xcvr_test_3_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_3_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfp_xcvr_test_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_3_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   qsfp_xcvr_test_3_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_default_pma_settings_conf_0

default_pma_settings_conf v1.0
qsfp_xcvr_test_3_mm_bridge_0 m0   qsfp_xcvr_test_3_default_pma_settings_conf_0
  avalon_slave
qsfp_xcvr_test_3_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   qsfp_xcvr_test_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_mm_bridge_0

altera_avalon_mm_bridge v17.1
qsfp_xcvr_test_3_clk_50 clk   qsfp_xcvr_test_3_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   qsfp_xcvr_test_3_default_pma_settings_conf_0
  avalon_slave
m0   qsfp_xcvr_test_3_nativePHY_loopback_cont_0
  csr
m0   qsfp_xcvr_test_3_xcvr_test_system_0_mm_bridge_0
  s0
m0   qsfp_xcvr_test_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
qsfp_xcvr_test_3_mm_bridge_0 m0   qsfp_xcvr_test_3_nativePHY_loopback_cont_0
  csr
qsfp_xcvr_test_3_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   qsfp_xcvr_test_3_pll_locked
  pll_locked_output
rx_is_lockedtoref   qsfp_xcvr_test_3_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_pll_locked

pll_status_interconnect v1.0
qsfp_xcvr_test_3_nativePHY_loopback_cont_0 pll_locked   qsfp_xcvr_test_3_pll_locked
  pll_locked_output
pll_locked_a   qsfp_xcvr_test_3_xcvr_reset_control_s10_0
  pll_locked
pll_locked   q_sys_pll_status_interconnect_qsfp1
  pll_locked_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
qsfp_xcvr_test_3_default_pma_settings_conf_0 avalon_master   qsfp_xcvr_test_3_xcvr_native_s10_0
  reconfig_avmm
qsfp_xcvr_test_3_mm_bridge_0 m0  
  reconfig_avmm
qsfp_xcvr_test_3_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
qsfp_xcvr_test_3_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
qsfp_xcvr_test_3_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
qsfp_xcvr_test_3_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
qsfp_xcvr_atx_pll_refclk out_clk  
  rx_cdr_refclk0
qsfp_xcvr_atx_pll1 tx_serial_clk_gxt  
  tx_serial_clk0
rx_clkout   qsfp_xcvr_test_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_cal_busy   qsfp_xcvr_test_3_xcvr_reset_control_s10_0
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
qsfp_xcvr_test_3_clk_100 clk   qsfp_xcvr_test_3_xcvr_reset_control_s10_0
  clock
clk_reset  
  reset
qsfp_xcvr_test_3_pll_locked pll_locked_a  
  pll_locked
qsfp_xcvr_test_3_xcvr_native_s10_0 rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_analogreset   qsfp_xcvr_test_3_xcvr_native_s10_0
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_st_converter_0

xcvr_st_converter v1.0
qsfp_xcvr_test_3_xcvr_native_s10_0 rx_clkout   qsfp_xcvr_test_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   qsfp_xcvr_test_3_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_test_system_0_clk_50

clock_source vnull
qsfp_xcvr_test_3_clk_50 clk   qsfp_xcvr_test_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfp_xcvr_test_3_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
qsfp_xcvr_test_3_xcvr_test_system_0_mm_bridge_0 m0   qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
qsfp_xcvr_test_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
qsfp_xcvr_test_3_xcvr_test_system_0_mm_bridge_0 m0   qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
qsfp_xcvr_test_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
qsfp_xcvr_test_3_xcvr_test_system_0_mm_bridge_0 m0   qsfp_xcvr_test_3_xcvr_test_system_0_freq_counter_0
  csr
qsfp_xcvr_test_3_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
qsfp_xcvr_test_3_xcvr_test_system_0_clk_50 clk   qsfp_xcvr_test_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
qsfp_xcvr_test_3_mm_bridge_0 m0  
  s0
m0   qsfp_xcvr_test_3_xcvr_test_system_0_freq_counter_0
  csr
m0   qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_test_system_0_rx_fifo

fifo v16.930
qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   qsfp_xcvr_test_3_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_test_system_0_tx_fifo

fifo v16.930
qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   qsfp_xcvr_test_3_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
qsfp_xcvr_test_3_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   qsfp_xcvr_test_3_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
qsfp_xcvr_test_3_xcvr_test_system_0_rx_fifo fifo_input   qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
qsfp_xcvr_test_3_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   qsfp_xcvr_test_3_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   qsfp_xcvr_test_3_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
qsfp_xcvr_test_3_xcvr_test_system_0_tx_fifo fifo_input   qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
qsfp_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
qsfp_xcvr_test_3_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   qsfp_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   qsfp_xcvr_test_3_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   qsfp_xcvr_test_3_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4

qsfp_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_clk_100

clock_source vnull
clk_100 clk   qsfp_xcvr_test_4_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_4_xcvr_reset_control_s10_0
  clock
clk_reset  
  reset
clk   qsfp_xcvr_test_4_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_clk_50

clock_source vnull
clk_50 clk   qsfp_xcvr_test_4_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_4_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfp_xcvr_test_4_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_4_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   qsfp_xcvr_test_4_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_default_pma_settings_conf_0

default_pma_settings_conf v1.0
qsfp_xcvr_test_4_mm_bridge_0 m0   qsfp_xcvr_test_4_default_pma_settings_conf_0
  avalon_slave
qsfp_xcvr_test_4_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   qsfp_xcvr_test_4_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_mm_bridge_0

altera_avalon_mm_bridge v17.1
qsfp_xcvr_test_4_clk_50 clk   qsfp_xcvr_test_4_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   qsfp_xcvr_test_4_default_pma_settings_conf_0
  avalon_slave
m0   qsfp_xcvr_test_4_nativePHY_loopback_cont_0
  csr
m0   qsfp_xcvr_test_4_xcvr_test_system_0_mm_bridge_0
  s0
m0   qsfp_xcvr_test_4_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
qsfp_xcvr_test_4_mm_bridge_0 m0   qsfp_xcvr_test_4_nativePHY_loopback_cont_0
  csr
qsfp_xcvr_test_4_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   qsfp_xcvr_test_4_pll_locked
  pll_locked_output
rx_is_lockedtoref   qsfp_xcvr_test_4_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_pll_locked

pll_status_interconnect v1.0
qsfp_xcvr_test_4_nativePHY_loopback_cont_0 pll_locked   qsfp_xcvr_test_4_pll_locked
  pll_locked_output
pll_locked_a   qsfp_xcvr_test_4_xcvr_reset_control_s10_0
  pll_locked
pll_locked   q_sys_pll_status_interconnect_qsfp1
  pll_locked_b


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
qsfp_xcvr_test_4_default_pma_settings_conf_0 avalon_master   qsfp_xcvr_test_4_xcvr_native_s10_0
  reconfig_avmm
qsfp_xcvr_test_4_mm_bridge_0 m0  
  reconfig_avmm
qsfp_xcvr_test_4_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
qsfp_xcvr_test_4_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
qsfp_xcvr_test_4_xcvr_reset_control_s10_0 rx_analogreset  
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
qsfp_xcvr_test_4_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
qsfp_xcvr_atx_pll_refclk out_clk  
  rx_cdr_refclk0
qsfp_xcvr_atx_pll1 tx_serial_clk_gxt  
  tx_serial_clk0
rx_clkout   qsfp_xcvr_test_4_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_cal_busy   qsfp_xcvr_test_4_xcvr_reset_control_s10_0
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
qsfp_xcvr_test_4_clk_100 clk   qsfp_xcvr_test_4_xcvr_reset_control_s10_0
  clock
clk_reset  
  reset
qsfp_xcvr_test_4_pll_locked pll_locked_a  
  pll_locked
qsfp_xcvr_test_4_xcvr_native_s10_0 rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_analogreset   qsfp_xcvr_test_4_xcvr_native_s10_0
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_st_converter_0

xcvr_st_converter v1.0
qsfp_xcvr_test_4_xcvr_native_s10_0 rx_clkout   qsfp_xcvr_test_4_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   qsfp_xcvr_test_4_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_test_system_0_clk_50

clock_source vnull
qsfp_xcvr_test_4_clk_50 clk   qsfp_xcvr_test_4_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfp_xcvr_test_4_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfp_xcvr_test_4_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
qsfp_xcvr_test_4_xcvr_test_system_0_mm_bridge_0 m0   qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
qsfp_xcvr_test_4_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
qsfp_xcvr_test_4_xcvr_test_system_0_mm_bridge_0 m0   qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
qsfp_xcvr_test_4_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
qsfp_xcvr_test_4_xcvr_test_system_0_mm_bridge_0 m0   qsfp_xcvr_test_4_xcvr_test_system_0_freq_counter_0
  csr
qsfp_xcvr_test_4_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
qsfp_xcvr_test_4_xcvr_test_system_0_clk_50 clk   qsfp_xcvr_test_4_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
qsfp_xcvr_test_4_mm_bridge_0 m0  
  s0
m0   qsfp_xcvr_test_4_xcvr_test_system_0_freq_counter_0
  csr
m0   qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_test_system_0_rx_fifo

fifo v16.930
qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   qsfp_xcvr_test_4_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_test_system_0_tx_fifo

fifo v16.930
qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   qsfp_xcvr_test_4_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
qsfp_xcvr_test_4_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   qsfp_xcvr_test_4_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
qsfp_xcvr_test_4_xcvr_test_system_0_rx_fifo fifo_input   qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
qsfp_xcvr_test_4_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   qsfp_xcvr_test_4_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   qsfp_xcvr_test_4_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
qsfp_xcvr_test_4_xcvr_test_system_0_tx_fifo fifo_input   qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
qsfp_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
qsfp_xcvr_test_4_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   qsfp_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   qsfp_xcvr_test_4_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   qsfp_xcvr_test_4_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0

sdi_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_clk_100

clock_source vnull
clk_100 clk   sdi_xcvr_test_0_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   sdi_xcvr_test_0_xcvr_reset_control_s10_0
  clock
clk_reset  
  reset
clk   sdi_xcvr_test_0_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_clk_50

clock_source vnull
clk_50 clk   sdi_xcvr_test_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   sdi_xcvr_test_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   sdi_xcvr_test_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   sdi_xcvr_test_0_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   sdi_xcvr_test_0_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_default_pma_settings_conf_0

default_pma_settings_conf v1.0
sdi_xcvr_test_0_mm_bridge_0 m0   sdi_xcvr_test_0_default_pma_settings_conf_0
  avalon_slave
sdi_xcvr_test_0_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   sdi_xcvr_test_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_mm_bridge_0

altera_avalon_mm_bridge v17.1
sdi_xcvr_test_0_clk_50 clk   sdi_xcvr_test_0_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   sdi_xcvr_test_0_default_pma_settings_conf_0
  avalon_slave
m0   sdi_xcvr_test_0_nativePHY_loopback_cont_0
  csr
m0   sdi_xcvr_test_0_xcvr_test_system_0_mm_bridge_0
  s0
m0   sdi_xcvr_test_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
sdi_xcvr_test_0_mm_bridge_0 m0   sdi_xcvr_test_0_nativePHY_loopback_cont_0
  csr
sdi_xcvr_test_0_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   sdi_xcvr_test_0_pll_status_interconnect_0
  pll_locked_output
rx_is_lockedtoref   sdi_xcvr_test_0_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_pll_status_interconnect_0

pll_status_interconnect v1.0
sdi_xcvr_test_0_nativePHY_loopback_cont_0 pll_locked   sdi_xcvr_test_0_pll_status_interconnect_0
  pll_locked_output
pll_locked_a   sdi_xcvr_test_0_xcvr_reset_control_s10_0
  pll_locked
pll_locked   q_sys_pll_status_interconnect_sdi
  pll_locked_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
sdi_xcvr_test_0_default_pma_settings_conf_0 avalon_master   sdi_xcvr_test_0_xcvr_native_s10_0
  reconfig_avmm
sdi_xcvr_test_0_mm_bridge_0 m0  
  reconfig_avmm
sdi_xcvr_test_0_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
sdi_xcvr_test_0_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
sdi_xcvr_test_0_xcvr_reset_control_s10_0 rx_cal_busy  
  rx_cal_busy
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
sdi_xcvr_test_0_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
sdi_xcvr_atx_pll_refclk out_clk  
  rx_cdr_refclk0
sdi_xcvr_atx_pll tx_serial_clk  
  tx_serial_clk0
rx_clkout   sdi_xcvr_test_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   sdi_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   sdi_xcvr_test_0_xcvr_reset_control_s10_0
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset  
  rx_digitalreset
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
sdi_xcvr_test_0_clk_100 clk   sdi_xcvr_test_0_xcvr_reset_control_s10_0
  clock
clk_reset  
  reset
sdi_xcvr_test_0_pll_status_interconnect_0 pll_locked_a  
  pll_locked
sdi_xcvr_test_0_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset  
  rx_digitalreset
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_cal_busy   sdi_xcvr_test_0_xcvr_native_s10_0
  rx_cal_busy
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_st_converter_0

xcvr_st_converter v1.0
sdi_xcvr_test_0_xcvr_native_s10_0 rx_clkout   sdi_xcvr_test_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
data_pattern_generator_pattern_out_clk  
  tx_clkout_a
rx_clkout_a_output   sdi_xcvr_test_0_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_test_system_0_clk_50

clock_source vnull
sdi_xcvr_test_0_clk_50 clk   sdi_xcvr_test_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   sdi_xcvr_test_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   sdi_xcvr_test_0_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
sdi_xcvr_test_0_xcvr_test_system_0_mm_bridge_0 m0   sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
sdi_xcvr_test_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
sdi_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
sdi_xcvr_test_0_xcvr_test_system_0_mm_bridge_0 m0   sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
sdi_xcvr_test_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   sdi_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
sdi_xcvr_test_0_xcvr_test_system_0_mm_bridge_0 m0   sdi_xcvr_test_0_xcvr_test_system_0_freq_counter_0
  csr
sdi_xcvr_test_0_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
sdi_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
sdi_xcvr_test_0_xcvr_test_system_0_clk_50 clk   sdi_xcvr_test_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
sdi_xcvr_test_0_mm_bridge_0 m0  
  s0
m0   sdi_xcvr_test_0_xcvr_test_system_0_freq_counter_0
  csr
m0   sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_test_system_0_rx_fifo

fifo v16.930
sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   sdi_xcvr_test_0_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_test_system_0_tx_fifo

fifo v16.930
sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   sdi_xcvr_test_0_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   sdi_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
sdi_xcvr_test_0_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   sdi_xcvr_test_0_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
sdi_xcvr_test_0_xcvr_test_system_0_rx_fifo fifo_input   sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
sdi_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
sdi_xcvr_test_0_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   sdi_xcvr_test_0_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   sdi_xcvr_test_0_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
sdi_xcvr_test_0_xcvr_test_system_0_tx_fifo fifo_input   sdi_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
sdi_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
data_pattern_generator_pattern_out_fifo_write   sdi_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   sdi_xcvr_test_0_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   sdi_xcvr_test_0_xcvr_st_converter_0
  tx_data_a
data_pattern_generator_pattern_out_clk  
  tx_clkout_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1

sdi_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_clk_100

clock_source vnull
clk_100 clk   sdi_xcvr_test_1_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   sdi_xcvr_test_1_xcvr_reset_control_s10_0
  clock
clk_reset  
  reset
clk   sdi_xcvr_test_1_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_clk_50

clock_source vnull
clk_50 clk   sdi_xcvr_test_1_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   sdi_xcvr_test_1_mm_bridge_0
  clk
clk_reset  
  reset
clk   sdi_xcvr_test_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   sdi_xcvr_test_1_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   sdi_xcvr_test_1_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_default_pma_settings_conf_0

default_pma_settings_conf v1.0
sdi_xcvr_test_1_mm_bridge_0 m0   sdi_xcvr_test_1_default_pma_settings_conf_0
  avalon_slave
sdi_xcvr_test_1_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   sdi_xcvr_test_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_mm_bridge_0

altera_avalon_mm_bridge v17.1
sdi_xcvr_test_1_clk_50 clk   sdi_xcvr_test_1_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   sdi_xcvr_test_1_default_pma_settings_conf_0
  avalon_slave
m0   sdi_xcvr_test_1_nativePHY_loopback_cont_0
  csr
m0   sdi_xcvr_test_1_xcvr_test_system_0_mm_bridge_0
  s0
m0   sdi_xcvr_test_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
sdi_xcvr_test_1_mm_bridge_0 m0   sdi_xcvr_test_1_nativePHY_loopback_cont_0
  csr
sdi_xcvr_test_1_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   sdi_xcvr_test_1_pll_status_interconnect_0
  pll_locked_output
rx_is_lockedtoref   sdi_xcvr_test_1_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_pll_status_interconnect_0

pll_status_interconnect v1.0
sdi_xcvr_test_1_nativePHY_loopback_cont_0 pll_locked   sdi_xcvr_test_1_pll_status_interconnect_0
  pll_locked_output
q_sys_pll_status_interconnect_sdi pll_locked_b  
  pll_locked
pll_locked_a   sdi_xcvr_test_1_xcvr_reset_control_s10_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
sdi_xcvr_test_1_default_pma_settings_conf_0 avalon_master   sdi_xcvr_test_1_xcvr_native_s10_0
  reconfig_avmm
sdi_xcvr_test_1_mm_bridge_0 m0  
  reconfig_avmm
sdi_xcvr_test_1_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
sdi_xcvr_test_1_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
sdi_xcvr_test_1_xcvr_reset_control_s10_0 rx_cal_busy  
  rx_cal_busy
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
sdi_xcvr_test_1_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
sdi_xcvr_atx_pll_refclk out_clk  
  rx_cdr_refclk0
sdi_xcvr_atx_pll tx_serial_clk  
  tx_serial_clk0
rx_clkout   sdi_xcvr_test_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   sdi_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   sdi_xcvr_test_1_xcvr_reset_control_s10_0
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset  
  rx_digitalreset
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
sdi_xcvr_test_1_clk_100 clk   sdi_xcvr_test_1_xcvr_reset_control_s10_0
  clock
clk_reset  
  reset
sdi_xcvr_test_1_pll_status_interconnect_0 pll_locked_a  
  pll_locked
sdi_xcvr_test_1_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset  
  rx_digitalreset
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_cal_busy   sdi_xcvr_test_1_xcvr_native_s10_0
  rx_cal_busy
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_st_converter_0

xcvr_st_converter v1.0
sdi_xcvr_test_1_xcvr_native_s10_0 rx_clkout   sdi_xcvr_test_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
data_pattern_generator_pattern_out_clk  
  tx_clkout_a
rx_clkout_a_output   sdi_xcvr_test_1_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_test_system_0_clk_50

clock_source vnull
sdi_xcvr_test_1_clk_50 clk   sdi_xcvr_test_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   sdi_xcvr_test_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   sdi_xcvr_test_1_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
sdi_xcvr_test_1_xcvr_test_system_0_mm_bridge_0 m0   sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
sdi_xcvr_test_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
sdi_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
sdi_xcvr_test_1_xcvr_test_system_0_mm_bridge_0 m0   sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
sdi_xcvr_test_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   sdi_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
sdi_xcvr_test_1_xcvr_test_system_0_mm_bridge_0 m0   sdi_xcvr_test_1_xcvr_test_system_0_freq_counter_0
  csr
sdi_xcvr_test_1_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
sdi_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
sdi_xcvr_test_1_xcvr_test_system_0_clk_50 clk   sdi_xcvr_test_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
sdi_xcvr_test_1_mm_bridge_0 m0  
  s0
m0   sdi_xcvr_test_1_xcvr_test_system_0_freq_counter_0
  csr
m0   sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_test_system_0_rx_fifo

fifo v16.930
sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   sdi_xcvr_test_1_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_test_system_0_tx_fifo

fifo v16.930
sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   sdi_xcvr_test_1_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   sdi_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
sdi_xcvr_test_1_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   sdi_xcvr_test_1_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
sdi_xcvr_test_1_xcvr_test_system_0_rx_fifo fifo_input   sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
sdi_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
sdi_xcvr_test_1_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   sdi_xcvr_test_1_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   sdi_xcvr_test_1_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
sdi_xcvr_test_1_xcvr_test_system_0_tx_fifo fifo_input   sdi_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
sdi_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
data_pattern_generator_pattern_out_fifo_write   sdi_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   sdi_xcvr_test_1_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   sdi_xcvr_test_1_xcvr_st_converter_0
  tx_data_a
data_pattern_generator_pattern_out_clk  
  tx_clkout_a


Parameters

generateLegacySim false
  

Software Assignments

(none)
generation took 0.07 seconds rendering took 0.13 seconds