ed_sim_emif_s10_0

2017.11.07.10:42:25 Datasheet
Overview

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   emif_s10_0 altera_emif_s10 17.1
Memory Map
  emif_s10_0
ctrl_amm_0 

emif_s10_0

altera_emif_s10 v17.1


Parameters

PROTOCOL_ENUM PROTOCOL_DDR3
PHY_FPGA_SPEEDGRADE_GUI E2V (ES) - change device under 'View'->'Device Family'
PHY_RZQ 240
PLL_ADD_EXTRA_CLKS false
PHY_DDR3_CONFIG_ENUM CONFIG_PHY_AND_HARD_CTRL
PHY_DDR3_USER_PING_PONG_EN false
PHY_DDR3_MEM_CLK_FREQ_MHZ 1066.667
PHY_DDR3_DEFAULT_REF_CLK_FREQ false
PHY_DDR3_USER_REF_CLK_FREQ_MHZ 133.333
PHY_DDR3_REF_CLK_JITTER_PS 10.0
PHY_DDR3_RATE_ENUM RATE_QUARTER
PHY_DDR3_CORE_CLKS_SHARING_ENUM CORE_CLKS_SHARING_DISABLED
PHY_DDR3_IO_VOLTAGE 1.5
PHY_DDR3_DEFAULT_IO false
PHY_DDR3_USER_AC_IO_STD_ENUM IO_STD_SSTL_15_C1
PHY_DDR3_USER_AC_MODE_ENUM CURRENT_ST_8
PHY_DDR3_USER_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_DDR3_USER_CK_IO_STD_ENUM IO_STD_SSTL_15_C1
PHY_DDR3_USER_CK_MODE_ENUM CURRENT_ST_8
PHY_DDR3_USER_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_DDR3_USER_DATA_IO_STD_ENUM IO_STD_SSTL_15
PHY_DDR3_USER_DATA_OUT_MODE_ENUM OUT_OCT_34_CAL
PHY_DDR3_USER_DATA_IN_MODE_ENUM IN_OCT_120_CAL
PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM IO_STD_LVDS
PHY_DDR3_USER_RZQ_IO_STD_ENUM IO_STD_CMOS_15
MEM_DDR3_FORMAT_ENUM MEM_FORMAT_DISCRETE
MEM_DDR3_DQ_WIDTH 72
MEM_DDR3_DQ_PER_DQS 8
MEM_DDR3_DISCRETE_CS_WIDTH 1
MEM_DDR3_CK_WIDTH 1
MEM_DDR3_ROW_ADDR_WIDTH 15
MEM_DDR3_COL_ADDR_WIDTH 10
MEM_DDR3_BANK_ADDR_WIDTH 3
MEM_DDR3_DM_EN true
MEM_DDR3_HIDE_ADV_MR_SETTINGS true
MEM_DDR3_DQS_WIDTH 9
MEM_DDR3_DRV_STR_ENUM DDR3_DRV_STR_RZQ_6
MEM_DDR3_RTT_NOM_ENUM DDR3_RTT_NOM_RZQ_2
MEM_DDR3_RTT_WR_ENUM DDR3_RTT_WR_RZQ_4
MEM_DDR3_WTCL 10
MEM_DDR3_ATCL_ENUM DDR3_ATCL_DISABLED
MEM_DDR3_TCL 14
MEM_DDR3_USE_DEFAULT_ODT true
MEM_DDR3_R_ODTN_1X1 Rank 0
MEM_DDR3_R_ODT0_1X1 off
MEM_DDR3_W_ODTN_1X1 Rank 0
MEM_DDR3_W_ODT0_1X1 on
MEM_DDR3_R_ODTN_2X2 Rank 0,Rank 1
MEM_DDR3_R_ODT0_2X2 off,off
MEM_DDR3_R_ODT1_2X2 off,off
MEM_DDR3_W_ODTN_2X2 Rank 0,Rank 1
MEM_DDR3_W_ODT0_2X2 on,off
MEM_DDR3_W_ODT1_2X2 off,on
MEM_DDR3_R_ODTN_4X2 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_R_ODT0_4X2 off,off,on,on
MEM_DDR3_R_ODT1_4X2 on,on,off,off
MEM_DDR3_W_ODTN_4X2 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_W_ODT0_4X2 off,off,on,on
MEM_DDR3_W_ODT1_4X2 on,on,off,off
MEM_DDR3_R_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_R_ODT0_4X4 off,off,off,off
MEM_DDR3_R_ODT1_4X4 off,off,on,on
MEM_DDR3_R_ODT2_4X4 off,off,off,off
MEM_DDR3_R_ODT3_4X4 on,on,off,off
MEM_DDR3_W_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_W_ODT0_4X4 on,on,off,off
MEM_DDR3_W_ODT1_4X4 off,off,on,on
MEM_DDR3_W_ODT2_4X4 off,off,on,on
MEM_DDR3_W_ODT3_4X4 on,on,off,off
MEM_DDR3_R_DERIVED_ODTN Rank 0,-,-,-
MEM_DDR3_R_DERIVED_ODT0 (Drive) RZQ/6,-,-,-
MEM_DDR3_R_DERIVED_ODT1 -,-,-,-
MEM_DDR3_R_DERIVED_ODT2 -,-,-,-
MEM_DDR3_R_DERIVED_ODT3 -,-,-,-
MEM_DDR3_W_DERIVED_ODTN Rank 0,-,-,-
MEM_DDR3_W_DERIVED_ODT0 (Dynamic) RZQ/4,-,-,-
MEM_DDR3_W_DERIVED_ODT1 -,-,-,-
MEM_DDR3_W_DERIVED_ODT2 -,-,-,-
MEM_DDR3_W_DERIVED_ODT3 -,-,-,-
MEM_DDR3_SPEEDBIN_ENUM DDR3_SPEEDBIN_2133
MEM_DDR3_TIS_PS 60
MEM_DDR3_TIS_AC_MV 135
MEM_DDR3_TIH_PS 95
MEM_DDR3_TIH_DC_MV 100
MEM_DDR3_TDS_PS 53
MEM_DDR3_TDS_AC_MV 135
MEM_DDR3_TDH_PS 55
MEM_DDR3_TDH_DC_MV 100
MEM_DDR3_TDQSQ_PS 75
MEM_DDR3_TQH_CYC 0.38
MEM_DDR3_TDQSCK_PS 180
MEM_DDR3_TDQSS_CYC 0.27
MEM_DDR3_TQSH_CYC 0.4
MEM_DDR3_TDSH_CYC 0.18
MEM_DDR3_TWLS_PS 125.0
MEM_DDR3_TWLH_PS 125.0
MEM_DDR3_TDSS_CYC 0.18
MEM_DDR3_TINIT_US 500
MEM_DDR3_TMRD_CK_CYC 4
MEM_DDR3_TRAS_NS 33.0
MEM_DDR3_TRCD_NS 13.09
MEM_DDR3_TRP_NS 13.09
MEM_DDR3_TREFI_US 7.8
MEM_DDR3_TRFC_NS 260.0
MEM_DDR3_TWR_NS 15.0
MEM_DDR3_TWTR_CYC 8
MEM_DDR3_TFAW_NS 35.0
MEM_DDR3_TRRD_CYC 7
MEM_DDR3_TRTP_CYC 8
BOARD_DDR3_USE_DEFAULT_ISI_VALUES true
BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED false
BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS 0.02
BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED true
BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_DDR3_DQS_TO_CK_SKEW_NS 0.02
BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS 0.05
BOARD_DDR3_SKEW_BETWEEN_DQS_NS 0.02
BOARD_DDR3_AC_TO_CK_SKEW_NS 0.0
BOARD_DDR3_MAX_CK_DELAY_NS 0.6
BOARD_DDR3_MAX_DQS_DELAY_NS 0.6
BOARD_DDR3_AC_ISI_NS 0.15
BOARD_DDR3_RCLK_ISI_NS 0.15
BOARD_DDR3_WCLK_ISI_NS 0.045
BOARD_DDR3_RDATA_ISI_NS 0.09
BOARD_DDR3_WDATA_ISI_NS 0.11
CTRL_DDR3_AUTO_POWER_DOWN_EN false
CTRL_DDR3_AUTO_POWER_DOWN_CYCS 32
CTRL_DDR3_USER_REFRESH_EN false
CTRL_DDR3_USER_PRIORITY_EN false
CTRL_DDR3_AUTO_PRECHARGE_EN false
CTRL_DDR3_ADDR_ORDER_ENUM DDR3_CTRL_ADDR_ORDER_CS_R_B_C
CTRL_DDR3_ECC_EN true
CTRL_DDR3_ECC_AUTO_CORRECTION_EN false
CTRL_DDR3_REORDER_EN true
CTRL_DDR3_STARVE_LIMIT 10
CTRL_DDR3_MMR_EN false
CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS 0
CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS 0
CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS 0
DIAG_SOFT_NIOS_MODE SOFT_NIOS_MODE_DISABLED
DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE false
DIAG_DDR3_SIM_CAL_MODE_ENUM SIM_CAL_MODE_SKIP
DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER false
DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES 1
DIAG_DDR3_EX_DESIGN_ISSP_EN false
DIAG_DDR3_INTERFACE_ID 0
DIAG_DDR3_EFFICIENCY_MONITOR EFFMON_MODE_DISABLED
DIAG_DDR3_USE_TG_AVL_2 false
DIAG_DDR3_ABSTRACT_PHY false
DIAG_DDR3_BYPASS_DEFAULT_PATTERN false
DIAG_DDR3_BYPASS_USER_STAGE true
DIAG_DDR3_BYPASS_REPEAT_STAGE true
DIAG_DDR3_BYPASS_STRESS_STAGE true
EX_DESIGN_GUI_DDR3_SEL_DESIGN AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_DDR3_GEN_SIM true
EX_DESIGN_GUI_DDR3_GEN_SYNTH true
EX_DESIGN_GUI_DDR3_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT TARGET_DEV_KIT_NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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