sdi_xcvr_test

2017.11.08.15:26:45 Datasheet
Overview
  clk_100  sdi_xcvr_test
  clk_50 
  xcvr_test_system_0_clk_50 

All Components
   default_pma_settings_conf_0 default_pma_settings_conf 1.0
   mm_bridge_0 altera_avalon_mm_bridge 17.1
   nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   xcvr_test_system_0 xcvr_test_system 1.0
   xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
Memory Map
default_pma_settings_conf_0
 avalon_master
  default_pma_settings_conf_0
avalon_slave 
  nativePHY_loopback_cont_0
csr 
  xcvr_native_s10_0
reconfig_avmm  0x00000000
  xcvr_test_system_0
mm_bridge_0_s0 
  xcvr_test_system_0_data_pattern_checker_0
csr_slave 
  xcvr_test_system_0_data_pattern_generator_0
csr_slave 
  xcvr_test_system_0_freq_counter_0
csr 

clk_100

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

clk_50

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

default_pma_settings_conf_0

default_pma_settings_conf v1.0
mm_bridge_0 m0   default_pma_settings_conf_0
  avalon_slave
clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_0

altera_avalon_mm_bridge v17.1
clk_50 clk   mm_bridge_0
  clk
clk_reset  
  reset
m0   default_pma_settings_conf_0
  avalon_slave
m0   nativePHY_loopback_cont_0
  csr
m0   xcvr_test_system_0_mm_bridge_0
  s0
m0   xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
mm_bridge_0 m0   nativePHY_loopback_cont_0
  csr
clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pll_status_interconnect_0
  pll_locked_output
rx_is_lockedtoref   xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pll_status_interconnect_0

pll_status_interconnect v1.0
nativePHY_loopback_cont_0 pll_locked   pll_status_interconnect_0
  pll_locked_output
pll_locked_a   xcvr_reset_control_s10_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
default_pma_settings_conf_0 avalon_master   xcvr_native_s10_0
  reconfig_avmm
mm_bridge_0 m0  
  reconfig_avmm
clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
xcvr_reset_control_s10_0 rx_cal_busy  
  rx_cal_busy
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat
nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
rx_clkout   xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   xcvr_reset_control_s10_0
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset  
  rx_digitalreset
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
clk_100 clk   xcvr_reset_control_s10_0
  clock
clk_reset  
  reset
pll_status_interconnect_0 pll_locked_a  
  pll_locked
xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset  
  rx_digitalreset
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset  
  tx_digitalreset
rx_cal_busy   xcvr_native_s10_0
  rx_cal_busy
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_st_converter_0

xcvr_st_converter v1.0
xcvr_native_s10_0 rx_clkout   xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
data_pattern_generator_pattern_out_clk  
  tx_clkout_a
rx_clkout_a_output   xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_test_system_0_clk_50

clock_source vnull
clk_50 clk   xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
xcvr_test_system_0_mm_bridge_0 m0   xcvr_test_system_0_data_pattern_checker_0
  csr_slave
xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
xcvr_test_system_0_mm_bridge_0 m0   xcvr_test_system_0_data_pattern_generator_0
  csr_slave
xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_test_system_0_freq_counter_0

freq_counter v1.0
xcvr_test_system_0_mm_bridge_0 m0   xcvr_test_system_0_freq_counter_0
  csr
xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
xcvr_test_system_0_clk_50 clk   xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
mm_bridge_0 m0  
  s0
m0   xcvr_test_system_0_freq_counter_0
  csr
m0   xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_test_system_0_rx_fifo

fifo v16.930
xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_test_system_0_tx_fifo

fifo v16.930
xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
xcvr_test_system_0_rx_fifo fifo_input   xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
xcvr_test_system_0_tx_fifo fifo_input   xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
data_pattern_generator_pattern_out_fifo_write   xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   xcvr_st_converter_0
  tx_data_a
data_pattern_generator_pattern_out_clk  
  tx_clkout_a


Parameters

generateLegacySim false
  

Software Assignments

(none)
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