ed_synth_clk_0
2017.11.16.19:34:39
Datasheet
Overview
clk_0
ed_synth_clk_0
Memory Map
clk_0
clock_source v17.1
Parameters
clockFrequency
50000000
clockFrequencyKnown
true
resetSynchronousEdges
NONE
deviceFamily
UNKNOWN
generateLegacySim
false
Software Assignments
(none)
generation took 0.00 seconds
rendering took 0.00 seconds