pcie_xcvr_system

2017.11.13.11:25:25 Datasheet
Overview
  clk_100  pcie_xcvr_system
  clk_50 
  pcie_xcvr_system_bank_1c_0_clk_100 
  pcie_xcvr_system_bank_1c_0_clk_50 
  pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1c_1_clk_100 
  pcie_xcvr_system_bank_1c_1_clk_50 
  pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1c_2_clk_100 
  pcie_xcvr_system_bank_1c_2_clk_50 
  pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1c_3_clk_100 
  pcie_xcvr_system_bank_1c_3_clk_50 
  pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1c_4_clk_100 
  pcie_xcvr_system_bank_1c_4_clk_50 
  pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1c_5_clk_100 
  pcie_xcvr_system_bank_1c_5_clk_50 
  pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1d_0_clk_100 
  pcie_xcvr_system_bank_1d_0_clk_50 
  pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1d_1_clk_100 
  pcie_xcvr_system_bank_1d_1_clk_50 
  pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1d_2_clk_100 
  pcie_xcvr_system_bank_1d_2_clk_50 
  pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1d_3_clk_100 
  pcie_xcvr_system_bank_1d_3_clk_50 
  pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1d_4_clk_100 
  pcie_xcvr_system_bank_1d_4_clk_50 
  pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1d_5_clk_100 
  pcie_xcvr_system_bank_1d_5_clk_50 
  pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1e_0_clk_100 
  pcie_xcvr_system_bank_1e_0_clk_50 
  pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1e_1_clk_100 
  pcie_xcvr_system_bank_1e_1_clk_50 
  pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1e_2_clk_100 
  pcie_xcvr_system_bank_1e_2_clk_50 
  pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50 
  pcie_xcvr_system_bank_1e_3_clk_100 
  pcie_xcvr_system_bank_1e_3_clk_50 
  pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50 

All Components
   product_info_0 product_info 1.0
   xcvr_atx_pll_1c altera_xcvr_atx_pll_s10_htile 17.1
   pcie_xcvr_system_bank_1c_0 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1c_0_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1c_0_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1c_0_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1c_1 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1c_1_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1c_1_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1c_1_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1c_2 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1c_2_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1c_2_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1c_2_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1c_3 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1c_3_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1c_3_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1c_3_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1c_4 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1c_4_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1c_4_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1c_4_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1c_5 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1c_5_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1c_5_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1c_5_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1d_0 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1d_0_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1d_0_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1d_0_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1d_1 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1d_1_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1d_1_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1d_1_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1d_2 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1d_2_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1d_2_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1d_2_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1d_3 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1d_3_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1d_3_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1d_3_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1d_4 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1d_4_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1d_4_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1d_4_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1d_5 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1d_5_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1d_5_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1d_5_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1e_0 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1e_0_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1e_0_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1e_0_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1e_1 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1e_1_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1e_1_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1e_1_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1e_2 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1e_2_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1e_2_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1e_2_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
   pcie_xcvr_system_bank_1e_3 pcie_xcvr_test 1.0
   pcie_xcvr_system_bank_1e_3_mm_bridge_0 altera_avalon_mm_bridge 17.1
   pcie_xcvr_system_bank_1e_3_nativePHY_loopback_cont_0 nativePHY_loopback_cont 1.0
   pcie_xcvr_system_bank_1e_3_pcie_xcvr_test_default_pma_settings_conf_0 default_pma_settings_conf 1.0
   pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 altera_xcvr_native_s10_htile 17.1
   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0 xcvr_test_system 1.0
   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 16.930
   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 16.930
   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 16.930
Memory Map
master_0 pcie_xcvr_system_bank_1c_0_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1c_1_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1c_2_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1c_3_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1c_4_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1c_5_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1d_0_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1d_1_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1d_2_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1d_3_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1d_4_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1d_5_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1e_0_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1e_1_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1e_2_pcie_xcvr_test_default_pma_settings_conf_0 pcie_xcvr_system_bank_1e_3_pcie_xcvr_test_default_pma_settings_conf_0
 master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master
  product_info_0
avalon_slave_0  0x00000000
  xcvr_atx_pll_1c
reconfig_avmm0  0x00200000
  pcie_xcvr_system_bank_1c_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1c_0_nativePHY_loopback_cont_0
csr  0x00013000
  pcie_xcvr_system_bank_1c_0_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x00012000
  pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0
reconfig_avmm  0x00010000 0x00000000
  pcie_xcvr_system_bank_1c_0_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00015020
  pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00015000
  pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_freq_counter_0
csr  0x00015200
  pcie_xcvr_system_bank_1c_1
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1c_1_nativePHY_loopback_cont_0
csr  0x00023000
  pcie_xcvr_system_bank_1c_1_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x00022000
  pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0
reconfig_avmm  0x00020000 0x00000000
  pcie_xcvr_system_bank_1c_1_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00025020
  pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00025000
  pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_freq_counter_0
csr  0x00025200
  pcie_xcvr_system_bank_1c_2
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1c_2_nativePHY_loopback_cont_0
csr  0x00033000
  pcie_xcvr_system_bank_1c_2_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x00032000
  pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0
reconfig_avmm  0x00030000 0x00000000
  pcie_xcvr_system_bank_1c_2_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00035020
  pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00035000
  pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_freq_counter_0
csr  0x00035200
  pcie_xcvr_system_bank_1c_3
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1c_3_nativePHY_loopback_cont_0
csr  0x00043000
  pcie_xcvr_system_bank_1c_3_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x00042000
  pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0
reconfig_avmm  0x00040000 0x00000000
  pcie_xcvr_system_bank_1c_3_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00045020
  pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00045000
  pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_freq_counter_0
csr  0x00045200
  pcie_xcvr_system_bank_1c_4
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1c_4_nativePHY_loopback_cont_0
csr  0x00053000
  pcie_xcvr_system_bank_1c_4_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x00052000
  pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0
reconfig_avmm  0x00050000 0x00000000
  pcie_xcvr_system_bank_1c_4_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00055020
  pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00055000
  pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_freq_counter_0
csr  0x00055200
  pcie_xcvr_system_bank_1c_5
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1c_5_nativePHY_loopback_cont_0
csr  0x00063000
  pcie_xcvr_system_bank_1c_5_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x00062000
  pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0
reconfig_avmm  0x00060000 0x00000000
  pcie_xcvr_system_bank_1c_5_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00065020
  pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00065000
  pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_freq_counter_0
csr  0x00065200
  pcie_xcvr_system_bank_1d_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1d_0_nativePHY_loopback_cont_0
csr  0x00073000
  pcie_xcvr_system_bank_1d_0_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x00072000
  pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0
reconfig_avmm  0x00070000 0x00000000
  pcie_xcvr_system_bank_1d_0_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00075020
  pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00075000
  pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_freq_counter_0
csr  0x00075200
  pcie_xcvr_system_bank_1d_1
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1d_1_nativePHY_loopback_cont_0
csr  0x00083000
  pcie_xcvr_system_bank_1d_1_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x00082000
  pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0
reconfig_avmm  0x00080000 0x00000000
  pcie_xcvr_system_bank_1d_1_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00085020
  pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00085000
  pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_freq_counter_0
csr  0x00085200
  pcie_xcvr_system_bank_1d_2
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1d_2_nativePHY_loopback_cont_0
csr  0x00093000
  pcie_xcvr_system_bank_1d_2_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x00092000
  pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0
reconfig_avmm  0x00090000 0x00000000
  pcie_xcvr_system_bank_1d_2_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00095020
  pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00095000
  pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_freq_counter_0
csr  0x00095200
  pcie_xcvr_system_bank_1d_3
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1d_3_nativePHY_loopback_cont_0
csr  0x000a3000
  pcie_xcvr_system_bank_1d_3_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x000a2000
  pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0
reconfig_avmm  0x000a0000 0x00000000
  pcie_xcvr_system_bank_1d_3_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x000a5020
  pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x000a5000
  pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_freq_counter_0
csr  0x000a5200
  pcie_xcvr_system_bank_1d_4
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1d_4_nativePHY_loopback_cont_0
csr  0x000b3000
  pcie_xcvr_system_bank_1d_4_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x000b2000
  pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0
reconfig_avmm  0x000b0000 0x00000000
  pcie_xcvr_system_bank_1d_4_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x000b5020
  pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x000b5000
  pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_freq_counter_0
csr  0x000b5200
  pcie_xcvr_system_bank_1d_5
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1d_5_nativePHY_loopback_cont_0
csr  0x000c3000
  pcie_xcvr_system_bank_1d_5_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x000c2000
  pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0
reconfig_avmm  0x000c0000 0x00000000
  pcie_xcvr_system_bank_1d_5_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x000c5020
  pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x000c5000
  pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_freq_counter_0
csr  0x000c5200
  pcie_xcvr_system_bank_1e_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1e_0_nativePHY_loopback_cont_0
csr  0x000d3000
  pcie_xcvr_system_bank_1e_0_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x000d2000
  pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0
reconfig_avmm  0x000d0000 0x00000000
  pcie_xcvr_system_bank_1e_0_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x000d5020
  pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x000d5000
  pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_freq_counter_0
csr  0x000d5200
  pcie_xcvr_system_bank_1e_1
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1e_1_nativePHY_loopback_cont_0
csr  0x000e3000
  pcie_xcvr_system_bank_1e_1_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x000e2000
  pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0
reconfig_avmm  0x000e0000 0x00000000
  pcie_xcvr_system_bank_1e_1_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x000e5020
  pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x000e5000
  pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_freq_counter_0
csr  0x000e5200
  pcie_xcvr_system_bank_1e_2
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1e_2_nativePHY_loopback_cont_0
csr  0x000f3000
  pcie_xcvr_system_bank_1e_2_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x000f2000
  pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0
reconfig_avmm  0x000f0000 0x00000000
  pcie_xcvr_system_bank_1e_2_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x000f5020
  pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x000f5000
  pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_freq_counter_0
csr  0x000f5200
  pcie_xcvr_system_bank_1e_3
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1e_3_nativePHY_loopback_cont_0
csr  0x00103000
  pcie_xcvr_system_bank_1e_3_pcie_xcvr_test_default_pma_settings_conf_0
avalon_slave  0x00102000
  pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0
reconfig_avmm  0x00100000 0x00000000
  pcie_xcvr_system_bank_1e_3_xcvr_test_system_0
mm_bridge_0_s0 
  pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00105020
  pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00105000
  pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_freq_counter_0
csr  0x00105200

atx_pll_1c_refclk

altera_clock_bridge v17.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

clk_100

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

clk_50

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

master_0

altera_jtag_avalon_master v17.1
clk_50 clk   master_0
  clk
clk_reset  
  clk_reset
master   product_info_0
  avalon_slave_0
master_reset  
  reset
master   pcie_xcvr_system_bank_1c_0_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1c_1_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1c_2_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1c_3_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1c_4_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1c_5_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1d_0_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1d_1_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1d_2_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1d_3_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1d_4_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1d_5_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1e_0_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1e_1_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1e_2_mm_bridge_0
  s0
master   pcie_xcvr_system_bank_1e_3_mm_bridge_0
  s0
master   xcvr_atx_pll_1c
  reconfig_avmm0
master_reset   pcie_xcvr_system_bank_1c_0_clk_100
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1c_1_clk_100
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1c_2_clk_100
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1c_3_clk_100
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1c_4_clk_100
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1c_5_clk_100
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1d_0_clk_100
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1d_2_clk_100
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1d_3_clk_100
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1d_4_clk_100
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1d_5_clk_100
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1e_2_clk_100
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1e_3_clk_100
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1c_0_clk_50
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1c_1_clk_50
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1c_2_clk_50
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1c_3_clk_50
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1c_4_clk_50
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1c_5_clk_50
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1d_1_clk_50
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1d_2_clk_50
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1d_3_clk_50
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1d_4_clk_50
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1d_5_clk_50
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1e_1_clk_50
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1e_2_clk_50
  clk_in_reset
master_reset   pcie_xcvr_system_bank_1e_3_clk_50
  clk_in_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_pll_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1c_0_pll_locked_status pll_locked   pcie_xcvr_system_pll_status
  pll_locked_a
pcie_xcvr_system_bank_1c_2_pll_locked_status pll_locked  
  pll_locked_c
pcie_xcvr_system_bank_1c_4_pll_locked_status pll_locked  
  pll_locked_e
pcie_xcvr_system_bank_1d_0_pll_locked_status pll_locked  
  pll_locked_g
pcie_xcvr_system_bank_1d_2_pll_locked_status pll_locked  
  pll_locked_i
pcie_xcvr_system_bank_1d_4_pll_locked_status pll_locked  
  pll_locked_k
pcie_xcvr_system_bank_1e_0_pll_locked_status pll_locked  
  pll_locked_m
pcie_xcvr_system_bank_1e_2_pll_locked_status pll_locked  
  pll_locked_o
pll_locked   xcvr_atx_pll_1c
  pll_locked
pll_locked_b   pcie_xcvr_system_bank_1c_1_pll_locked_status
  pll_locked
pll_locked_d   pcie_xcvr_system_bank_1c_3_pll_locked_status
  pll_locked
pll_locked_f   pcie_xcvr_system_bank_1c_5_pll_locked_status
  pll_locked
pll_locked_h   pcie_xcvr_system_bank_1d_1_pll_locked_status
  pll_locked
pll_locked_j   pcie_xcvr_system_bank_1d_3_pll_locked_status
  pll_locked
pll_locked_l   pcie_xcvr_system_bank_1d_5_pll_locked_status
  pll_locked
pll_locked_n   pcie_xcvr_system_bank_1e_1_pll_locked_status
  pll_locked
pll_locked_p   pcie_xcvr_system_bank_1e_3_pll_locked_status
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

product_info_0

product_info v1.0
master_0 master   product_info_0
  avalon_slave_0
master_reset  
  reset
clk_50 clk  
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_atx_pll_1c

altera_xcvr_atx_pll_s10_htile v17.1
master_0 master   xcvr_atx_pll_1c
  reconfig_avmm0
clk_100 clk  
  reconfig_clk0
clk_reset  
  reconfig_reset0
atx_pll_1c_refclk out_clk  
  pll_refclk0
pcie_xcvr_system_pll_status pll_locked  
  pll_locked
mcgb_serial_clk   pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0
  tx_serial_clk0
mcgb_serial_clk   pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk   pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk   pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk   pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk   pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk   pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0
  tx_serial_clk0
tx_serial_clk   pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0
  tx_serial_clk0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1c_0_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1c_0_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1c_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_0_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1c_0_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_0_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1c_0_clk_50 clk   pcie_xcvr_system_bank_1c_0_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1c_0_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1c_0_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1c_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_0_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1c_0_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1c_0_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1c_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_0_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1c_0_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1c_0_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1c_0_pll_locked_status
  pll_locked_output
pll_locked_a   pcie_xcvr_system_bank_1c_0_xcvr_reset_control_s10_0
  pll_locked
pll_locked   pcie_xcvr_system_pll_status
  pll_locked_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1c_0_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1c_0_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1c_0_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1c_0_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1c_0_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c tx_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1c_0_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1c_0_clk_50 clk   pcie_xcvr_system_bank_1c_0_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1c_0_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1c_0_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1c_0_clk_50 clk   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_0_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1c_1_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1c_1_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1c_1_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_1_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_1_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1c_1_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_1_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1c_1_clk_50 clk   pcie_xcvr_system_bank_1c_1_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1c_1_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1c_1_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1c_1_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_1_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1c_1_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1c_1_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1c_1_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_1_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1c_1_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1c_1_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1c_1_pll_locked_status
  pll_locked_output
pcie_xcvr_system_pll_status pll_locked_b  
  pll_locked
pll_locked_a   pcie_xcvr_system_bank_1c_1_xcvr_reset_control_s10_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1c_1_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1c_1_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1c_1_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1c_1_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1c_1_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c tx_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1c_1_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1c_1_clk_50 clk   pcie_xcvr_system_bank_1c_1_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1c_1_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1c_1_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1c_1_clk_50 clk   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_1_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1c_2_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1c_2_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1c_2_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_2_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_2_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1c_2_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_2_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1c_2_clk_50 clk   pcie_xcvr_system_bank_1c_2_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1c_2_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1c_2_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1c_2_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_2_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1c_2_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1c_2_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1c_2_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_2_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1c_2_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1c_2_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1c_2_pll_locked_status
  pll_locked_output
pll_locked_a   pcie_xcvr_system_bank_1c_2_xcvr_reset_control_s10_0
  pll_locked
pll_locked   pcie_xcvr_system_pll_status
  pll_locked_c


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1c_2_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1c_2_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1c_2_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1c_2_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1c_2_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c tx_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1c_2_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1c_2_clk_50 clk   pcie_xcvr_system_bank_1c_2_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1c_2_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1c_2_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1c_2_clk_50 clk   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_2_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1c_3_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1c_3_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1c_3_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_3_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_3_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1c_3_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_3_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1c_3_clk_50 clk   pcie_xcvr_system_bank_1c_3_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1c_3_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1c_3_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1c_3_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_3_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1c_3_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1c_3_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1c_3_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_3_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1c_3_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1c_3_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1c_3_pll_locked_status
  pll_locked_output
pcie_xcvr_system_pll_status pll_locked_d  
  pll_locked
pll_locked_a   pcie_xcvr_system_bank_1c_3_xcvr_reset_control_s10_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1c_3_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1c_3_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1c_3_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1c_3_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1c_3_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c tx_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1c_3_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1c_3_clk_50 clk   pcie_xcvr_system_bank_1c_3_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1c_3_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1c_3_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1c_3_clk_50 clk   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_3_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1c_4_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1c_4_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1c_4_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_4_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_4_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1c_4_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_4_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1c_4_clk_50 clk   pcie_xcvr_system_bank_1c_4_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1c_4_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1c_4_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1c_4_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_4_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1c_4_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1c_4_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1c_4_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_4_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1c_4_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1c_4_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1c_4_pll_locked_status
  pll_locked_output
pll_locked_a   pcie_xcvr_system_bank_1c_4_xcvr_reset_control_s10_0
  pll_locked
pll_locked   pcie_xcvr_system_pll_status
  pll_locked_e


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1c_4_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1c_4_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1c_4_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1c_4_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1c_4_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c tx_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1c_4_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1c_4_clk_50 clk   pcie_xcvr_system_bank_1c_4_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1c_4_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1c_4_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1c_4_clk_50 clk   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_4_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1c_5_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1c_5_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1c_5_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_5_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_5_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1c_5_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_5_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1c_5_clk_50 clk   pcie_xcvr_system_bank_1c_5_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1c_5_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1c_5_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1c_5_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_5_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1c_5_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1c_5_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1c_5_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_5_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1c_5_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1c_5_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1c_5_pll_locked_status
  pll_locked_output
pcie_xcvr_system_pll_status pll_locked_f  
  pll_locked
pll_locked_a   pcie_xcvr_system_bank_1c_5_xcvr_reset_control_s10_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1c_5_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1c_5_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1c_5_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1c_5_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1c_5_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c tx_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1c_5_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1c_5_clk_50 clk   pcie_xcvr_system_bank_1c_5_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1c_5_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1c_5_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1c_5_clk_50 clk   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1c_5_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1d_0_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1d_0_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1d_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_0_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1d_0_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_0_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1d_0_clk_50 clk   pcie_xcvr_system_bank_1d_0_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1d_0_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1d_0_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1d_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_0_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1d_0_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1d_0_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1d_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_0_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1d_0_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1d_0_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1d_0_pll_locked_status
  pll_locked_output
pll_locked_a   pcie_xcvr_system_bank_1d_0_xcvr_reset_control_s10_0
  pll_locked
pll_locked   pcie_xcvr_system_pll_status
  pll_locked_g


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1d_0_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1d_0_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1d_0_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1d_0_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1d_0_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1d_0_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1d_0_clk_50 clk   pcie_xcvr_system_bank_1d_0_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1d_0_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1d_0_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1d_0_clk_50 clk   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_0_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1d_1_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1d_1_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1d_1_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_1_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_1_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1d_1_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_1_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1d_1_clk_50 clk   pcie_xcvr_system_bank_1d_1_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1d_1_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1d_1_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1d_1_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_1_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1d_1_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1d_1_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1d_1_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_1_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1d_1_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1d_1_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1d_1_pll_locked_status
  pll_locked_output
pcie_xcvr_system_pll_status pll_locked_h  
  pll_locked
pll_locked_a   pcie_xcvr_system_bank_1d_1_xcvr_reset_control_s10_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1d_1_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1d_1_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1d_1_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1d_1_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1d_1_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1d_1_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1d_1_clk_50 clk   pcie_xcvr_system_bank_1d_1_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1d_1_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1d_1_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1d_1_clk_50 clk   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_1_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1d_2_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1d_2_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1d_2_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_2_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_2_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1d_2_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_2_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1d_2_clk_50 clk   pcie_xcvr_system_bank_1d_2_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1d_2_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1d_2_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1d_2_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_2_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1d_2_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1d_2_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1d_2_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_2_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1d_2_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1d_2_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1d_2_pll_locked_status
  pll_locked_output
pll_locked_a   pcie_xcvr_system_bank_1d_2_xcvr_reset_control_s10_0
  pll_locked
pll_locked   pcie_xcvr_system_pll_status
  pll_locked_i


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1d_2_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1d_2_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1d_2_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1d_2_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1d_2_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1d_2_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1d_2_clk_50 clk   pcie_xcvr_system_bank_1d_2_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1d_2_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1d_2_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1d_2_clk_50 clk   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_2_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1d_3_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1d_3_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1d_3_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_3_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_3_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1d_3_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_3_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1d_3_clk_50 clk   pcie_xcvr_system_bank_1d_3_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1d_3_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1d_3_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1d_3_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_3_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1d_3_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1d_3_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1d_3_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_3_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1d_3_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1d_3_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1d_3_pll_locked_status
  pll_locked_output
pcie_xcvr_system_pll_status pll_locked_j  
  pll_locked
pll_locked_a   pcie_xcvr_system_bank_1d_3_xcvr_reset_control_s10_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1d_3_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1d_3_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1d_3_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1d_3_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1d_3_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1d_3_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1d_3_clk_50 clk   pcie_xcvr_system_bank_1d_3_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1d_3_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1d_3_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1d_3_clk_50 clk   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_3_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1d_4_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1d_4_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1d_4_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_4_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_4_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1d_4_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_4_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1d_4_clk_50 clk   pcie_xcvr_system_bank_1d_4_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1d_4_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1d_4_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1d_4_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_4_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1d_4_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1d_4_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1d_4_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_4_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1d_4_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1d_4_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1d_4_pll_locked_status
  pll_locked_output
pll_locked_a   pcie_xcvr_system_bank_1d_4_xcvr_reset_control_s10_0
  pll_locked
pll_locked   pcie_xcvr_system_pll_status
  pll_locked_k


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1d_4_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1d_4_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1d_4_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1d_4_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1d_4_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1d_4_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1d_4_clk_50 clk   pcie_xcvr_system_bank_1d_4_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1d_4_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1d_4_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1d_4_clk_50 clk   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_4_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1d_5_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1d_5_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1d_5_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_5_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_5_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1d_5_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_5_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1d_5_clk_50 clk   pcie_xcvr_system_bank_1d_5_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1d_5_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1d_5_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1d_5_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_5_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1d_5_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1d_5_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1d_5_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_5_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1d_5_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1d_5_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1d_5_pll_locked_status
  pll_locked_output
pcie_xcvr_system_pll_status pll_locked_l  
  pll_locked
pll_locked_a   pcie_xcvr_system_bank_1d_5_xcvr_reset_control_s10_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1d_5_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1d_5_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1d_5_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1d_5_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1d_5_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1d_5_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1d_5_clk_50 clk   pcie_xcvr_system_bank_1d_5_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1d_5_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1d_5_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1d_5_clk_50 clk   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1d_5_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1e_0_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1e_0_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1e_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_0_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1e_0_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_0_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1e_0_clk_50 clk   pcie_xcvr_system_bank_1e_0_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1e_0_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1e_0_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1e_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_0_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1e_0_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1e_0_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1e_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_0_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1e_0_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1e_0_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1e_0_pll_locked_status
  pll_locked_output
pll_locked_a   pcie_xcvr_system_bank_1e_0_xcvr_reset_control_s10_0
  pll_locked
pll_locked   pcie_xcvr_system_pll_status
  pll_locked_m


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1e_0_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1e_0_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1e_0_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1e_0_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1e_0_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1e_0_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1e_0_clk_50 clk   pcie_xcvr_system_bank_1e_0_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1e_0_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1e_0_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1e_0_clk_50 clk   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1e_0_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1e_1_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1e_1_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1e_1_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_1_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_1_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1e_1_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_1_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1e_1_clk_50 clk   pcie_xcvr_system_bank_1e_1_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1e_1_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1e_1_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1e_1_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_1_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1e_1_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1e_1_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1e_1_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_1_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1e_1_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1e_1_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1e_1_pll_locked_status
  pll_locked_output
pcie_xcvr_system_pll_status pll_locked_n  
  pll_locked
pll_locked_a   pcie_xcvr_system_bank_1e_1_xcvr_reset_control_s10_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1e_1_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1e_1_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1e_1_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1e_1_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1e_1_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1e_1_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1e_1_clk_50 clk   pcie_xcvr_system_bank_1e_1_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1e_1_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1e_1_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1e_1_clk_50 clk   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1e_1_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1e_2_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1e_2_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1e_2_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_2_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_2_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1e_2_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_2_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1e_2_clk_50 clk   pcie_xcvr_system_bank_1e_2_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1e_2_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1e_2_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1e_2_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_2_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1e_2_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1e_2_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1e_2_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_2_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1e_2_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1e_2_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1e_2_pll_locked_status
  pll_locked_output
pll_locked_a   pcie_xcvr_system_bank_1e_2_xcvr_reset_control_s10_0
  pll_locked
pll_locked   pcie_xcvr_system_pll_status
  pll_locked_o


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1e_2_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1e_2_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1e_2_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1e_2_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1e_2_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1e_2_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1e_2_clk_50 clk   pcie_xcvr_system_bank_1e_2_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1e_2_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1e_2_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1e_2_clk_50 clk   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1e_2_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3

pcie_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_clk_100

clock_source vnull
clk_100 clk   pcie_xcvr_system_bank_1e_3_clk_100
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0
  reconfig_clk
clk_reset  
  reconfig_reset
clk_reset   pcie_xcvr_system_bank_1e_3_xcvr_reset_control_s10_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_clk_50

clock_source vnull
clk_50 clk   pcie_xcvr_system_bank_1e_3_clk_50
  clk_in
clk_reset  
  clk_in_reset
master_0 master_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_3_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_3_xcvr_reset_control_s10_0
  clock
clk   pcie_xcvr_system_bank_1e_3_pcie_xcvr_test_default_pma_settings_conf_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_3_nativePHY_loopback_cont_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_mm_bridge_0

altera_avalon_mm_bridge v17.1
pcie_xcvr_system_bank_1e_3_clk_50 clk   pcie_xcvr_system_bank_1e_3_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   pcie_xcvr_system_bank_1e_3_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
m0   pcie_xcvr_system_bank_1e_3_nativePHY_loopback_cont_0
  csr
m0   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0
  s0
m0   pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_nativePHY_loopback_cont_0

nativePHY_loopback_cont v1.0
pcie_xcvr_system_bank_1e_3_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_3_nativePHY_loopback_cont_0
  csr
pcie_xcvr_system_bank_1e_3_clk_50 clk  
  clock
clk_reset  
  reset
pll_locked   pcie_xcvr_system_bank_1e_3_pll_locked_status
  pll_locked_output
rx_is_lockedtoref   pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_pcie_xcvr_test_default_pma_settings_conf_0

default_pma_settings_conf v1.0
pcie_xcvr_system_bank_1e_3_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_3_pcie_xcvr_test_default_pma_settings_conf_0
  avalon_slave
pcie_xcvr_system_bank_1e_3_clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_pll_locked_status

pll_status_interconnect v1.0
pcie_xcvr_system_bank_1e_3_nativePHY_loopback_cont_0 pll_locked   pcie_xcvr_system_bank_1e_3_pll_locked_status
  pll_locked_output
pcie_xcvr_system_pll_status pll_locked_p  
  pll_locked
pll_locked_a   pcie_xcvr_system_bank_1e_3_xcvr_reset_control_s10_0
  pll_locked


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0

altera_xcvr_native_s10_htile v17.1
pcie_xcvr_system_bank_1e_3_pcie_xcvr_test_default_pma_settings_conf_0 avalon_master   pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0
  reconfig_avmm
pcie_xcvr_system_bank_1e_3_mm_bridge_0 m0  
  reconfig_avmm
pcie_xcvr_system_bank_1e_3_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
pcie_xcvr_system_bank_1e_3_xcvr_reset_control_s10_0 rx_analogreset_stat  
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat
pcie_xcvr_system_bank_1e_3_nativePHY_loopback_cont_0 rx_is_lockedtoref  
  rx_is_lockedtoref
rx_seriallpbken  
  rx_seriallpbken
atx_pll_1c_refclk out_clk  
  rx_cdr_refclk0
xcvr_atx_pll_1c mcgb_serial_clk  
  tx_serial_clk0
rx_clkout   pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_clkout2   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
tx_clkout2  
  tx_clkout2
rx_analogreset   pcie_xcvr_system_bank_1e_3_xcvr_reset_control_s10_0
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_reset_control_s10_0

altera_xcvr_reset_control_s10 v17.1
pcie_xcvr_system_bank_1e_3_clk_50 clk   pcie_xcvr_system_bank_1e_3_xcvr_reset_control_s10_0
  clock
pcie_xcvr_system_bank_1e_3_pll_locked_status pll_locked_a  
  pll_locked
pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 rx_analogreset  
  rx_analogreset
rx_cal_busy  
  rx_cal_busy
rx_digitalreset  
  rx_digitalreset
rx_is_lockedtodata  
  rx_is_lockedtodata
tx_analogreset_stat  
  tx_analogreset_stat
tx_digitalreset  
  tx_digitalreset
pcie_xcvr_system_bank_1e_3_clk_100 clk_reset  
  reset
rx_analogreset_stat   pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0
  rx_analogreset_stat
rx_digitalreset_stat  
  rx_digitalreset_stat
tx_analogreset  
  tx_analogreset
tx_cal_busy  
  tx_cal_busy
tx_digitalreset_stat  
  tx_digitalreset_stat


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0

xcvr_st_converter v1.0
pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 rx_clkout   pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out  
  tx_data_a
rx_clkout_a_output   pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50

clock_source vnull
pcie_xcvr_system_bank_1e_3_clk_50 clk   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v16.930
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v16.930
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0 m0   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_freq_counter_0
  csr
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v16.930
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50 clk   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
pcie_xcvr_system_bank_1e_3_mm_bridge_0 m0  
  s0
m0   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_freq_counter_0
  csr
m0   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_rx_fifo

fifo v16.930
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_tx_fifo

fifo v16.930
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 rx_clkout2  
  rx_clkout2
tx_clkout2  
  tx_clkout2
tx_clkout2_sample   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_rx_fifo fifo_input   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_tx_fifo fifo_input   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
data_pattern_generator_pattern_out_fifo_write   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_tx_fifo
  fifo_output
data_pattern_generator_pattern_out   pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0
  tx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)
generation took 0.02 seconds rendering took 0.44 seconds