bup_qsys

2017.11.28.20:27:51 Datasheet
Overview
  clk_125m  bup_qsys
  sys_clk 
Processor
   cpu Nios II 17.1
All Components
   button_pio altera_avalon_pio 17.1
   cpu altera_nios2_gen2 17.1
   descriptor_memory altera_avalon_onchip_memory2 17.1
   ext_flash altera_generic_tristate_controller 17.1
   flash_select altera_avalon_pio 17.1
   jtag_uart altera_avalon_jtag_uart 17.1
   led_pio altera_avalon_pio 17.1
   onchip_ram_m9 altera_avalon_onchip_memory2 17.1
   opencores_i2c_0 opencores_i2c 9.1
   sys_clk_timer altera_avalon_timer 17.1
   sysid altera_avalon_sysid_qsys 17.1
   tse_0_dma_rx altera_msgdma 17.1
   tse_0_dma_tx altera_msgdma 17.1
   tse_0_tse altera_eth_tse 17.1
Memory Map
cpu tse_0_dma_rx tse_0_dma_tx
 data_master  instruction_master  descriptor_read_master  descriptor_write_master  mm_write  descriptor_read_master  descriptor_write_master  mm_read
  button_pio
s1  0x100a0000
  cpu
debug_mem_slave  0x10002800 0x10002800
  descriptor_memory
s1  0x10040000 0x00000000 0x00000000 0x00000000 0x00000000
  ext_flash
uas  0x00000000 0x00000000
  flash_select
s1  0x10050000
  jtag_uart
avalon_jtag_slave  0x10050010
  led_pio
s1  0x10060020
  onchip_ram_m9
s1  0x10200000 0x10200000 0x10200000 0x10200000
  opencores_i2c_0
avalon_slave_0  0x10090000
  sys_clk_timer
s1  0x10070040
  sysid
control_slave  0x10080000
  tse_0_dma_rx
csr  0x10003400
prefetcher_csr  0x10004000
  tse_0_dma_tx
csr  0x10003440
prefetcher_csr  0x10005000
  tse_0_tse
control_port  0x10020000

bup_qsys_cfi_flash_atb_bridge_0

altera_tristate_conduit_bridge v17.1
sys_clk clk   bup_qsys_cfi_flash_atb_bridge_0
  clk
clk_reset  
  reset
cpu debug_reset_request  
  reset
ext_flash tcm  
  tcs


Parameters

generateLegacySim false
  

Software Assignments

(none)

button_pio

altera_avalon_pio v17.1
cpu data_master   button_pio
  s1
debug_reset_request  
  reset
sys_clk clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 3
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

clk_125m

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

cpu

altera_nios2_gen2 v17.1
sys_clk clk   cpu
  clk
clk_reset  
  reset
data_master   jtag_uart
  avalon_jtag_slave
irq  
  irq
debug_reset_request  
  reset
data_master   opencores_i2c_0
  avalon_slave_0
debug_reset_request  
  clock_reset
data_master   tse_0_tse
  control_port
debug_reset_request  
  reset_connection
data_master   sysid
  control_slave
debug_reset_request  
  reset
data_master   tse_0_dma_rx
  csr
data_master  
  prefetcher_csr
irq  
  csr_irq
debug_reset_request  
  reset_n
data_master   tse_0_dma_tx
  csr
data_master  
  prefetcher_csr
irq  
  csr_irq
debug_reset_request  
  reset_n
data_master   onchip_ram_m9
  s1
instruction_master  
  s1
debug_reset_request  
  reset1
data_master   descriptor_memory
  s1
debug_reset_request  
  reset1
data_master   led_pio
  s1
debug_reset_request  
  reset
data_master   sys_clk_timer
  s1
irq  
  irq
debug_reset_request  
  reset
data_master   button_pio
  s1
debug_reset_request  
  reset
data_master   flash_select
  s1
debug_reset_request  
  reset
data_master   ext_flash
  uas
instruction_master  
  uas
debug_reset_request  
  reset
debug_reset_request   bup_qsys_cfi_flash_atb_bridge_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x10002820
CPU_ARCH_NIOS2_R1
CPU_FREQ 50000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "fast"
DATA_ADDR_WIDTH 29
DCACHE_BYPASS_MASK 0x80000000
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 65536
EXCEPTION_ADDR 0x10200120
FLASH_ACCELERATOR_LINES 0
FLASH_ACCELERATOR_LINE_SIZE 0
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_EXTRA_EXCEPTION_INFO
HAS_ILLEGAL_INSTRUCTION_EXCEPTION
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 65536
INITDA_SUPPORTED
INST_ADDR_WIDTH 29
NUM_OF_SHADOW_REG_SETS 0
OCI_VERSION 1
RESET_ADDR 0x05f00000

descriptor_memory

altera_avalon_onchip_memory2 v17.1
cpu data_master   descriptor_memory
  s1
debug_reset_request  
  reset1
tse_0_dma_tx descriptor_read_master  
  s1
descriptor_write_master  
  s1
tse_0_dma_rx descriptor_read_master  
  s1
descriptor_write_master  
  s1
sys_clk clk  
  clk1
clk_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE descriptor_memory_descriptor_memory
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 8192
WRITABLE 1

ext_flash

altera_generic_tristate_controller v17.1
cpu data_master   ext_flash
  uas
instruction_master  
  uas
debug_reset_request  
  reset
sys_clk clk  
  clk
clk_reset  
  reset
tcm   bup_qsys_cfi_flash_atb_bridge_0
  tcs


Parameters

generateLegacySim false
  

Software Assignments

HOLD_VALUE 33
SETUP_VALUE 33
SIZE 134217728u
TIMING_UNITS ns
WAIT_VALUE 144

flash_select

altera_avalon_pio v17.1
cpu data_master   flash_select
  s1
debug_reset_request  
  reset
sys_clk clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

jtag_uart

altera_avalon_jtag_uart v17.1
cpu data_master   jtag_uart
  avalon_jtag_slave
irq  
  irq
debug_reset_request  
  reset
sys_clk clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

READ_DEPTH 2048
READ_THRESHOLD 8
WRITE_DEPTH 2048
WRITE_THRESHOLD 8

led_pio

altera_avalon_pio v17.1
cpu data_master   led_pio
  s1
debug_reset_request  
  reset
sys_clk clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 8
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 255

onchip_ram_m9

altera_avalon_onchip_memory2 v17.1
cpu data_master   onchip_ram_m9
  s1
instruction_master  
  s1
debug_reset_request  
  reset1
tse_0_dma_tx mm_read  
  s1
tse_0_dma_rx mm_write  
  s1
sys_clk clk  
  clk1
clk_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE bup_qsys_onchip_ram_m9_onchip_ram_m9
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 2097152
WRITABLE 1

opencores_i2c_0

opencores_i2c v9.1
cpu data_master   opencores_i2c_0
  avalon_slave_0
debug_reset_request  
  clock_reset
sys_clk clk  
  clock
clk_reset  
  clock_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

sys_clk

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

sys_clk_timer

altera_avalon_timer v17.1
cpu data_master   sys_clk_timer
  s1
irq  
  irq
debug_reset_request  
  reset
sys_clk clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 499999
MULT 0.001
PERIOD 10
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 100
TIMEOUT_PULSE_OUTPUT 0

sysid

altera_avalon_sysid_qsys v17.1
cpu data_master   sysid
  control_slave
debug_reset_request  
  reset
sys_clk clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ID -87110915
TIMESTAMP 0

tse_0_dma_rx

altera_msgdma v17.1
cpu data_master   tse_0_dma_rx
  csr
data_master  
  prefetcher_csr
irq  
  csr_irq
debug_reset_request  
  reset_n
tse_0_tse receive  
  st_sink
sys_clk clk  
  clock
clk_reset  
  reset_n
descriptor_read_master   descriptor_memory
  s1
descriptor_write_master  
  s1
mm_write   onchip_ram_m9
  s1


Parameters

generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
CHANNEL_ENABLE 0
CHANNEL_ENABLE_DERIVED 0
CHANNEL_WIDTH 8
DATA_FIFO_DEPTH 64
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 128
DMA_MODE 2
ENHANCED_FEATURES 0
ERROR_ENABLE 1
ERROR_ENABLE_DERIVED 1
ERROR_WIDTH 6
MAX_BURST_COUNT 2
MAX_BYTE 262144
MAX_STRIDE 1
PACKET_ENABLE 1
PACKET_ENABLE_DERIVED 1
PREFETCHER_ENABLE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_PORT 2
STRIDE_ENABLE 0
STRIDE_ENABLE_DERIVED 0
TRANSFER_TYPE Aligned Accesses

tse_0_dma_tx

altera_msgdma v17.1
cpu data_master   tse_0_dma_tx
  csr
data_master  
  prefetcher_csr
irq  
  csr_irq
debug_reset_request  
  reset_n
sys_clk clk  
  clock
clk_reset  
  reset_n
descriptor_read_master   descriptor_memory
  s1
descriptor_write_master  
  s1
mm_read   onchip_ram_m9
  s1
st_source   tse_0_tse
  transmit


Parameters

generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
CHANNEL_ENABLE 0
CHANNEL_ENABLE_DERIVED 0
CHANNEL_WIDTH 8
DATA_FIFO_DEPTH 128
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 128
DMA_MODE 1
ENHANCED_FEATURES 0
ERROR_ENABLE 1
ERROR_ENABLE_DERIVED 1
ERROR_WIDTH 1
MAX_BURST_COUNT 2
MAX_BYTE 262144
MAX_STRIDE 1
PACKET_ENABLE 1
PACKET_ENABLE_DERIVED 1
PREFETCHER_ENABLE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_PORT 2
STRIDE_ENABLE 0
STRIDE_ENABLE_DERIVED 0
TRANSFER_TYPE Aligned Accesses

tse_0_tse

altera_eth_tse v17.1
cpu data_master   tse_0_tse
  control_port
debug_reset_request  
  reset_connection
tse_0_dma_tx st_source  
  transmit
sys_clk clk  
  control_port_clock_connection
clk  
  receive_clock_connection
clk  
  transmit_clock_connection
clk_reset  
  reset_connection
clk_125m clk  
  pcs_ref_clk_clock_connection
clk_reset  
  reset_connection
receive   tse_0_dma_rx
  st_sink


Parameters

generateLegacySim false
  

Software Assignments

ENABLE_MACLITE 0
FIFO_WIDTH 32
IS_MULTICHANNEL_MAC 0
MACLITE_GIGE 0
MDIO_SHARED 0
NUMBER_OF_CHANNEL 1
NUMBER_OF_MAC_MDIO_SHARED 1
PCS 1
PCS_ID 0
PCS_SGMII 1
RECEIVE_FIFO_DEPTH 4096
REGISTER_SHARED 0
RGMII 0
TRANSMIT_FIFO_DEPTH 4096
USE_MDIO 1
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