pcie_xcvr_system |
|
2017.11.13.11:25:25 | Datasheet |
clk_100 | pcie_xcvr_system |
clk_50 | |
pcie_xcvr_system_bank_1c_0_clk_100 | |
pcie_xcvr_system_bank_1c_0_clk_50 | |
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1c_1_clk_100 | |
pcie_xcvr_system_bank_1c_1_clk_50 | |
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1c_2_clk_100 | |
pcie_xcvr_system_bank_1c_2_clk_50 | |
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1c_3_clk_100 | |
pcie_xcvr_system_bank_1c_3_clk_50 | |
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1c_4_clk_100 | |
pcie_xcvr_system_bank_1c_4_clk_50 | |
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1c_5_clk_100 | |
pcie_xcvr_system_bank_1c_5_clk_50 | |
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1d_0_clk_100 | |
pcie_xcvr_system_bank_1d_0_clk_50 | |
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1d_1_clk_100 | |
pcie_xcvr_system_bank_1d_1_clk_50 | |
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1d_2_clk_100 | |
pcie_xcvr_system_bank_1d_2_clk_50 | |
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1d_3_clk_100 | |
pcie_xcvr_system_bank_1d_3_clk_50 | |
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1d_4_clk_100 | |
pcie_xcvr_system_bank_1d_4_clk_50 | |
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1d_5_clk_100 | |
pcie_xcvr_system_bank_1d_5_clk_50 | |
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1e_0_clk_100 | |
pcie_xcvr_system_bank_1e_0_clk_50 | |
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1e_1_clk_100 | |
pcie_xcvr_system_bank_1e_1_clk_50 | |
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1e_2_clk_100 | |
pcie_xcvr_system_bank_1e_2_clk_50 | |
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50 | |
pcie_xcvr_system_bank_1e_3_clk_100 | |
pcie_xcvr_system_bank_1e_3_clk_50 | |
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50 | |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1c_0_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1c_0_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1c_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_0_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1c_0_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_0_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_clk_50 | clk | pcie_xcvr_system_bank_1c_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_0_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1c_0_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_0_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1c_0_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1c_0_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_0_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1c_0_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1c_0_pll_locked_status | |
pll_locked_output | |||
pll_locked_a | pcie_xcvr_system_bank_1c_0_xcvr_reset_control_s10_0 | ||
pll_locked | |||
pll_locked | pcie_xcvr_system_pll_status | ||
pll_locked_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1c_0_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1c_0_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1c_0_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1c_0_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | tx_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1c_0_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_clk_50 | clk | pcie_xcvr_system_bank_1c_0_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1c_0_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1c_0_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_clk_50 | clk | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1c_0_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1c_0_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1c_0_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1c_0_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1c_1_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1c_1_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1c_1_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_1_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_1_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1c_1_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_1_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_clk_50 | clk | pcie_xcvr_system_bank_1c_1_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_1_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1c_1_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_1_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1c_1_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1c_1_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_1_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1c_1_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1c_1_pll_locked_status | |
pll_locked_output | |||
pcie_xcvr_system_pll_status | pll_locked_b | ||
pll_locked | |||
pll_locked_a | pcie_xcvr_system_bank_1c_1_xcvr_reset_control_s10_0 | ||
pll_locked |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1c_1_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1c_1_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1c_1_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1c_1_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | tx_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1c_1_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_clk_50 | clk | pcie_xcvr_system_bank_1c_1_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1c_1_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1c_1_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_clk_50 | clk | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1c_1_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1c_1_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1c_1_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1c_1_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1c_2_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1c_2_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1c_2_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_2_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_2_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1c_2_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_2_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_clk_50 | clk | pcie_xcvr_system_bank_1c_2_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_2_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1c_2_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_2_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1c_2_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1c_2_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_2_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1c_2_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1c_2_pll_locked_status | |
pll_locked_output | |||
pll_locked_a | pcie_xcvr_system_bank_1c_2_xcvr_reset_control_s10_0 | ||
pll_locked | |||
pll_locked | pcie_xcvr_system_pll_status | ||
pll_locked_c |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1c_2_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1c_2_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1c_2_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1c_2_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | tx_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1c_2_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_clk_50 | clk | pcie_xcvr_system_bank_1c_2_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1c_2_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1c_2_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_clk_50 | clk | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1c_2_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1c_2_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1c_2_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1c_2_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1c_3_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1c_3_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1c_3_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_3_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_3_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1c_3_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_3_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_clk_50 | clk | pcie_xcvr_system_bank_1c_3_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_3_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1c_3_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_3_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1c_3_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1c_3_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_3_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1c_3_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1c_3_pll_locked_status | |
pll_locked_output | |||
pcie_xcvr_system_pll_status | pll_locked_d | ||
pll_locked | |||
pll_locked_a | pcie_xcvr_system_bank_1c_3_xcvr_reset_control_s10_0 | ||
pll_locked |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1c_3_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1c_3_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1c_3_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1c_3_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | tx_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1c_3_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_clk_50 | clk | pcie_xcvr_system_bank_1c_3_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1c_3_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1c_3_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_clk_50 | clk | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1c_3_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1c_3_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1c_3_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1c_3_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1c_4_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1c_4_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1c_4_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_4_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_4_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1c_4_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_4_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_clk_50 | clk | pcie_xcvr_system_bank_1c_4_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_4_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1c_4_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_4_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1c_4_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1c_4_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_4_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1c_4_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1c_4_pll_locked_status | |
pll_locked_output | |||
pll_locked_a | pcie_xcvr_system_bank_1c_4_xcvr_reset_control_s10_0 | ||
pll_locked | |||
pll_locked | pcie_xcvr_system_pll_status | ||
pll_locked_e |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1c_4_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1c_4_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1c_4_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1c_4_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | tx_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1c_4_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_clk_50 | clk | pcie_xcvr_system_bank_1c_4_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1c_4_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1c_4_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_clk_50 | clk | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1c_4_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1c_4_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1c_4_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1c_4_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1c_5_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1c_5_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1c_5_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_5_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_5_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1c_5_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_5_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_clk_50 | clk | pcie_xcvr_system_bank_1c_5_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_5_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1c_5_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_5_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1c_5_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1c_5_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_5_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1c_5_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1c_5_pll_locked_status | |
pll_locked_output | |||
pcie_xcvr_system_pll_status | pll_locked_f | ||
pll_locked | |||
pll_locked_a | pcie_xcvr_system_bank_1c_5_xcvr_reset_control_s10_0 | ||
pll_locked |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1c_5_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1c_5_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1c_5_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1c_5_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | tx_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1c_5_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_clk_50 | clk | pcie_xcvr_system_bank_1c_5_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1c_5_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1c_5_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_clk_50 | clk | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1c_5_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1c_5_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1c_5_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1c_5_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1d_0_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1d_0_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1d_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_0_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1d_0_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_0_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_clk_50 | clk | pcie_xcvr_system_bank_1d_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_0_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1d_0_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_0_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1d_0_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1d_0_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_0_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1d_0_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1d_0_pll_locked_status | |
pll_locked_output | |||
pll_locked_a | pcie_xcvr_system_bank_1d_0_xcvr_reset_control_s10_0 | ||
pll_locked | |||
pll_locked | pcie_xcvr_system_pll_status | ||
pll_locked_g |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1d_0_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1d_0_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1d_0_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1d_0_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | mcgb_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1d_0_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_clk_50 | clk | pcie_xcvr_system_bank_1d_0_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1d_0_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1d_0_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_clk_50 | clk | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1d_0_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1d_0_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1d_0_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1d_0_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1d_1_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1d_1_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1d_1_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_1_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_1_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1d_1_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_1_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_clk_50 | clk | pcie_xcvr_system_bank_1d_1_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_1_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1d_1_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_1_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1d_1_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1d_1_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_1_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1d_1_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1d_1_pll_locked_status | |
pll_locked_output | |||
pcie_xcvr_system_pll_status | pll_locked_h | ||
pll_locked | |||
pll_locked_a | pcie_xcvr_system_bank_1d_1_xcvr_reset_control_s10_0 | ||
pll_locked |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1d_1_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1d_1_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1d_1_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1d_1_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | mcgb_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1d_1_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_clk_50 | clk | pcie_xcvr_system_bank_1d_1_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1d_1_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1d_1_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_clk_50 | clk | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1d_1_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1d_1_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1d_1_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1d_1_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1d_2_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1d_2_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1d_2_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_2_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_2_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1d_2_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_2_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_clk_50 | clk | pcie_xcvr_system_bank_1d_2_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_2_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1d_2_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_2_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1d_2_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1d_2_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_2_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1d_2_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1d_2_pll_locked_status | |
pll_locked_output | |||
pll_locked_a | pcie_xcvr_system_bank_1d_2_xcvr_reset_control_s10_0 | ||
pll_locked | |||
pll_locked | pcie_xcvr_system_pll_status | ||
pll_locked_i |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1d_2_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1d_2_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1d_2_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1d_2_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | mcgb_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1d_2_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_clk_50 | clk | pcie_xcvr_system_bank_1d_2_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1d_2_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1d_2_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_clk_50 | clk | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1d_2_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1d_2_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1d_2_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1d_2_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1d_3_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1d_3_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1d_3_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_3_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_3_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1d_3_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_3_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_clk_50 | clk | pcie_xcvr_system_bank_1d_3_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_3_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1d_3_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_3_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1d_3_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1d_3_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_3_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1d_3_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1d_3_pll_locked_status | |
pll_locked_output | |||
pcie_xcvr_system_pll_status | pll_locked_j | ||
pll_locked | |||
pll_locked_a | pcie_xcvr_system_bank_1d_3_xcvr_reset_control_s10_0 | ||
pll_locked |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1d_3_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1d_3_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1d_3_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1d_3_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | mcgb_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1d_3_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_clk_50 | clk | pcie_xcvr_system_bank_1d_3_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1d_3_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1d_3_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_clk_50 | clk | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1d_3_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1d_3_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1d_3_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1d_3_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1d_4_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1d_4_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1d_4_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_4_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_4_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1d_4_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_4_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_clk_50 | clk | pcie_xcvr_system_bank_1d_4_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_4_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1d_4_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_4_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1d_4_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1d_4_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_4_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1d_4_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1d_4_pll_locked_status | |
pll_locked_output | |||
pll_locked_a | pcie_xcvr_system_bank_1d_4_xcvr_reset_control_s10_0 | ||
pll_locked | |||
pll_locked | pcie_xcvr_system_pll_status | ||
pll_locked_k |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1d_4_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1d_4_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1d_4_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1d_4_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | mcgb_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1d_4_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_clk_50 | clk | pcie_xcvr_system_bank_1d_4_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1d_4_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1d_4_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_clk_50 | clk | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1d_4_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1d_4_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1d_4_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1d_4_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1d_5_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1d_5_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1d_5_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_5_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_5_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1d_5_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_5_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_clk_50 | clk | pcie_xcvr_system_bank_1d_5_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_5_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1d_5_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_5_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1d_5_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1d_5_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_5_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1d_5_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1d_5_pll_locked_status | |
pll_locked_output | |||
pcie_xcvr_system_pll_status | pll_locked_l | ||
pll_locked | |||
pll_locked_a | pcie_xcvr_system_bank_1d_5_xcvr_reset_control_s10_0 | ||
pll_locked |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1d_5_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1d_5_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1d_5_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1d_5_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | mcgb_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1d_5_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_clk_50 | clk | pcie_xcvr_system_bank_1d_5_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1d_5_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1d_5_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_clk_50 | clk | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1d_5_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1d_5_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1d_5_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1d_5_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1e_0_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1e_0_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1e_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_0_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1e_0_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_0_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_clk_50 | clk | pcie_xcvr_system_bank_1e_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1e_0_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1e_0_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_0_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1e_0_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1e_0_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_0_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1e_0_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1e_0_pll_locked_status | |
pll_locked_output | |||
pll_locked_a | pcie_xcvr_system_bank_1e_0_xcvr_reset_control_s10_0 | ||
pll_locked | |||
pll_locked | pcie_xcvr_system_pll_status | ||
pll_locked_m |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1e_0_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1e_0_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1e_0_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1e_0_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | mcgb_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1e_0_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_clk_50 | clk | pcie_xcvr_system_bank_1e_0_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1e_0_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1e_0_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_clk_50 | clk | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1e_0_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1e_0_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1e_0_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1e_0_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1e_1_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1e_1_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1e_1_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_1_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_1_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1e_1_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_1_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_clk_50 | clk | pcie_xcvr_system_bank_1e_1_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1e_1_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1e_1_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_1_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1e_1_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1e_1_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_1_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1e_1_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1e_1_pll_locked_status | |
pll_locked_output | |||
pcie_xcvr_system_pll_status | pll_locked_n | ||
pll_locked | |||
pll_locked_a | pcie_xcvr_system_bank_1e_1_xcvr_reset_control_s10_0 | ||
pll_locked |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1e_1_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1e_1_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1e_1_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1e_1_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | mcgb_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1e_1_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_clk_50 | clk | pcie_xcvr_system_bank_1e_1_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1e_1_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1e_1_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_clk_50 | clk | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1e_1_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1e_1_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1e_1_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1e_1_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1e_2_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1e_2_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1e_2_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_2_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_2_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1e_2_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_2_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_clk_50 | clk | pcie_xcvr_system_bank_1e_2_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1e_2_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1e_2_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_2_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1e_2_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1e_2_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_2_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1e_2_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1e_2_pll_locked_status | |
pll_locked_output | |||
pll_locked_a | pcie_xcvr_system_bank_1e_2_xcvr_reset_control_s10_0 | ||
pll_locked | |||
pll_locked | pcie_xcvr_system_pll_status | ||
pll_locked_o |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1e_2_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1e_2_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1e_2_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1e_2_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | mcgb_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1e_2_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_clk_50 | clk | pcie_xcvr_system_bank_1e_2_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1e_2_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1e_2_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_clk_50 | clk | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1e_2_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1e_2_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1e_2_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1e_2_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | pcie_xcvr_system_bank_1e_3_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
clk_reset | pcie_xcvr_system_bank_1e_3_xcvr_reset_control_s10_0 | ||
reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | pcie_xcvr_system_bank_1e_3_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
master_0 | master_reset | ||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_3_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_3_xcvr_reset_control_s10_0 | ||
clock | |||
clk | pcie_xcvr_system_bank_1e_3_pcie_xcvr_test_default_pma_settings_conf_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_3_nativePHY_loopback_cont_0 | ||
clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_clk_50 | clk | pcie_xcvr_system_bank_1e_3_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1e_3_pcie_xcvr_test_default_pma_settings_conf_0 | ||
avalon_slave | |||
m0 | pcie_xcvr_system_bank_1e_3_nativePHY_loopback_cont_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_3_nativePHY_loopback_cont_0 | |
csr | |||
pcie_xcvr_system_bank_1e_3_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
pll_locked | pcie_xcvr_system_bank_1e_3_pll_locked_status | ||
pll_locked_output | |||
rx_is_lockedtoref | pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_3_pcie_xcvr_test_default_pma_settings_conf_0 | |
avalon_slave | |||
pcie_xcvr_system_bank_1e_3_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_nativePHY_loopback_cont_0 | pll_locked | pcie_xcvr_system_bank_1e_3_pll_locked_status | |
pll_locked_output | |||
pcie_xcvr_system_pll_status | pll_locked_p | ||
pll_locked | |||
pll_locked_a | pcie_xcvr_system_bank_1e_3_xcvr_reset_control_s10_0 | ||
pll_locked |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_pcie_xcvr_test_default_pma_settings_conf_0 | avalon_master | pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 | |
reconfig_avmm | |||
pcie_xcvr_system_bank_1e_3_mm_bridge_0 | m0 | ||
reconfig_avmm | |||
pcie_xcvr_system_bank_1e_3_clk_100 | clk | ||
reconfig_clk | |||
clk_reset | |||
reconfig_reset | |||
pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0 | rx_clkout_a_output | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
pcie_xcvr_system_bank_1e_3_xcvr_reset_control_s10_0 | rx_analogreset_stat | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
pcie_xcvr_system_bank_1e_3_nativePHY_loopback_cont_0 | rx_is_lockedtoref | ||
rx_is_lockedtoref | |||
rx_seriallpbken | |||
rx_seriallpbken | |||
atx_pll_1c_refclk | out_clk | ||
rx_cdr_refclk0 | |||
xcvr_atx_pll_1c | mcgb_serial_clk | ||
tx_serial_clk0 | |||
rx_clkout | pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0 | ||
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
rx_clkout2 | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
rx_analogreset | pcie_xcvr_system_bank_1e_3_xcvr_reset_control_s10_0 | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_clk_50 | clk | pcie_xcvr_system_bank_1e_3_xcvr_reset_control_s10_0 | |
clock | |||
pcie_xcvr_system_bank_1e_3_pll_locked_status | pll_locked_a | ||
pll_locked | |||
pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 | rx_analogreset | ||
rx_analogreset | |||
rx_cal_busy | |||
rx_cal_busy | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
pcie_xcvr_system_bank_1e_3_clk_100 | clk_reset | ||
reset | |||
rx_analogreset_stat | pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 | ||
rx_analogreset_stat | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
tx_analogreset | |||
tx_analogreset | |||
tx_cal_busy | |||
tx_cal_busy | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 | rx_clkout | pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0 | |
rx_clkout | |||
tx_clkout | |||
tx_clkout | |||
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in | ||
rx_data_a | |||
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out | ||
tx_data_a | |||
rx_clkout_a_output | pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 | ||
rx_coreclkin | |||
tx_clkout_a_output | |||
tx_coreclkin | |||
rx_parallel_data | |||
rx_parallel_data | |||
tx_parallel_data | |||
tx_parallel_data | |||
rx_clkout_a | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_clk | |||
tx_clkout_a | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_clk_50 | clk | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_checker_0 |
csr_slave | ||
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | data_pattern_checker_pattern_in_fifo_read | |
conduit_pattern_in | ||
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_a | |
conduit_pattern_in_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_generator_0 | |
csr_slave | |||
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | data_pattern_generator_pattern_out_fifo_write | ||
conduit_pattern_out | |||
conduit_pattern_out_clk | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | ||
tx_clkout2_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0 | m0 | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_freq_counter_0 |
csr | ||
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_sample | |
sample_clock |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_clk_50 | clk | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
pcie_xcvr_system_bank_1e_3_mm_bridge_0 | m0 | ||
s0 | |||
m0 | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_freq_counter_0 | ||
csr | |||
m0 | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_checker_0 | ||
csr_slave |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_rx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | fifo_output | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_tx_fifo | |
fifo_output | |||
fifo_input | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
fifo_input |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_generator_0 | conduit_pattern_out_clk | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | |
tx_clkout2_a | |||
pcie_xcvr_system_bank_1e_3_xcvr_native_s10_0 | rx_clkout2 | ||
rx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2 | |||
tx_clkout2_sample | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_freq_counter_0 | ||
sample_clock | |||
rx_clkout2_a | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in_clk | |||
rx_clkout2_b | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
tx_clkout2_b | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | ||
data_pattern_generator_pattern_out_fifo_write_clk |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_rx_fifo | fifo_input | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | rx_clkout2_b | ||
data_pattern_checker_pattern_in_fifo_read_clk | |||
pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0 | rx_clkout_a | ||
data_pattern_checker_pattern_in_clk | |||
data_pattern_checker_pattern_in_fifo_read | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_checker_0 | ||
conduit_pattern_in | |||
fifo_output | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_rx_fifo | ||
fifo_output | |||
data_pattern_checker_pattern_in | pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0 | ||
rx_data_a |
Parameters
|
Software Assignments(none) |
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_tx_fifo | fifo_input | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 | |
fifo_input | |||
pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 | tx_clkout2_b | ||
data_pattern_generator_pattern_out_fifo_write_clk | |||
pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0 | tx_clkout_a | ||
data_pattern_generator_pattern_out_clk | |||
data_pattern_generator_pattern_out_fifo_write | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_data_pattern_generator_0 | ||
conduit_pattern_out | |||
fifo_output | pcie_xcvr_system_bank_1e_3_xcvr_test_system_0_tx_fifo | ||
fifo_output | |||
data_pattern_generator_pattern_out | pcie_xcvr_system_bank_1e_3_xcvr_st_converter_0 | ||
tx_data_a |
Parameters
|
Software Assignments(none) |
generation took 0.02 seconds | rendering took 0.44 seconds |