mSGDMA

2017.11.08.15:12:59 Datasheet
Overview
  clk  mSGDMA
  clk_0 

All Components
   dispatcher_read modular_sgdma_dispatcher 17.1
   dispatcher_write modular_sgdma_dispatcher 17.1
   freq_counter_0 freq_counter 1.0
   mm_bridge_slv altera_avalon_mm_bridge 17.1
   prbs_pattern_checker prbs_pattern_checker 1.1
   prbs_pattern_generator prbs_pattern_generator 1.1
   status_mon_0 status_mon 1.0
   timer_0 altera_avalon_timer 17.1
Memory Map
dma_read_master dma_write_master
 Data_Read_Master  Data_Write_Master
  dispatcher_read
CSR 
Descriptor_Slave 
  dispatcher_write
CSR 
Descriptor_Slave 
  freq_counter_0
csr 
  prbs_pattern_checker
csr 
  prbs_pattern_generator
csr 
  status_mon_0
slv 
  timer_0
s1 

clk

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

clk_0

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

dispatcher_read

modular_sgdma_dispatcher v17.1
mm_bridge_slv m0   dispatcher_read
  CSR
m0  
  Descriptor_Slave
dma_read_master Response_Source  
  Read_Response_Sink
clk clk  
  clock
clk_reset  
  clock_reset
Read_Command_Source   dma_read_master
  Command_Sink


Parameters

generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
DATA_FIFO_DEPTH 32
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
MAX_BURST_COUNT 2
MAX_BYTE 1024
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_FIFO_DEPTH 2048
RESPONSE_PORT 0
STRIDE_ENABLE 0
TRANSFER_TYPE Aligned Accesses

dispatcher_write

modular_sgdma_dispatcher v17.1
mm_bridge_slv m0   dispatcher_write
  CSR
m0  
  Descriptor_Slave
dma_write_master Response_Source  
  Write_Response_Sink
clk clk  
  clock
clk_reset  
  clock_reset
Write_Command_Source   dma_write_master
  Command_Sink


Parameters

generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
DATA_FIFO_DEPTH 32
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
MAX_BURST_COUNT 2
MAX_BYTE 1024
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_FIFO_DEPTH 2048
RESPONSE_PORT 2
STRIDE_ENABLE 0
TRANSFER_TYPE Aligned Accesses

dma_read_master

dma_read_master v17.1
dispatcher_read Read_Command_Source   dma_read_master
  Command_Sink
clk clk  
  Clock
clk_reset  
  Clock_reset
Data_Source   prbs_pattern_checker
  st_pattern_input
Response_Source   dispatcher_read
  Read_Response_Sink


Parameters

generateLegacySim false
  

Software Assignments

(none)

dma_write_master

dma_write_master v17.1
dispatcher_write Write_Command_Source   dma_write_master
  Command_Sink
timing_adapter out  
  Data_Sink
clk clk  
  Clock
clk_reset  
  Clock_reset
Response_Source   dispatcher_write
  Write_Response_Sink


Parameters

generateLegacySim false
  

Software Assignments

(none)

freq_counter_0

freq_counter v1.0
mm_bridge_slv m0   freq_counter_0
  csr
clk_0 clk  
  clock
clk_reset  
  reset
clk clk  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_slv

altera_avalon_mm_bridge v17.1
clk clk   mm_bridge_slv
  clk
clk_reset  
  reset
m0   dispatcher_read
  CSR
m0  
  Descriptor_Slave
m0   dispatcher_write
  CSR
m0  
  Descriptor_Slave
m0   freq_counter_0
  csr
m0   prbs_pattern_checker
  csr
m0   prbs_pattern_generator
  csr
m0   timer_0
  s1
m0   status_mon_0
  slv


Parameters

generateLegacySim false
  

Software Assignments

(none)

prbs_pattern_checker

prbs_pattern_checker v1.1
mm_bridge_slv m0   prbs_pattern_checker
  csr
dma_read_master Data_Source  
  st_pattern_input
clk clk  
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

prbs_pattern_generator

prbs_pattern_generator v1.1
mm_bridge_slv m0   prbs_pattern_generator
  csr
clk clk  
  clock
clk_reset  
  reset
st_pattern_output   timing_adapter
  in


Parameters

generateLegacySim false
  

Software Assignments

(none)

status_mon_0

status_mon v1.0
mm_bridge_slv m0   status_mon_0
  slv
clk clk  
  clock
clk_reset  
  reset_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

timer_0

altera_avalon_timer v17.1
mm_bridge_slv m0   timer_0
  s1
clk_0 clk  
  clk
clk clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0

timing_adapter

timing_adapter v17.1
prbs_pattern_generator st_pattern_output   timing_adapter
  in
clk clk  
  clk
clk_reset  
  reset
out   dma_write_master
  Data_Sink


Parameters

generateLegacySim false
  

Software Assignments

(none)
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