q_sys

2017.05.09.23:38:31 Datasheet
Overview
  clk_0  q_sys

All Components
   System_max_ID_0 System_max_ID 1.0
   opencores_i2c_0 opencores_i2c 9.1
   pio_ch_data altera_avalon_pio 17.0
   pio_ch_no altera_avalon_pio 17.0
   sysid_qsys_0 altera_avalon_sysid_qsys 17.0
Memory Map
alt_jtagavalon_wrapper_0
 avm_jtag
  System_max_ID_0
slv  0x00000020
  opencores_i2c_0
avalon_slave_0  0x00000000
  pio_ch_data
s1  0x00000080
  pio_ch_no
s1  0x00000060
  sysid_qsys_0
control_slave  0x00000040

System_max_ID_0

System_max_ID v1.0
alt_jtagavalon_wrapper_0 avm_jtag   System_max_ID_0
  slv
clk_0 clk  
  clock
clk_reset  
  reset


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_jtagavalon_wrapper_0

alt_jtagavalon_wrapper v17.0
clk_0 clk   alt_jtagavalon_wrapper_0
  global_signals_clock
clk_reset  
  global_signals_clock_reset
avm_jtag   opencores_i2c_0
  avalon_slave_0
avm_jtag   sysid_qsys_0
  control_slave
avm_jtag   pio_ch_no
  s1
avm_jtag   pio_ch_data
  s1
avm_jtag   System_max_ID_0
  slv


Parameters

ADDR_WIDTH 16
DATA_WIDTH 32
MODE_WIDTH 3
INSTANCE_ID 0
SLD_AUTO_INSTANCE_INDEX YES
ADDRESS_MAP <address-map><slave name='opencores_i2c_0.avalon_slave_0' start='0x0' end='0x20' type='opencores_i2c.avalon_slave_0' /><slave name='System_max_ID_0.slv' start='0x20' end='0x40' type='System_max_ID.slv' /><slave name='sysid_qsys_0.control_slave' start='0x40' end='0x48' type='altera_avalon_sysid_qsys.control_slave' /><slave name='pio_ch_no.s1' start='0x60' end='0x70' type='altera_avalon_pio.s1' /><slave name='pio_ch_data.s1' start='0x80' end='0x90' type='altera_avalon_pio.s1' /></address-map>
ROM_CONTENTS 00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000111011100000000000000000000000001100101000000000000000000000000011111000000000000000000000000001101111000000000000000000000000001001000000000000000000000000000000010010000000000000000000000001001001000000000000000000000000000100000000000000000000000000000010011000000000000000000000000001100110000000000000000000000000011101100000000000000000000000000010111000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000001011000000000000000000000000000110110000000000000000000000000011011100000000000000000000000000000100010000000000000000000000000000000100000000000000000000000011100010000000000000000000000000011010010000000000000000000000000110001000000000000000000000000001100000000000000000000000000000111001100000000000000000000000000110001000000000000000000000000001100101000000000000000000000000011001010000000000000000000000000110001100000000000000000000000010000101
ROM_SIZE 31
OWNER_ID 0
USAGE_ID 256
USER_ID1 0
USER_ID2 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

clk_0

clock_source v17.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

opencores_i2c_0

opencores_i2c v9.1
alt_jtagavalon_wrapper_0 avm_jtag   opencores_i2c_0
  avalon_slave_0
clk_0 clk  
  clock
clk_reset  
  clock_reset


Parameters

AUTO_CLOCK_CLOCK_RATE 50000000
AUTO_SLOW_CLOCK_CLOCK_RATE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

pio_ch_data

altera_avalon_pio v17.0
alt_jtagavalon_wrapper_0 avm_jtag   pio_ch_data
  s1
clk_0 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 32
clockRate 50000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 32
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_ch_no

altera_avalon_pio v17.0
alt_jtagavalon_wrapper_0 avm_jtag   pio_ch_no
  s1
clk_0 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 3
clockRate 50000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 3
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

sysid_qsys_0

altera_avalon_sysid_qsys v17.0
alt_jtagavalon_wrapper_0 avm_jtag   sysid_qsys_0
  control_slave
clk_0 clk  
  clk
clk_reset  
  reset


Parameters

id 279093
timestamp 1494398310
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ID 279093
TIMESTAMP 1494398310
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