ed_synth_clk_0

2017.11.16.19:34:39 Datasheet
Overview
  clk_0  ed_synth_clk_0

Memory Map

clk_0

clock_source v17.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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