ed_synth_clk_0
2019.12.04.15:07:11
Datasheet
Overview
ed_synth_clk_0
ed_synth_clk_0
Memory Map
ed_synth_clk_0
clock_source v19.3
Parameters
clockFrequency
50000000
clockFrequencyKnown
true
resetSynchronousEdges
NONE
deviceFamily
UNKNOWN
generateLegacySim
false
Software Assignments
(none)
generation took 0.00 seconds
rendering took 0.00 seconds