q_sys

2019.12.04.10:35:38 Datasheet
Overview
  clk_100  q_sys
  clk_50 
  qsfpdd_xcvr_test_0_clk_100 
  qsfpdd_xcvr_test_0_clk_50 
  qsfpdd_xcvr_test_0_xcvr_test_system_0_clk_50 
  qsfpdd_xcvr_test_1_clk_100 
  qsfpdd_xcvr_test_1_clk_50 
  qsfpdd_xcvr_test_1_xcvr_test_system_0_clk_50 
  qsfpdd_xcvr_test_2_clk_100 
  qsfpdd_xcvr_test_2_clk_50 
  qsfpdd_xcvr_test_2_xcvr_test_system_0_clk_50 
  qsfpdd_xcvr_test_3_clk_100 
  qsfpdd_xcvr_test_3_clk_50 
  qsfpdd_xcvr_test_3_xcvr_test_system_0_clk_50 
  qsfpdd_xcvr_test_4_clk_100 
  qsfpdd_xcvr_test_4_clk_50 
  qsfpdd_xcvr_test_4_xcvr_test_system_0_clk_50 
  qsfpdd_xcvr_test_5_clk_100 
  qsfpdd_xcvr_test_5_clk_50 
  qsfpdd_xcvr_test_5_xcvr_test_system_0_clk_50 
  qsfpdd_xcvr_test_6_clk_100 
  qsfpdd_xcvr_test_6_clk_50 
  qsfpdd_xcvr_test_6_xcvr_test_system_0_clk_50 
  qsfpdd_xcvr_test_7_clk_100 
  qsfpdd_xcvr_test_7_clk_50 
  qsfpdd_xcvr_test_7_xcvr_test_system_0_clk_50 

All Components
   i2c_0 altera_avalon_i2c 19.1
   i2c_1 altera_avalon_i2c 19.1
   i2c_2 altera_avalon_i2c 19.1
   module_debug_inputs altera_avalon_pio 19.1
   module_debug_outputs altera_avalon_pio 19.1
   product_info_0 product_info 1.0
   temp_info_0 temp_info 1.0
   qsfpdd_xcvr_test_0 qsfpdd_xcvr_test 1.0
   qsfpdd_xcvr_test_0_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_0_xcvr_conduit_ctrl_0 xcvr_conduit_ctrl 1.0
   qsfpdd_xcvr_test_0_xcvr_native_s10_etile_0 altera_xcvr_native_s10_etile 21.0.0
   qsfpdd_xcvr_test_0_xcvr_test_system_0 xcvr_test_system 1.0
   qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 19.1
   qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 19.1
   qsfpdd_xcvr_test_0_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   qsfpdd_xcvr_test_0_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_1 qsfpdd_xcvr_test 1.0
   qsfpdd_xcvr_test_1_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_1_xcvr_conduit_ctrl_0 xcvr_conduit_ctrl 1.0
   qsfpdd_xcvr_test_1_xcvr_native_s10_etile_0 altera_xcvr_native_s10_etile 21.0.0
   qsfpdd_xcvr_test_1_xcvr_test_system_0 xcvr_test_system 1.0
   qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 19.1
   qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 19.1
   qsfpdd_xcvr_test_1_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   qsfpdd_xcvr_test_1_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_2 qsfpdd_xcvr_test 1.0
   qsfpdd_xcvr_test_2_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_2_xcvr_conduit_ctrl_0 xcvr_conduit_ctrl 1.0
   qsfpdd_xcvr_test_2_xcvr_native_s10_etile_0 altera_xcvr_native_s10_etile 21.0.0
   qsfpdd_xcvr_test_2_xcvr_test_system_0 xcvr_test_system 1.0
   qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 19.1
   qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 19.1
   qsfpdd_xcvr_test_2_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   qsfpdd_xcvr_test_2_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_3 qsfpdd_xcvr_test 1.0
   qsfpdd_xcvr_test_3_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_3_xcvr_conduit_ctrl_0 xcvr_conduit_ctrl 1.0
   qsfpdd_xcvr_test_3_xcvr_native_s10_etile_0 altera_xcvr_native_s10_etile 21.0.0
   qsfpdd_xcvr_test_3_xcvr_test_system_0 xcvr_test_system 1.0
   qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 19.1
   qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 19.1
   qsfpdd_xcvr_test_3_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   qsfpdd_xcvr_test_3_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_4 qsfpdd_xcvr_test 1.0
   qsfpdd_xcvr_test_4_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_4_xcvr_conduit_ctrl_0 xcvr_conduit_ctrl 1.0
   qsfpdd_xcvr_test_4_xcvr_native_s10_etile_0 altera_xcvr_native_s10_etile 21.0.0
   qsfpdd_xcvr_test_4_xcvr_test_system_0 xcvr_test_system 1.0
   qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 19.1
   qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 19.1
   qsfpdd_xcvr_test_4_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   qsfpdd_xcvr_test_4_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_5 qsfpdd_xcvr_test 1.0
   qsfpdd_xcvr_test_5_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_5_xcvr_conduit_ctrl_0 xcvr_conduit_ctrl 1.0
   qsfpdd_xcvr_test_5_xcvr_native_s10_etile_0 altera_xcvr_native_s10_etile 21.0.0
   qsfpdd_xcvr_test_5_xcvr_test_system_0 xcvr_test_system 1.0
   qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 19.1
   qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 19.1
   qsfpdd_xcvr_test_5_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   qsfpdd_xcvr_test_5_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_6 qsfpdd_xcvr_test 1.0
   qsfpdd_xcvr_test_6_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_6_xcvr_conduit_ctrl_0 xcvr_conduit_ctrl 1.0
   qsfpdd_xcvr_test_6_xcvr_native_s10_etile_0 altera_xcvr_native_s10_etile 21.0.0
   qsfpdd_xcvr_test_6_xcvr_test_system_0 xcvr_test_system 1.0
   qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 19.1
   qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 19.1
   qsfpdd_xcvr_test_6_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   qsfpdd_xcvr_test_6_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_7 qsfpdd_xcvr_test 1.0
   qsfpdd_xcvr_test_7_mm_bridge_0 altera_avalon_mm_bridge 19.1
   qsfpdd_xcvr_test_7_xcvr_conduit_ctrl_0 xcvr_conduit_ctrl 1.0
   qsfpdd_xcvr_test_7_xcvr_native_s10_etile_0 altera_xcvr_native_s10_etile 21.0.0
   qsfpdd_xcvr_test_7_xcvr_test_system_0 xcvr_test_system 1.0
   qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 19.1
   qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 19.1
   qsfpdd_xcvr_test_7_xcvr_test_system_0_freq_counter_0 freq_counter 1.0
   qsfpdd_xcvr_test_7_xcvr_test_system_0_mm_bridge_0 altera_avalon_mm_bridge 19.1
Memory Map
master_0
 master
  i2c_0
csr  0x000000c0
  i2c_1
csr  0x00000100
  i2c_2
csr  0x00000140
  module_debug_inputs
s1  0x00000010
  module_debug_outputs
s1  0x00000080
  product_info_0
avalon_slave_0  0x00000000
  temp_info_0
avalon_slave_0  0x00000040
  qsfpdd_xcvr_test_0
mm_bridge_0_s0 
  qsfpdd_xcvr_test_0_xcvr_conduit_ctrl_0
csr  0x00302000
  qsfpdd_xcvr_test_0_xcvr_native_s10_etile_0
reconfig_avmm  0x00200000
  qsfpdd_xcvr_test_0_xcvr_test_system_0
mm_bridge_0_s0 
  qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00301020
  qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00301000
  qsfpdd_xcvr_test_0_xcvr_test_system_0_freq_counter_0
csr  0x00301200
  qsfpdd_xcvr_test_1
mm_bridge_0_s0 
  qsfpdd_xcvr_test_1_xcvr_conduit_ctrl_0
csr  0x00502000
  qsfpdd_xcvr_test_1_xcvr_native_s10_etile_0
reconfig_avmm  0x00400000
  qsfpdd_xcvr_test_1_xcvr_test_system_0
mm_bridge_0_s0 
  qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00501020
  qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00501000
  qsfpdd_xcvr_test_1_xcvr_test_system_0_freq_counter_0
csr  0x00501200
  qsfpdd_xcvr_test_2
mm_bridge_0_s0 
  qsfpdd_xcvr_test_2_xcvr_conduit_ctrl_0
csr  0x00702000
  qsfpdd_xcvr_test_2_xcvr_native_s10_etile_0
reconfig_avmm  0x00600000
  qsfpdd_xcvr_test_2_xcvr_test_system_0
mm_bridge_0_s0 
  qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00701020
  qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00701000
  qsfpdd_xcvr_test_2_xcvr_test_system_0_freq_counter_0
csr  0x00701200
  qsfpdd_xcvr_test_3
mm_bridge_0_s0 
  qsfpdd_xcvr_test_3_xcvr_conduit_ctrl_0
csr  0x00902000
  qsfpdd_xcvr_test_3_xcvr_native_s10_etile_0
reconfig_avmm  0x00800000
  qsfpdd_xcvr_test_3_xcvr_test_system_0
mm_bridge_0_s0 
  qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00901020
  qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00901000
  qsfpdd_xcvr_test_3_xcvr_test_system_0_freq_counter_0
csr  0x00901200
  qsfpdd_xcvr_test_4
mm_bridge_0_s0 
  qsfpdd_xcvr_test_4_xcvr_conduit_ctrl_0
csr  0x00b02000
  qsfpdd_xcvr_test_4_xcvr_native_s10_etile_0
reconfig_avmm  0x00a00000
  qsfpdd_xcvr_test_4_xcvr_test_system_0
mm_bridge_0_s0 
  qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00b01020
  qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00b01000
  qsfpdd_xcvr_test_4_xcvr_test_system_0_freq_counter_0
csr  0x00b01200
  qsfpdd_xcvr_test_5
mm_bridge_0_s0 
  qsfpdd_xcvr_test_5_xcvr_conduit_ctrl_0
csr  0x00d02000
  qsfpdd_xcvr_test_5_xcvr_native_s10_etile_0
reconfig_avmm  0x00c00000
  qsfpdd_xcvr_test_5_xcvr_test_system_0
mm_bridge_0_s0 
  qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00d01020
  qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00d01000
  qsfpdd_xcvr_test_5_xcvr_test_system_0_freq_counter_0
csr  0x00d01200
  qsfpdd_xcvr_test_6
mm_bridge_0_s0 
  qsfpdd_xcvr_test_6_xcvr_conduit_ctrl_0
csr  0x00f02000
  qsfpdd_xcvr_test_6_xcvr_native_s10_etile_0
reconfig_avmm  0x00e00000
  qsfpdd_xcvr_test_6_xcvr_test_system_0
mm_bridge_0_s0 
  qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x00f01020
  qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x00f01000
  qsfpdd_xcvr_test_6_xcvr_test_system_0_freq_counter_0
csr  0x00f01200
  qsfpdd_xcvr_test_7
mm_bridge_0_s0 
  qsfpdd_xcvr_test_7_xcvr_conduit_ctrl_0
csr  0x01102000
  qsfpdd_xcvr_test_7_xcvr_native_s10_etile_0
reconfig_avmm  0x01000000
  qsfpdd_xcvr_test_7_xcvr_test_system_0
mm_bridge_0_s0 
  qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_checker_0
csr_slave  0x01101020
  qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_generator_0
csr_slave  0x01101000
  qsfpdd_xcvr_test_7_xcvr_test_system_0_freq_counter_0
csr  0x01101200

clk_100

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

clk_50

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

i2c_0

altera_avalon_i2c v19.1
master_0 master   i2c_0
  csr
clk_50 clk  
  clock
clk_reset  
  reset_sink


Parameters

generateLegacySim false
  

Software Assignments

FIFO_DEPTH 64
FREQ 50000000
USE_AV_ST 0

i2c_1

altera_avalon_i2c v19.1
master_0 master   i2c_1
  csr
clk_50 clk  
  clock
clk_reset  
  reset_sink


Parameters

generateLegacySim false
  

Software Assignments

FIFO_DEPTH 64
FREQ 50000000
USE_AV_ST 0

i2c_2

altera_avalon_i2c v19.1
master_0 master   i2c_2
  csr
clk_50 clk  
  clock
clk_reset  
  reset_sink


Parameters

generateLegacySim false
  

Software Assignments

FIFO_DEPTH 64
FREQ 50000000
USE_AV_ST 0

master_0

altera_jtag_avalon_master v19.1
clk_50 clk   master_0
  clk
clk_reset  
  clk_reset
master   product_info_0
  avalon_slave_0
master   temp_info_0
  avalon_slave_0
master   i2c_2
  csr
master   i2c_1
  csr
master   i2c_0
  csr
master   qsfpdd_xcvr_test_1_mm_bridge_0
  s0
master   qsfpdd_xcvr_test_0_mm_bridge_0
  s0
master   qsfpdd_xcvr_test_2_mm_bridge_0
  s0
master   qsfpdd_xcvr_test_3_mm_bridge_0
  s0
master   qsfpdd_xcvr_test_4_mm_bridge_0
  s0
master   qsfpdd_xcvr_test_5_mm_bridge_0
  s0
master   qsfpdd_xcvr_test_6_mm_bridge_0
  s0
master   qsfpdd_xcvr_test_7_mm_bridge_0
  s0
master   module_debug_outputs
  s1
master   module_debug_inputs
  s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

module_debug_inputs

altera_avalon_pio v19.1
master_0 master   module_debug_inputs
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 8
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

module_debug_outputs

altera_avalon_pio v19.1
master_0 master   module_debug_outputs
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 8
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 1

product_info_0

product_info v1.0
master_0 master   product_info_0
  avalon_slave_0
clk_50 clk  
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

q_sys_iopll_9a

altera_iopll v19.3.0
qsfpdd_xcvr_test_0_xcvr_native_s10_etile_0 tx_clkout2   q_sys_iopll_9a
  refclk
clk_50 clk_reset  
  reset
outclk0   qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
outclk0  
  tx_clkout2
outclk0   qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
outclk0  
  tx_clkout2
outclk0   qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
outclk0  
  tx_clkout2
outclk0   qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
outclk0  
  tx_clkout2
outclk0   qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
outclk0  
  tx_clkout2
outclk0   qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
outclk0  
  tx_clkout2
outclk0   qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
outclk0  
  tx_clkout2
outclk0   qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  rx_clkout2
outclk0  
  tx_clkout2


Parameters

generateLegacySim false
  

Software Assignments

(none)

refclk_etile_9a

altera_clock_bridge v19.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

temp_info_0

temp_info v1.0
master_0 master   temp_info_0
  avalon_slave_0
clk_50 clk  
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0

qsfpdd_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_clk_100

clock_source vnull
clk_100 clk   qsfpdd_xcvr_test_0_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_0_xcvr_native_s10_etile_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_clk_50

clock_source vnull
clk_50 clk   qsfpdd_xcvr_test_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_0_xcvr_conduit_ctrl_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_0_clk_50 clk   qsfpdd_xcvr_test_0_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   qsfpdd_xcvr_test_0_xcvr_conduit_ctrl_0
  csr
m0   qsfpdd_xcvr_test_0_xcvr_test_system_0_mm_bridge_0
  s0
m0   qsfpdd_xcvr_test_0_xcvr_native_s10_etile_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_conduit_ctrl_0

xcvr_conduit_ctrl v1.0
qsfpdd_xcvr_test_0_mm_bridge_0 m0   qsfpdd_xcvr_test_0_xcvr_conduit_ctrl_0
  csr
qsfpdd_xcvr_test_0_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_0_xcvr_native_s10_etile_0 rx_pma_ready  
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_native_s10_etile_0

altera_xcvr_native_s10_etile v21.0.0
qsfpdd_xcvr_test_0_mm_bridge_0 m0   qsfpdd_xcvr_test_0_xcvr_native_s10_etile_0
  reconfig_avmm
qsfpdd_xcvr_test_0_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
qsfpdd_xcvr_test_0_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
refclk_etile_9a out_clk  
  pll_refclk0
rx_clkout   qsfpdd_xcvr_test_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
rx_pma_ready   qsfpdd_xcvr_test_0_xcvr_conduit_ctrl_0
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready
tx_clkout2   q_sys_iopll_9a
  refclk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_st_converter_0

xcvr_st_converter v1.0
qsfpdd_xcvr_test_0_xcvr_native_s10_etile_0 rx_clkout   qsfpdd_xcvr_test_0_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
rx_clkout_a_output   qsfpdd_xcvr_test_0_xcvr_native_s10_etile_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_test_system_0_clk_50

clock_source vnull
qsfpdd_xcvr_test_0_clk_50 clk   qsfpdd_xcvr_test_0_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_0_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v19.1
qsfpdd_xcvr_test_0_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
qsfpdd_xcvr_test_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v19.1
qsfpdd_xcvr_test_0_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
qsfpdd_xcvr_test_0_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
qsfpdd_xcvr_test_0_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_0_xcvr_test_system_0_freq_counter_0
  csr
qsfpdd_xcvr_test_0_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_0_xcvr_test_system_0_clk_50 clk   qsfpdd_xcvr_test_0_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
qsfpdd_xcvr_test_0_mm_bridge_0 m0  
  s0
m0   qsfpdd_xcvr_test_0_xcvr_test_system_0_freq_counter_0
  csr
m0   qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_test_system_0_rx_fifo

fifo v19.1
qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_0_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_test_system_0_tx_fifo

fifo v19.1
qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_0_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
q_sys_iopll_9a outclk0  
  rx_clkout2
outclk0  
  tx_clkout2
tx_clkout2_sample   qsfpdd_xcvr_test_0_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
qsfpdd_xcvr_test_0_xcvr_test_system_0_rx_fifo fifo_input   qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
qsfpdd_xcvr_test_0_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   qsfpdd_xcvr_test_0_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   qsfpdd_xcvr_test_0_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
qsfpdd_xcvr_test_0_xcvr_test_system_0_tx_fifo fifo_input   qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_0_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
qsfpdd_xcvr_test_0_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out
data_pattern_generator_pattern_out_fifo_write   qsfpdd_xcvr_test_0_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   qsfpdd_xcvr_test_0_xcvr_test_system_0_tx_fifo
  fifo_output


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1

qsfpdd_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_clk_100

clock_source vnull
clk_100 clk   qsfpdd_xcvr_test_1_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_1_xcvr_native_s10_etile_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_clk_50

clock_source vnull
clk_50 clk   qsfpdd_xcvr_test_1_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_1_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_1_xcvr_conduit_ctrl_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_1_clk_50 clk   qsfpdd_xcvr_test_1_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   qsfpdd_xcvr_test_1_xcvr_conduit_ctrl_0
  csr
m0   qsfpdd_xcvr_test_1_xcvr_test_system_0_mm_bridge_0
  s0
m0   qsfpdd_xcvr_test_1_xcvr_native_s10_etile_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_conduit_ctrl_0

xcvr_conduit_ctrl v1.0
qsfpdd_xcvr_test_1_mm_bridge_0 m0   qsfpdd_xcvr_test_1_xcvr_conduit_ctrl_0
  csr
qsfpdd_xcvr_test_1_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_1_xcvr_native_s10_etile_0 rx_pma_ready  
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_native_s10_etile_0

altera_xcvr_native_s10_etile v21.0.0
qsfpdd_xcvr_test_1_mm_bridge_0 m0   qsfpdd_xcvr_test_1_xcvr_native_s10_etile_0
  reconfig_avmm
qsfpdd_xcvr_test_1_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
qsfpdd_xcvr_test_1_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
refclk_etile_9a out_clk  
  pll_refclk0
rx_clkout   qsfpdd_xcvr_test_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
rx_pma_ready   qsfpdd_xcvr_test_1_xcvr_conduit_ctrl_0
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_st_converter_0

xcvr_st_converter v1.0
qsfpdd_xcvr_test_1_xcvr_native_s10_etile_0 rx_clkout   qsfpdd_xcvr_test_1_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
rx_clkout_a_output   qsfpdd_xcvr_test_1_xcvr_native_s10_etile_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_test_system_0_clk_50

clock_source vnull
qsfpdd_xcvr_test_1_clk_50 clk   qsfpdd_xcvr_test_1_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_1_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v19.1
qsfpdd_xcvr_test_1_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
qsfpdd_xcvr_test_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v19.1
qsfpdd_xcvr_test_1_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
qsfpdd_xcvr_test_1_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
qsfpdd_xcvr_test_1_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_1_xcvr_test_system_0_freq_counter_0
  csr
qsfpdd_xcvr_test_1_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_1_xcvr_test_system_0_clk_50 clk   qsfpdd_xcvr_test_1_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
qsfpdd_xcvr_test_1_mm_bridge_0 m0  
  s0
m0   qsfpdd_xcvr_test_1_xcvr_test_system_0_freq_counter_0
  csr
m0   qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_test_system_0_rx_fifo

fifo v19.1
qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_1_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_test_system_0_tx_fifo

fifo v19.1
qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_1_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
q_sys_iopll_9a outclk0  
  rx_clkout2
outclk0  
  tx_clkout2
tx_clkout2_sample   qsfpdd_xcvr_test_1_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
qsfpdd_xcvr_test_1_xcvr_test_system_0_rx_fifo fifo_input   qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
qsfpdd_xcvr_test_1_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   qsfpdd_xcvr_test_1_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   qsfpdd_xcvr_test_1_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
qsfpdd_xcvr_test_1_xcvr_test_system_0_tx_fifo fifo_input   qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_1_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
qsfpdd_xcvr_test_1_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out
data_pattern_generator_pattern_out_fifo_write   qsfpdd_xcvr_test_1_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   qsfpdd_xcvr_test_1_xcvr_test_system_0_tx_fifo
  fifo_output


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2

qsfpdd_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_clk_100

clock_source vnull
clk_100 clk   qsfpdd_xcvr_test_2_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_2_xcvr_native_s10_etile_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_clk_50

clock_source vnull
clk_50 clk   qsfpdd_xcvr_test_2_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_2_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_2_xcvr_conduit_ctrl_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_2_clk_50 clk   qsfpdd_xcvr_test_2_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   qsfpdd_xcvr_test_2_xcvr_conduit_ctrl_0
  csr
m0   qsfpdd_xcvr_test_2_xcvr_test_system_0_mm_bridge_0
  s0
m0   qsfpdd_xcvr_test_2_xcvr_native_s10_etile_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_conduit_ctrl_0

xcvr_conduit_ctrl v1.0
qsfpdd_xcvr_test_2_mm_bridge_0 m0   qsfpdd_xcvr_test_2_xcvr_conduit_ctrl_0
  csr
qsfpdd_xcvr_test_2_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_2_xcvr_native_s10_etile_0 rx_pma_ready  
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_native_s10_etile_0

altera_xcvr_native_s10_etile v21.0.0
qsfpdd_xcvr_test_2_mm_bridge_0 m0   qsfpdd_xcvr_test_2_xcvr_native_s10_etile_0
  reconfig_avmm
qsfpdd_xcvr_test_2_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
qsfpdd_xcvr_test_2_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
refclk_etile_9a out_clk  
  pll_refclk0
rx_clkout   qsfpdd_xcvr_test_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
rx_pma_ready   qsfpdd_xcvr_test_2_xcvr_conduit_ctrl_0
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_st_converter_0

xcvr_st_converter v1.0
qsfpdd_xcvr_test_2_xcvr_native_s10_etile_0 rx_clkout   qsfpdd_xcvr_test_2_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
rx_clkout_a_output   qsfpdd_xcvr_test_2_xcvr_native_s10_etile_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_test_system_0_clk_50

clock_source vnull
qsfpdd_xcvr_test_2_clk_50 clk   qsfpdd_xcvr_test_2_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_2_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v19.1
qsfpdd_xcvr_test_2_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
qsfpdd_xcvr_test_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v19.1
qsfpdd_xcvr_test_2_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
qsfpdd_xcvr_test_2_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
qsfpdd_xcvr_test_2_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_2_xcvr_test_system_0_freq_counter_0
  csr
qsfpdd_xcvr_test_2_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_2_xcvr_test_system_0_clk_50 clk   qsfpdd_xcvr_test_2_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
qsfpdd_xcvr_test_2_mm_bridge_0 m0  
  s0
m0   qsfpdd_xcvr_test_2_xcvr_test_system_0_freq_counter_0
  csr
m0   qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_test_system_0_rx_fifo

fifo v19.1
qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_2_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_test_system_0_tx_fifo

fifo v19.1
qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_2_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
q_sys_iopll_9a outclk0  
  rx_clkout2
outclk0  
  tx_clkout2
tx_clkout2_sample   qsfpdd_xcvr_test_2_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
qsfpdd_xcvr_test_2_xcvr_test_system_0_rx_fifo fifo_input   qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
qsfpdd_xcvr_test_2_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   qsfpdd_xcvr_test_2_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   qsfpdd_xcvr_test_2_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
qsfpdd_xcvr_test_2_xcvr_test_system_0_tx_fifo fifo_input   qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_2_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
qsfpdd_xcvr_test_2_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out
data_pattern_generator_pattern_out_fifo_write   qsfpdd_xcvr_test_2_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   qsfpdd_xcvr_test_2_xcvr_test_system_0_tx_fifo
  fifo_output


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3

qsfpdd_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_clk_100

clock_source vnull
clk_100 clk   qsfpdd_xcvr_test_3_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_3_xcvr_native_s10_etile_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_clk_50

clock_source vnull
clk_50 clk   qsfpdd_xcvr_test_3_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_3_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_3_xcvr_conduit_ctrl_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_3_clk_50 clk   qsfpdd_xcvr_test_3_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   qsfpdd_xcvr_test_3_xcvr_conduit_ctrl_0
  csr
m0   qsfpdd_xcvr_test_3_xcvr_test_system_0_mm_bridge_0
  s0
m0   qsfpdd_xcvr_test_3_xcvr_native_s10_etile_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_conduit_ctrl_0

xcvr_conduit_ctrl v1.0
qsfpdd_xcvr_test_3_mm_bridge_0 m0   qsfpdd_xcvr_test_3_xcvr_conduit_ctrl_0
  csr
qsfpdd_xcvr_test_3_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_3_xcvr_native_s10_etile_0 rx_pma_ready  
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_native_s10_etile_0

altera_xcvr_native_s10_etile v21.0.0
qsfpdd_xcvr_test_3_mm_bridge_0 m0   qsfpdd_xcvr_test_3_xcvr_native_s10_etile_0
  reconfig_avmm
qsfpdd_xcvr_test_3_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
qsfpdd_xcvr_test_3_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
refclk_etile_9a out_clk  
  pll_refclk0
rx_clkout   qsfpdd_xcvr_test_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
rx_pma_ready   qsfpdd_xcvr_test_3_xcvr_conduit_ctrl_0
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_st_converter_0

xcvr_st_converter v1.0
qsfpdd_xcvr_test_3_xcvr_native_s10_etile_0 rx_clkout   qsfpdd_xcvr_test_3_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
rx_clkout_a_output   qsfpdd_xcvr_test_3_xcvr_native_s10_etile_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_test_system_0_clk_50

clock_source vnull
qsfpdd_xcvr_test_3_clk_50 clk   qsfpdd_xcvr_test_3_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_3_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v19.1
qsfpdd_xcvr_test_3_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
qsfpdd_xcvr_test_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v19.1
qsfpdd_xcvr_test_3_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
qsfpdd_xcvr_test_3_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
qsfpdd_xcvr_test_3_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_3_xcvr_test_system_0_freq_counter_0
  csr
qsfpdd_xcvr_test_3_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_3_xcvr_test_system_0_clk_50 clk   qsfpdd_xcvr_test_3_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
qsfpdd_xcvr_test_3_mm_bridge_0 m0  
  s0
m0   qsfpdd_xcvr_test_3_xcvr_test_system_0_freq_counter_0
  csr
m0   qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_test_system_0_rx_fifo

fifo v19.1
qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_3_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_test_system_0_tx_fifo

fifo v19.1
qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_3_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
q_sys_iopll_9a outclk0  
  rx_clkout2
outclk0  
  tx_clkout2
tx_clkout2_sample   qsfpdd_xcvr_test_3_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
qsfpdd_xcvr_test_3_xcvr_test_system_0_rx_fifo fifo_input   qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
qsfpdd_xcvr_test_3_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   qsfpdd_xcvr_test_3_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   qsfpdd_xcvr_test_3_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
qsfpdd_xcvr_test_3_xcvr_test_system_0_tx_fifo fifo_input   qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_3_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
qsfpdd_xcvr_test_3_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out
data_pattern_generator_pattern_out_fifo_write   qsfpdd_xcvr_test_3_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   qsfpdd_xcvr_test_3_xcvr_test_system_0_tx_fifo
  fifo_output


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4

qsfpdd_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_clk_100

clock_source vnull
clk_100 clk   qsfpdd_xcvr_test_4_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_4_xcvr_native_s10_etile_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_clk_50

clock_source vnull
clk_50 clk   qsfpdd_xcvr_test_4_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_4_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_4_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_4_xcvr_conduit_ctrl_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_4_clk_50 clk   qsfpdd_xcvr_test_4_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   qsfpdd_xcvr_test_4_xcvr_conduit_ctrl_0
  csr
m0   qsfpdd_xcvr_test_4_xcvr_test_system_0_mm_bridge_0
  s0
m0   qsfpdd_xcvr_test_4_xcvr_native_s10_etile_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_conduit_ctrl_0

xcvr_conduit_ctrl v1.0
qsfpdd_xcvr_test_4_mm_bridge_0 m0   qsfpdd_xcvr_test_4_xcvr_conduit_ctrl_0
  csr
qsfpdd_xcvr_test_4_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_4_xcvr_native_s10_etile_0 rx_pma_ready  
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_native_s10_etile_0

altera_xcvr_native_s10_etile v21.0.0
qsfpdd_xcvr_test_4_mm_bridge_0 m0   qsfpdd_xcvr_test_4_xcvr_native_s10_etile_0
  reconfig_avmm
qsfpdd_xcvr_test_4_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
qsfpdd_xcvr_test_4_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
refclk_etile_9a out_clk  
  pll_refclk0
rx_clkout   qsfpdd_xcvr_test_4_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
rx_pma_ready   qsfpdd_xcvr_test_4_xcvr_conduit_ctrl_0
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_st_converter_0

xcvr_st_converter v1.0
qsfpdd_xcvr_test_4_xcvr_native_s10_etile_0 rx_clkout   qsfpdd_xcvr_test_4_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
rx_clkout_a_output   qsfpdd_xcvr_test_4_xcvr_native_s10_etile_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_test_system_0_clk_50

clock_source vnull
qsfpdd_xcvr_test_4_clk_50 clk   qsfpdd_xcvr_test_4_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_4_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_4_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v19.1
qsfpdd_xcvr_test_4_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
qsfpdd_xcvr_test_4_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v19.1
qsfpdd_xcvr_test_4_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
qsfpdd_xcvr_test_4_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
qsfpdd_xcvr_test_4_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_4_xcvr_test_system_0_freq_counter_0
  csr
qsfpdd_xcvr_test_4_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_4_xcvr_test_system_0_clk_50 clk   qsfpdd_xcvr_test_4_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
qsfpdd_xcvr_test_4_mm_bridge_0 m0  
  s0
m0   qsfpdd_xcvr_test_4_xcvr_test_system_0_freq_counter_0
  csr
m0   qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_test_system_0_rx_fifo

fifo v19.1
qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_4_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_test_system_0_tx_fifo

fifo v19.1
qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_4_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
q_sys_iopll_9a outclk0  
  rx_clkout2
outclk0  
  tx_clkout2
tx_clkout2_sample   qsfpdd_xcvr_test_4_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
qsfpdd_xcvr_test_4_xcvr_test_system_0_rx_fifo fifo_input   qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
qsfpdd_xcvr_test_4_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   qsfpdd_xcvr_test_4_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   qsfpdd_xcvr_test_4_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
qsfpdd_xcvr_test_4_xcvr_test_system_0_tx_fifo fifo_input   qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_4_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
qsfpdd_xcvr_test_4_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out
data_pattern_generator_pattern_out_fifo_write   qsfpdd_xcvr_test_4_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   qsfpdd_xcvr_test_4_xcvr_test_system_0_tx_fifo
  fifo_output


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5

qsfpdd_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_clk_100

clock_source vnull
clk_100 clk   qsfpdd_xcvr_test_5_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_5_xcvr_native_s10_etile_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_clk_50

clock_source vnull
clk_50 clk   qsfpdd_xcvr_test_5_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_5_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_5_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_5_xcvr_conduit_ctrl_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_5_clk_50 clk   qsfpdd_xcvr_test_5_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   qsfpdd_xcvr_test_5_xcvr_conduit_ctrl_0
  csr
m0   qsfpdd_xcvr_test_5_xcvr_test_system_0_mm_bridge_0
  s0
m0   qsfpdd_xcvr_test_5_xcvr_native_s10_etile_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_conduit_ctrl_0

xcvr_conduit_ctrl v1.0
qsfpdd_xcvr_test_5_mm_bridge_0 m0   qsfpdd_xcvr_test_5_xcvr_conduit_ctrl_0
  csr
qsfpdd_xcvr_test_5_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_5_xcvr_native_s10_etile_0 rx_pma_ready  
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_native_s10_etile_0

altera_xcvr_native_s10_etile v21.0.0
qsfpdd_xcvr_test_5_mm_bridge_0 m0   qsfpdd_xcvr_test_5_xcvr_native_s10_etile_0
  reconfig_avmm
qsfpdd_xcvr_test_5_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
qsfpdd_xcvr_test_5_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
refclk_etile_9a out_clk  
  pll_refclk0
rx_clkout   qsfpdd_xcvr_test_5_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
rx_pma_ready   qsfpdd_xcvr_test_5_xcvr_conduit_ctrl_0
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_st_converter_0

xcvr_st_converter v1.0
qsfpdd_xcvr_test_5_xcvr_native_s10_etile_0 rx_clkout   qsfpdd_xcvr_test_5_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
rx_clkout_a_output   qsfpdd_xcvr_test_5_xcvr_native_s10_etile_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_test_system_0_clk_50

clock_source vnull
qsfpdd_xcvr_test_5_clk_50 clk   qsfpdd_xcvr_test_5_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_5_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_5_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v19.1
qsfpdd_xcvr_test_5_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
qsfpdd_xcvr_test_5_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v19.1
qsfpdd_xcvr_test_5_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
qsfpdd_xcvr_test_5_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
qsfpdd_xcvr_test_5_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_5_xcvr_test_system_0_freq_counter_0
  csr
qsfpdd_xcvr_test_5_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_5_xcvr_test_system_0_clk_50 clk   qsfpdd_xcvr_test_5_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
qsfpdd_xcvr_test_5_mm_bridge_0 m0  
  s0
m0   qsfpdd_xcvr_test_5_xcvr_test_system_0_freq_counter_0
  csr
m0   qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_test_system_0_rx_fifo

fifo v19.1
qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_5_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_test_system_0_tx_fifo

fifo v19.1
qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_5_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
q_sys_iopll_9a outclk0  
  rx_clkout2
outclk0  
  tx_clkout2
tx_clkout2_sample   qsfpdd_xcvr_test_5_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
qsfpdd_xcvr_test_5_xcvr_test_system_0_rx_fifo fifo_input   qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
qsfpdd_xcvr_test_5_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   qsfpdd_xcvr_test_5_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   qsfpdd_xcvr_test_5_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
qsfpdd_xcvr_test_5_xcvr_test_system_0_tx_fifo fifo_input   qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_5_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
qsfpdd_xcvr_test_5_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out
data_pattern_generator_pattern_out_fifo_write   qsfpdd_xcvr_test_5_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   qsfpdd_xcvr_test_5_xcvr_test_system_0_tx_fifo
  fifo_output


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6

qsfpdd_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_clk_100

clock_source vnull
clk_100 clk   qsfpdd_xcvr_test_6_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_6_xcvr_native_s10_etile_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_clk_50

clock_source vnull
clk_50 clk   qsfpdd_xcvr_test_6_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_6_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_6_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_6_xcvr_conduit_ctrl_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_6_clk_50 clk   qsfpdd_xcvr_test_6_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   qsfpdd_xcvr_test_6_xcvr_conduit_ctrl_0
  csr
m0   qsfpdd_xcvr_test_6_xcvr_test_system_0_mm_bridge_0
  s0
m0   qsfpdd_xcvr_test_6_xcvr_native_s10_etile_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_conduit_ctrl_0

xcvr_conduit_ctrl v1.0
qsfpdd_xcvr_test_6_mm_bridge_0 m0   qsfpdd_xcvr_test_6_xcvr_conduit_ctrl_0
  csr
qsfpdd_xcvr_test_6_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_6_xcvr_native_s10_etile_0 rx_pma_ready  
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_native_s10_etile_0

altera_xcvr_native_s10_etile v21.0.0
qsfpdd_xcvr_test_6_mm_bridge_0 m0   qsfpdd_xcvr_test_6_xcvr_native_s10_etile_0
  reconfig_avmm
qsfpdd_xcvr_test_6_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
qsfpdd_xcvr_test_6_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
refclk_etile_9a out_clk  
  pll_refclk0
rx_clkout   qsfpdd_xcvr_test_6_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
rx_pma_ready   qsfpdd_xcvr_test_6_xcvr_conduit_ctrl_0
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_st_converter_0

xcvr_st_converter v1.0
qsfpdd_xcvr_test_6_xcvr_native_s10_etile_0 rx_clkout   qsfpdd_xcvr_test_6_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
rx_clkout_a_output   qsfpdd_xcvr_test_6_xcvr_native_s10_etile_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_test_system_0_clk_50

clock_source vnull
qsfpdd_xcvr_test_6_clk_50 clk   qsfpdd_xcvr_test_6_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_6_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_6_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v19.1
qsfpdd_xcvr_test_6_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
qsfpdd_xcvr_test_6_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v19.1
qsfpdd_xcvr_test_6_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
qsfpdd_xcvr_test_6_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
qsfpdd_xcvr_test_6_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_6_xcvr_test_system_0_freq_counter_0
  csr
qsfpdd_xcvr_test_6_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_6_xcvr_test_system_0_clk_50 clk   qsfpdd_xcvr_test_6_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
qsfpdd_xcvr_test_6_mm_bridge_0 m0  
  s0
m0   qsfpdd_xcvr_test_6_xcvr_test_system_0_freq_counter_0
  csr
m0   qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_test_system_0_rx_fifo

fifo v19.1
qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_6_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_test_system_0_tx_fifo

fifo v19.1
qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_6_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
q_sys_iopll_9a outclk0  
  rx_clkout2
outclk0  
  tx_clkout2
tx_clkout2_sample   qsfpdd_xcvr_test_6_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
qsfpdd_xcvr_test_6_xcvr_test_system_0_rx_fifo fifo_input   qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
qsfpdd_xcvr_test_6_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   qsfpdd_xcvr_test_6_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   qsfpdd_xcvr_test_6_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
qsfpdd_xcvr_test_6_xcvr_test_system_0_tx_fifo fifo_input   qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_6_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
qsfpdd_xcvr_test_6_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out
data_pattern_generator_pattern_out_fifo_write   qsfpdd_xcvr_test_6_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   qsfpdd_xcvr_test_6_xcvr_test_system_0_tx_fifo
  fifo_output


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7

qsfpdd_xcvr_test v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_clk_100

clock_source vnull
clk_100 clk   qsfpdd_xcvr_test_7_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_7_xcvr_native_s10_etile_0
  reconfig_clk
clk_reset  
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_clk_50

clock_source vnull
clk_50 clk   qsfpdd_xcvr_test_7_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_7_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_7_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_7_xcvr_conduit_ctrl_0
  clock
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_7_clk_50 clk   qsfpdd_xcvr_test_7_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   qsfpdd_xcvr_test_7_xcvr_conduit_ctrl_0
  csr
m0   qsfpdd_xcvr_test_7_xcvr_test_system_0_mm_bridge_0
  s0
m0   qsfpdd_xcvr_test_7_xcvr_native_s10_etile_0
  reconfig_avmm


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_conduit_ctrl_0

xcvr_conduit_ctrl v1.0
qsfpdd_xcvr_test_7_mm_bridge_0 m0   qsfpdd_xcvr_test_7_xcvr_conduit_ctrl_0
  csr
qsfpdd_xcvr_test_7_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_7_xcvr_native_s10_etile_0 rx_pma_ready  
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_native_s10_etile_0

altera_xcvr_native_s10_etile v21.0.0
qsfpdd_xcvr_test_7_mm_bridge_0 m0   qsfpdd_xcvr_test_7_xcvr_native_s10_etile_0
  reconfig_avmm
qsfpdd_xcvr_test_7_clk_100 clk  
  reconfig_clk
clk_reset  
  reconfig_reset
qsfpdd_xcvr_test_7_xcvr_st_converter_0 rx_clkout_a_output  
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
refclk_etile_9a out_clk  
  pll_refclk0
rx_clkout   qsfpdd_xcvr_test_7_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
rx_pma_ready   qsfpdd_xcvr_test_7_xcvr_conduit_ctrl_0
  rx_pma_ready
rx_ready  
  rx_ready
tx_pma_ready  
  tx_pma_ready
tx_ready  
  tx_ready


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_st_converter_0

xcvr_st_converter v1.0
qsfpdd_xcvr_test_7_xcvr_native_s10_etile_0 rx_clkout   qsfpdd_xcvr_test_7_xcvr_st_converter_0
  rx_clkout
tx_clkout  
  tx_clkout
rx_is_lockedtodata  
  rx_is_lockedtodata
qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in  
  rx_data_a
rx_clkout_a_output   qsfpdd_xcvr_test_7_xcvr_native_s10_etile_0
  rx_coreclkin
tx_clkout_a_output  
  tx_coreclkin
rx_parallel_data  
  rx_parallel_data
tx_parallel_data  
  tx_parallel_data
rx_clkout_a   qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_clk
tx_clkout_a   qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_test_system_0

xcvr_test_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_test_system_0_clk_50

clock_source vnull
qsfpdd_xcvr_test_7_clk_50 clk   qsfpdd_xcvr_test_7_xcvr_test_system_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   qsfpdd_xcvr_test_7_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_7_xcvr_test_system_0_freq_counter_0
  clock
clk_reset  
  reset
clk   qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v19.1
qsfpdd_xcvr_test_7_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_checker_0
  csr_slave
qsfpdd_xcvr_test_7_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 data_pattern_checker_pattern_in_fifo_read  
  conduit_pattern_in
qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_a  
  conduit_pattern_in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v19.1
qsfpdd_xcvr_test_7_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
qsfpdd_xcvr_test_7_xcvr_test_system_0_clk_50 clk  
  csr_clk
clk_reset  
  reset
qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 data_pattern_generator_pattern_out_fifo_write  
  conduit_pattern_out
conduit_pattern_out_clk   qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_test_system_0_freq_counter_0

freq_counter v1.0
qsfpdd_xcvr_test_7_xcvr_test_system_0_mm_bridge_0 m0   qsfpdd_xcvr_test_7_xcvr_test_system_0_freq_counter_0
  csr
qsfpdd_xcvr_test_7_xcvr_test_system_0_clk_50 clk  
  clock
clk_reset  
  reset
qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_sample  
  sample_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_test_system_0_mm_bridge_0

altera_avalon_mm_bridge v19.1
qsfpdd_xcvr_test_7_xcvr_test_system_0_clk_50 clk   qsfpdd_xcvr_test_7_xcvr_test_system_0_mm_bridge_0
  clk
clk_reset  
  reset
qsfpdd_xcvr_test_7_mm_bridge_0 m0  
  s0
m0   qsfpdd_xcvr_test_7_xcvr_test_system_0_freq_counter_0
  csr
m0   qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_generator_0
  csr_slave
m0   qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_checker_0
  csr_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_test_system_0_rx_fifo

fifo v19.1
qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_7_xcvr_test_system_0_rx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_test_system_0_tx_fifo

fifo v19.1
qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0 fifo_output   qsfpdd_xcvr_test_7_xcvr_test_system_0_tx_fifo
  fifo_output
fifo_input   qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0

xcvr_tx_rx_clkout2_converter v1.0
qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_generator_0 conduit_pattern_out_clk   qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0
  tx_clkout2_a
q_sys_iopll_9a outclk0  
  rx_clkout2
outclk0  
  tx_clkout2
tx_clkout2_sample   qsfpdd_xcvr_test_7_xcvr_test_system_0_freq_counter_0
  sample_clock
rx_clkout2_a   qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in_clk
rx_clkout2_b   qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  data_pattern_checker_pattern_in_fifo_read_clk
tx_clkout2_b   qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  data_pattern_generator_pattern_out_fifo_write_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0

xcvr_user_rx_fifo_converter v1.0
qsfpdd_xcvr_test_7_xcvr_test_system_0_rx_fifo fifo_input   qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_rx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 rx_clkout2_b  
  data_pattern_checker_pattern_in_fifo_read_clk
qsfpdd_xcvr_test_7_xcvr_st_converter_0 rx_clkout_a  
  data_pattern_checker_pattern_in_clk
data_pattern_checker_pattern_in_fifo_read   qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_checker_0
  conduit_pattern_in
fifo_output   qsfpdd_xcvr_test_7_xcvr_test_system_0_rx_fifo
  fifo_output
data_pattern_checker_pattern_in   qsfpdd_xcvr_test_7_xcvr_st_converter_0
  rx_data_a


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0

xcvr_user_tx_fifo_converter v1.0
qsfpdd_xcvr_test_7_xcvr_test_system_0_tx_fifo fifo_input   qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_user_tx_fifo_converter_0
  fifo_input
qsfpdd_xcvr_test_7_xcvr_test_system_0_xcvr_tx_rx_clkout2_converter_0 tx_clkout2_b  
  data_pattern_generator_pattern_out_fifo_write_clk
qsfpdd_xcvr_test_7_xcvr_st_converter_0 tx_clkout_a  
  data_pattern_generator_pattern_out_clk
tx_data_a  
  data_pattern_generator_pattern_out
data_pattern_generator_pattern_out_fifo_write   qsfpdd_xcvr_test_7_xcvr_test_system_0_data_pattern_generator_0
  conduit_pattern_out
fifo_output   qsfpdd_xcvr_test_7_xcvr_test_system_0_tx_fifo
  fifo_output


Parameters

generateLegacySim false
  

Software Assignments

(none)
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