Release Notes For ModelSim Intel FPGA 2019.2 Apr 16 2019 Copyright 1991-2019 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. 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End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/terms_conditions/enduser.cfm. _______________________________________________________________________ * How to Get Support ModelSim Intel FPGA is supported by Intel + World-Wide-Web Support [1]http://www.altera.com/mySupport _______________________________________________________________________ Index to Release Notes * [2]Key Information * [3]Release Announcements in 2019.2 * [4]Base Product Specifications in 2019.2 * [5]Compatibility Issues with Release 2019.2 * [6]General Defects Repaired in 2019.2 * [7]User Interface Defects Repaired in 2019.2 * [8]SystemVerilog Defects Repaired in 2019.2 * [9]VHDL Defects Repaired in 2019.2 * [10]SystemC Defects Repaired in 2019.2 * [11]Mixed Language Defects Repaired in 2019.2 * [12]Document Revision History in 2019.2 _______________________________________________________________________ Key Information * There is no licensing change between 10.7 and 2019.1 or 2019.2. However, if you are migrating to 2019.2 from a release like 10.6 and older, please note that release 2019.2 uses FLEXnet v11.14.1.3. For floating licenses, it will be necessary to verify that the vendor daemon (i.e., mgcld) and the license server (i.e., lmgrd) have FLEXnet versions equal to or greater than 11.14.1.3. If the current FLEXnet version of your vendor daemon and lmgrd are less than 11.14.1.3 then it will be necessary to stop your license server and restart it using the vendor daemon and lmgrd contained in this release. If you use node locked licenses you don't need to do anything. This release will update licensing to MSL v2017_1_patch2 with MGLS v9.17_10.2.4 and PCLS v9.17.10.2.0 In summary, this release uses the following license versions: + FLEXnet v11.14.1.3 + MSL v2017_1_patch2 + MGLS v9.17_10.2.4 + PCLS v9.17.10.2.0 _______________________________________________________________________ Release Announcements in 2019.2 * Due to enhanced security restrictions with web browser PDF plug-ins, some links do not function. Links in HTML documentation are fully functional. Clicking a link within a PDF viewed in a web browser may result in no action, or it may load the title page of the current PDF manual (instead of the intended target in the PDF manual). The unresolved link behavior occurs in all web browsers on Windows and Linux platforms. Because of this behavior, the navigational experience of PDF manuals is compromised. PDF is ideal for printing because of its page-oriented layout. Use the HTML manuals to search for topics, navigate between topics, and click links to examples, videos, reference material, and other related technical content. For information about Adobe's discontinued support of Adobe Reader on Linux platforms and your available options, refer to Knowledge Article MG596568 on SupportNet. Linux is a registered trademark of Linus Torvalds in the U.S. and other countries. * Starting 2019.1 release, support for Windows 7 and 8.1 have discontinued. Only Windows 10 is supported. However, we continue to support Windows 7 & 8.1 with our 10.6 and 10.7 release series until their planned End Of Life (10.6 EOL - mid 2019, 10.7 EOL - mid 2020) to coincide with Microsoft's EOL for Windows 7. _______________________________________________________________________ Base Product Specifications in 2019.2 * [Supported Platforms] Linux RHEL 6 x86/x86-64 Linux RHEL 7 x86/x86-64 Linux SLES 11 x86/x86-64 Linux SLES 12 x86/x86-64 Windows 10 x86/x64 [Supported GCC Compilers (for SystemC)] gcc-5.3.0-linux/gcc-5.3.0-linux_x86_64 gcc-4.7.4-linux/gcc-4.7.4-linux_x86_64 gcc-4.5.0-linux/gcc-4.5.0-linux_x86_64 gcc-4.2.1-mingw32vc12 [OVL (shipped with product)] v2.8.1 [VHDL OSVVM (shipped with product)] v2014.07 [Licensing] FLEXnet v11.14.1.3 MSL v2017_1_patch2 MGLS v9.17_10.2.4 PCLS v9.17.10.2.0 _______________________________________________________________________ Compatibility Issues with Release 2019.2 User Interface Compatibility * QSIM-18738 - (results) Fixes corner cases that were causing the Colorize system in the Transcript window to malfunction for some customers. Using a color of 0 (Normal) now works as a Start Tag. Also, having an End Tag on another line from its matching Start Tag now correctly cleans up the color escape sequence. General Compatibility * QSIM-54154 - (results) Messages printed from VPI or PLI containing the strings "error" or "warning" were counted as tool error and warning and reported in stats output. _______________________________________________________________________ General Defects Repaired in 2019.2 * QSIM-54154 - (results) Messages printed from VPI or PLI containing the strings "error" or "warning" were counted as tool error and warning and reported in stats output. _______________________________________________________________________ User Interface Defects Repaired in 2019.2 * QSIM-18738 - (results) Fixes corner cases that were causing the Colorize system in the Transcript window to malfunction for some customers. Using a color of 0 (Normal) now works as a Start Tag. Also, having an End Tag on another line from its matching Start Tag now correctly cleans up the color escape sequence. * QSIM-53899 - The font size in the Source window is incorrect under some newer X server configurations. This problem has been resolved. _______________________________________________________________________ SystemVerilog Defects Repaired in 2019.2 * [nodvtid] - In some cases, vsim did not generate an error during elaboration when a non-existent class field was the first name in a dotted name. * QSIM-36267 - Vsim would sometimes leak memory when SystemVerilog strings were used in constant functions defined in a package. * QSIM-53856 - Use of the 'inside' operator with an array of 'real' type on the RHS (e.g. "myvar inside { array_of_real }") would trigger an internal error "==? operator invalid for REAL". This issue has been fixed. _______________________________________________________________________ VHDL Defects Repaired in 2019.2 * QSIM-54334 - References within an uninstantiated package to a locally-defined package instantiation could result in incorrect simulator error messages due to incorrect code generation. * QSIM-54962 - An object declaration with an initial value (or default value, for signal) that was the parenthesized OPEN reserved word was accepted and resulted in bad code that would crash the simulator. This is a syntax error that is now detected. * QSIM-54941 - The presence of a package instantiation declaration within the declarative region of a design unit could cause the compiler to incorrectly identify the instantiation as a standalone design unit when compiling a source file with a -just command-line switch. As a consequence, it is possible the extracted generic map clause of the instantiation will refer to objects that are not in scope, or the containing design unit will be broken into two parts that cannot be compiled without syntax errors. * QSIM-55531 - If a component or an entity contains a generic whose type is dependent on another generic of the component or entity. Code generation in vcom or vopt could fail. * QSIM-56373 - A VHDL design unit whose source text is in 2 or more files is not supported. An error will be issued if such a situation is detected. _______________________________________________________________________ SystemC Defects Repaired in 2019.2 * QSIM-39643 - Fixed an incorrect flag setting for the pointer types that would cause an sccom (sccom-6165) merge error. _______________________________________________________________________ Mixed Language Defects Repaired in 2019.2 * QSIM-53578 - When a write-protected library contained a Verilog DU made visible (as its equivalent ENTITY) by VHDL "use lib.all" in a VHDL design unit, if the VHDL design unit then contained an identifier that was the same as the name of this Verilog module, an error would occur as the equivalent ENTITY was being made. This error happened on Windows platforms only. _______________________________________________________________________ Document Revision History in 2019.2 * Revision - Changes - Status/Date + 4.1 - Modifications to improve the readability and comprehension of the content. Approved by Tim Peeke. All technical enhancements, changes, and fixes are listed in this document for all products in this release. Approved by Bryan Ramirez. - Released/April 2019 + 4.0 - Modifications to improve the readability and comprehension of the content. Approved by Tim Peeke. All technical enhancements, changes, and fixes are listed in this document for all products in this release. Approved by Bryan Ramirez. - Released/January 2019 * Author: In-house procedures and working practices require multiple authors for documents. All associated authors for each topic within this document are tracked within the document source. * Revision History: Released documents maintain a revision history of up to four revisions. For earlier revision history, refer to earlier releases of documentation which are available on Support Center (http://support.mentor.com).