Intel® FPGA Emulation Platform for OpenCL™ Getting Started Guide

This guide provides quick steps to install the technical preview of Intel® FPGA Emulation Platform for OpenCL™, compile and run OpenCL kernels on the Emulator.

About the Intel® FPGA Emulation Platform for OpenCL™

Intel® FPGA Emulation Platform for OpenCL™ technical preview includes the runtime and compiler, which runs on Intel® Core™ and Intel® Xeon® processors. It is capable of compiling and running programs written with Intel® OpenCL™ FPGA extensions (for example, with the FPGA 'channels' extension).

The emulator aims to provide:

This version of the emulator is a technical preview, and it does not provide full functional equivalence with an FPGA device. It is provided for evaluation purposes only without any warranties.

System Requirements

Supported OS:

Supported Hardware:

Note

The runtime cannot create more than 4 threads per logical core (physical cores with Intel® HT Technology). For example, if application executes 32 kernels simultaneously it will require at least 8 logical cores (8 physical cores or 4 physical cores with HT option enabled).

Installing Intel® FPGA Emulation Platform for OpenCL™ Technical Preview

To configure environment of current session for using OpenCL™ standalone binaries do the following steps:

  1. Unpack provided binaries to any working directory
  2. Create new .icd file with following content as shown below:
    echo /path/to/binaries/libintelocl_emu.so >> /etc/OpenCL/vendors/intel_fpga_fast_emu.icd
  3. Set INSTALLDIR variable in setupvars.sh script to the path where binaries have been unpacked.

If installation succeeded the following OpenCL™ platform will be available:

Platform [#1]           :

    Profile             : FULL_PROFILE

    Version             : OpenCL 2.0 LINUX

    Name                : Intel(R) FPGA Emulation Platform for OpenCL(TM) (preview)

    Vendor              : Intel(R) Corporation

    Devices             : 1

    Device [#1]         :

        Type            : accelerator

        Profile         : FULL_PROFILE

        Version         : OpenCL 2.0 (Build 5)

        Name            : Intel(R) FPGA Emulation Device (preview)

        Vendor          : Intel(R) Corporation

        C version       : OpenCL C 2.0

        Driver version  : 1.2.0.5

Getting Started with Intel® FPGA Emulation Platform for OpenCL™ Technical Preview  

The emulator provides a separate OpenCL™ platform with one OpenCL™ CPU device. It supports Intel® FPGA OpenCL™ extensions.

OpenCL programs written for FPGA device can be compiled and executed on this device, using standard OpenCL API (including clCreateProgramWithBinary(), see the Offline Compilation section).

There are sets of environment variable affecting emulator execution.

   Optimization guide using OpenMP is available in the directory with binaries (Optimization_guide.pdf).

Offline Compilation  

The Emulator supports OpenCL™ kernels compilation into binaries (similar to .aocx files used for FPGA device), which can be used in clCreateProgramWithBinary().

Use Intel® SDK for OpenCL™ Applications - offline compiler ('ioc64' tool) to compile kernel binaries for the emulator from OpenCL C source code. This tool is distributed as part of Intel® Code Builder for OpenCL™ API:

> ioc64 -bo='-cl-std=CL2.0' -device-fpga_fast_emu -input=source.cl -ir=kernel_binary.elf

Name for the output file is arbitrary, and it can have .aocx extension to let a host program use the same names for both FPGA device and the emulator.

Kernel binaries produced by the 'ioc' tool are not compatible with binaries compiled for FPGA device and vice versa.

Execution

Set of environment variables mentioned in the Getting Started section can affect the emulator behavior.

Bash script (setupvars.sh) distributed with binaries can be used to simplify the environment setting. Please uncomment/modify value for required variable in the script and run the command below:

> . /path/to/binaries/setupvars.sh

After that all application running in current console will use environment variables set in the script.

Generating FPGA static reports

To generate the FPGA static reports on build perform the following steps:

  1. Right click the session in the Code Builder Session Explorer window and select Session Options.
  2. Go the Build Artifacts tab and check the Static Reports option.

 

After each build, the static reports is generated and listed in the session tree as report.html under Build Artifacts.

The static report menu is divided into three section: