Release Notes For Questa Intel FPGA Edition 2021.3 Jul 13 2021 Copyright 1991-2021 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. 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End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/terms_conditions/enduser.cfm. _______________________________________________________________________ * How to Get Support For information on how to obtain technical support, visit the support page at [1]http://supportnet.mentor.com _______________________________________________________________________ Index to Release Notes * [2]Key Information * [3]Release Announcements in 2021.3 * [4]Base Product Specifications in 2021.3 * [5]Compatibility Issues with Release 2021.3 * [6]General Defects Repaired in 2021.3 * [7]SystemVerilog Defects Repaired in 2021.3 * [8]VHDL Defects Repaired in 2021.3 * [9]Power Aware Defects Repaired in 2021.3 * [10]SystemVerilog Enhancements in 2021.3 * [11]Power Aware Enhancements in 2021.3 * [12]Document Revision History in 2021.3 _______________________________________________________________________ Key Information * Starting 2021.1 release, Redhat Enterprise Linux (RHEL) 6 platform and Suse Enterprise Linux (SLES) 11 will not be supported. * QSIM-64029 - There is no licensing change between 2020.x and 2021.1. However, if you are migrating to 2021.1 from a release older than 2020.1, please note that release 2021.1 uses FLEXnet v11.16.4.0. For floating licenses, it will be necessary to verify that the vendor daemon (i.e., mgcld) and the license server (i.e., lmgrd) have FLEXnet versions equal to or greater than 11.16.4.0. If the current FLEXnet version of your vendor daemon and lmgrd are less than 11.16.4.0 then it will be necessary to stop your license server and restart it using the vendor daemon and lmgrd contained in this release. If you use node locked licenses you don't need to do anything. This release will update licensing to MSL v2020_1 with MGLS v9.23_5.5.0 and PCLS v9.23_5.3.0 In summary, this release uses the following license versions: + FLEXnet v11.16.4.0 + MSL v2020_1 + MGLS v9.23_5.5.0 + PCLS v9.23_5.3.0 * QSIM-62239 - For newly supported operating systems, like SUSE15 and RHEL8, it is required to have the libnsl-devel package installed on the system to have the cosim functionality work as expected. * QSIM-67636 - For newly supported operating systems, like SUSE15 and RHEL8, a linking error "[13]liblto_plugin.so: wrong ELF class: ELFCLASS32" might show up while building 32-bit libraries when using GCC versions other than the Versions we officially support. To fix/workaround this error, the flag '-fno-use-linker-plugin' should be passed to the linker command line. This applies to: + 'sccom' when using user specified GCC installation other than the supported ones + Using the shipped GCC executables directly to build 32-bit libraries/executables (using gcc/g++ commands). * QSIM-523 - SystemC/GCC changes starting 2021.1 + SystemC is now supported for the win64 platform + SystemC/DPI/PLI/VPI/FLI default compiler (MinGW GCC) for Windows, both win32 and win64, has been upgraded to 7.4.0 + MinGW GCC 4.2.1 for win32 and MinGW GCC 4.5.0 for win64 are no longer supported and will no longer be distributed with the release + Warnings may be emitted when %ll specifiers for long long 64 bit wide types are used with printf/scanf functions families on Windows when MinGW GCC 7.4.0 is being used + To suppress those warnings, the flag __USE_MINGW_ANSI_STDIO should be defined and set to 1 by passing -D__USE_MINGW_ANSI_STDIO=1 command line option QSIM-57794 - When Visual Studio 2017 is being used for C compilation, compilation errors due to missing printf/scanf functions families definitions may appear. To fix this issue #include should be added for the printf/scanf function families definitions to be available. The Register Assistant version included in this release has been upgraded to RUVM/2021.3 RUVM/2021.3 is a native 64-bit application. _______________________________________________________________________ Release Announcements in 2021.3 * Due to enhanced security restrictions with web browser PDF plug-ins, some links do not function. Links in HTML documentation are fully functional. Clicking a link within a PDF viewed in a web browser may result in no action, or it may load the title page of the current PDF manual (instead of the intended target in the PDF manual). The unresolved link behavior occurs in all web browsers on Windows and Linux platforms. Because of this behavior, the navigational experience of PDF manuals is compromised. PDF is ideal for printing because of its page-oriented layout. Use the HTML manuals to search for topics, navigate between topics, and click links to examples, videos, reference material, and other related technical content. For information about Adobe's discontinued support of Adobe Reader on Linux platforms and your available options, refer to Knowledge Article MG596568 on SupportNet. Linux is a registered trademark of Linus Torvalds in the U.S. and other countries. * Notice of Accessibility For ModelSim, Questa SIM, and Visualizer Debug Environment products, U.S. English is the only language supported. _______________________________________________________________________ Base Product Specifications in 2021.3 * [Supported Platforms] Linux RHEL 7 x86/x86-64 Linux RHEL 8 x86/x86-64 Linux SLES 12 x86/x86-64 Linux SLES 15 x86/x86-64 Windows 10 x86/x64 [Supported GCC Compilers (for SystemC)] gcc-7.4.0-linux/gcc-7.4.0-linux_x86_64 gcc-5.3.0-linux/gcc-5.3.0-linux_x86_64 gcc-4.7.4-linux/gcc-4.7.4-linux_x86_64 gcc-7.4.0-mingw32vc15 gcc-7.4.0-mingw64vc15 [OVL (shipped with product)] v2.8.1 [VHDL OSVVM (shipped with product)] v2014.07 [VHDL UVVM (shipped with product)] UVVM v2019.11.25 [Licensing] FLEXnet v11.16.4.0 MSL v2020_1 MGLS v9.23_5.5.0 PCLS v9.23.5.3.0 _______________________________________________________________________ Compatibility Issues with Release 2021.3 SystemVerilog Compatibility * [nodvtid] - (source) Questa's SystemVerilog compiler now aligns with the 1800-2017 LRM regarding syntax for the use of the "pure virtual" keywords. If you have code that uses class_item_qualifiers, please place them after the use of "pure virtual". For example: "protected pure virtual" should be written as "pure virtual protected" * [nodvtid] - (results) This is a fix to a VPI bug when the caller attempts to get a VPI handle using a single index on a reg variable with more than 2 indexes (i.e. a top index select from a 3 or more dimensional reg). VPI would supply a handle with incorrect typing (vpiRegBit) in this case. Incorrect typing can cause related problems with other VPI requests on the returned object handle such as vpi_get_value(). The typing of objects after this fix is vpiReg. General Compatibility * QSIM-68397 - (source, results) fix for vopt crash : JIRA 68397 : updaing the concat chain late after optimizations are done.However resolve_expr still makes the concat chain early in vopt phase.We stop pulling of intermediate concat expressions within a concat during loop invariant optimization. * QSIM-66630 - (source, results) adding integer overflow warning at compile time : fix for JIRA 66630 _______________________________________________________________________ General Defects Repaired in 2021.3 * QSIM-68397 - (source, results) fix for vopt crash : JIRA 68397 : updaing the concat chain late after optimizations are done.However resolve_expr still makes the concat chain early in vopt phase.We stop pulling of intermediate concat expressions within a concat during loop invariant optimization. * QSIM-66630 - (source, results) adding integer overflow warning at compile time : fix for JIRA 66630 _______________________________________________________________________ SystemVerilog Defects Repaired in 2021.3 * QSIM-69967 - Starting in release 2021.2 some designs would start to generate errors like this in vsim: Error: (vsim-3567) test.sv(27): No field named 'get'. In UVM code calling "type_id::get()". This has been fixed in 2021.3 * QSIM-70177 - Vsim hangs when using -glsnegtchk level3 * QSIM-70154 - In some rare cases, a call to randomize() would cause simulation to hang (without issuing a timeout). This issue has been fixed. * QSIM-70213 - Vsim would sometimes crash after doing a "restart" in designs using SystemVerilog associative arrays or structs with default field values. * [nodvtid] - Single line comments found within SV macros are now captured with the -lint du switch. * QSIM-72424 - In some rare cases, randomize() would cause the simulation to crash when evaluating a constraint referring to an indexed multi-dimensional unpacked array having an out-of-bounds index. This issue has been fixed. * QSIM-70409 - In some rare cases, a randomize() call would cause simulation to crash when evaluating a constraint involving a non-random associative array. This issue has been fixed. * QSIM-70002 - In some cases, randomize() would incorrectly evaluate an if/else constraint if the condition expression contained a division or modulo expression where the divisor could be 0. This issue has been fixed. * QSIM-70103 - In some cases, randomize() would incorrectly evaluate an if/else constraint if the condition expression contained a division or modulo expression where the divisor could be 0. This issue has been fixed. * QSIM-72564 - In some cases, randomize() would produce a -solvefaildebug constraint contradiction report where the displayed values of non-random variables are incorrect. This issue has been fixed. * QSIM-72561 - In some rare cases, randomize() would trigger a (vsim-7209) error "randomize() succeeded but there was an intermediate solver failure due to an internal error". This issue has been fixed. * QSIM-72422 - Extended support for randomize() calls involving dependent array.size() and array.sum() constraints (more scenarios involving these constraints can now be successfully evaluated). * [nodvtid] - (results) This is a fix to a VPI bug when the caller attempts to get a VPI handle using a single index on a reg variable with more than 2 indexes (i.e. a top index select from a 3 or more dimensional reg). VPI would supply a handle with incorrect typing (vpiRegBit) in this case. Incorrect typing can cause related problems with other VPI requests on the returned object handle such as vpi_get_value(). The typing of objects after this fix is vpiReg. * [nodvtid] - (source) Questa's SystemVerilog compiler now aligns with the 1800-2017 LRM regarding syntax for the use of the "pure virtual" keywords. If you have code that uses class_item_qualifiers, please place them after the use of "pure virtual". For example: "protected pure virtual" should be written as "pure virtual protected" _______________________________________________________________________ VHDL Defects Repaired in 2021.3 * QSIM-70266 - Vopt could crash in some cases where a variable of a protected type is declared in a subprogram. * QSIM-70190 - This fixes the Qsim-70190, that is when there was duplicate instantiation of a module in -autoorder for full path names no warning was given, this fixes that now for full path name also warning are given. * QSIM-70517 - Use of an alias or aggregate as an out parameter to a concurrent procedure call could cause vsim to crash. This issue has been fixed. * QSIM-70160 - In certain cases optimization in processes with shared variable was a vsim elaboration crash. This has been fixed. * QSIM-69382 - Corrected the scenario where error should not have been given out by a generic, with initial value and its dimension depended on another generic, when valid values are supplied by the top level entity. * QSIM-68647 - For certain cases with protected types vcom used to crash. This has been fixed. * QSIM-68520 - For some cases of processes with wait statements there used to be a fatal error in vsim due to optimizations. This is now fixed. * QSIM-68838 - For certain cases the sine function of the math real package was giving incorrect assertion. This has been fixed. _______________________________________________________________________ Power Aware Defects Repaired in 2021.3 * QSIM-72381 - If "load_upf -scope " is present in UPF file then we were only changing current scope to "-scope " while parsing loaded UPF file. But design top instance was not changed to "-scope ". As per IEEE 2018 UPF LRM (shown below) design top instance should also change to "-scope " and design top module should be set to module of that instance as quoted below. Here I am fixing this issue. After this change if "load_upf -scope " is present in UPF file then both current scope and design top instance will be set to "-scope " and design top module will be set to module of that instance. If -scope is specified, each instance name in the instance name list shall be a simple name or a hierarchical name rooted in the current scope. In this case, load_upf executes the commands in the scope of each instance, as follows: a) The current scope and "design top instance are both set to the instance, and the design top module is set to the module type of that instance;" b) The commands in the specified UPF file are then executed in the scope of the instance; c) The current scope, design top instance, and design top module then revert to their previous values. * QSIM-70252 - Here issue is if both ISO and LS strategy are present in use_interface_cell then tool is not picking up "use_interface_cell -lib_cells library cells". Now use_interface_cell will consider -lib_cells library cells if both ISO and LS strategy are present or only one of them is present. _______________________________________________________________________ SystemVerilog Enhancements in 2021.3 * [nodvtid] - Introduce 2 new vlog -svext switch options: + miwp - Macro ignore whitespace after paste of macro tokens via tick-tick, ``. + mpwp - Macro preserve whitespace after paste of macro tokens via the tick-tick, ``, text. * QSIM-69835 - The declaration of 'pure' constraints within the context of an abstract class are now supported. _______________________________________________________________________ Power Aware Enhancements in 2021.3 * QSIM-69997 - Tool will stop generating 'report.mspa.txt' file. * QSIM-64383 - Here I am removing "vsim -pa_disabletimezeroevent" option and replacing it with "vopt -pa_disable=timezeroevent" option. Also I replaced "vsim -pa_allowtimezeroevent=all" with "vopt -pa_enable=alltimezeroevent". Also I replaced "vsim -pa_allowtimezeroevent" with "vopt -pa_enable=timezeroevent". Also vsim will give below error if user specifies "vsim -pa_disabletimezeroevent" option. Similar warning will come if "vsim -pa_allowtimezeroevent=[+all]" is specified or environment variable "PA_DISABLETIMEZEROEVENT" is specified. ** Error: (vsim-8796) vsim option -pa_disabletimezeroevent is deprecated. Please replace this with option -pa_disable=timezeroevent in vopt PA. _______________________________________________________________________ Document Revision History in 2021.3 * Revision - Changes - Status/Date + 6.6 - Modifications to improve the readability and comprehension of the content. Approved by Tim Peeke. All technical enhancements, changes, and fixes are listed in this document for all products in this release. Approved by Bryan Ramirez. - Released/July 2021 + 6.5 - Modifications to improve the readability and comprehension of the content. Approved by Tim Peeke. All technical enhancements, changes, and fixes are listed in this document for all products in this release. Approved by Bryan Ramirez. - Released/June 2021 + 6.4 - Modifications to improve the readability and comprehension of the content. Approved by Tim Peeke. All technical enhancements, changes, and fixes are listed in this document for all products in this release. Approved by Bryan Ramirez. - Released/May 2021 * Author: In-house procedures and working practices require multiple authors for documents. All associated authors for each topic within this document are tracked within the document source. * Revision History: Released documents maintain a revision history of up to four revisions. For earlier revision history, refer to earlier releases of documentation which are available on Support Center (http://support.mentor.com).