Release Notes For Questa Sim - Intel FPGA Edition 2022.1 Jan 29 2022 Copyright 1991-2022 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a third-party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. The following are trademarks of of Mentor Graphics Corporation: Questa, ModelSim, JobSpy, and Signal Spy. A current list of Mentor Graphics trademarks may be viewed at www.mentor.com/terms_conditions/trademarks.cfm. End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/terms_conditions/enduser.cfm. _______________________________________________________________________ * How to Get Support For information on how to obtain technical support, visit the support page at [1]http://supportnet.mentor.com _______________________________________________________________________ Index to Release Notes * [2]Key Information * [3]Release Announcements in 2022.1 * [4]Base Product Specifications in 2022.1 * [5]Compatibility Issues with Release 2022.1 * [6]SystemVerilog Defects Repaired in 2022.1 * [7]VHDL Defects Repaired in 2022.1 * [8]Mixed Language Defects Repaired in 2022.1 * [9]Verification Management Defects Repaired in 2022.1 * [10]Power Aware Defects Repaired in 2022.1 * [11]General Enhancements in 2022.1 * [12]User Interface Enhancements in 2022.1 * [13]SystemVerilog Enhancements in 2022.1 * [14]VHDL Enhancements in 2022.1 * [15]SystemC Enhancements in 2022.1 * [16]Mixed Language Enhancements in 2022.1 * [17]Power Aware Enhancements in 2022.1 * [18]Document Revision History in 2022.1 _______________________________________________________________________ Key Information * RUVM is replaced with RA (full HDL Register Assistant) from 2022.1 onward releases. First version RA_2022.1 to be part of 2022.1 release. * QSIM-74070 - (source) Starting 2022.1 release, OSVVM and UVVM libraries are no longer shipped in Questa installation. Users needing these libraries can directly download them to compile and use with QuestaSim * QSIM-72784 - This release supports the new licensing solution, Siemens Advanced Licensing Technology (SALT), and includes new licensing documentation: Siemens Digital Industries Software License Server Installation Instructions and Siemens Digital Industries Software Licensing Manual for Mentor Products. Please refer to your product licensing installation document first. There is no change between 2021.x and 2022.1 with regards to the FLEXnet version used, it continues to be FLEXnet v11.16.4.0. For floating licenses, it will be necessary to verify that the vendor daemon (i.e., mgcld) and the license server (i.e., lmgrd) have FLEXnet versions equal to or greater than 11.16.4.0. If the current FLEXnet version of your vendor daemon and lmgrd are less than 11.16.4.0 then it will be necessary to stop your license server and restart it using the vendor daemon and lmgrd contained in this release. If you use node locked licenses you don't need to do anything. This release will update licensing to SALT v1.4.3.0. In summary, this release uses the following license versions: + FLEXnet v11.16.4.0 + SALT v1.4.3.0 * (source, results) Starting from 2023.1 release: 1. For linux and linux_x86_64: 1. GCC 5.3.0 and GCC 4.7.4 will no longer be supported and they will no longer be distributed with the release. * For linux_aarch64: 1. GCC 5.4.0 will no longer be supported and it will no longer be distributed with the release. _______________________________________________________________________ Release Announcements in 2022.1 * Due to enhanced security restrictions with web browser PDF plug-ins, some links do not function. Links in HTML documentation are fully functional. Clicking a link within a PDF viewed in a web browser may result in no action, or it may load the title page of the current PDF manual (instead of the intended target in the PDF manual). The unresolved link behavior occurs in all web browsers on Windows and Linux platforms. Because of this behavior, the navigational experience of PDF manuals is compromised. PDF is ideal for printing because of its page-oriented layout. Use the HTML manuals to search for topics, navigate between topics, and click links to examples, videos, reference material, and other related technical content. For information about Adobe's discontinued support of Adobe Reader on Linux platforms and your available options, refer to Knowledge Article MG596568 on SupportNet. Linux is a registered trademark of Linus Torvalds in the U.S. and other countries. * Notice of Accessibility For ModelSim, Questa SIM, and Visualizer Debug Environment products, U.S. English is the only language supported. * QSIM-75179 - voptclassic is deprecated from 2022.1 and subsequent releases. If voptclassic is used either directly or by setting environment variable QUESTA_CLASSIC_VOPT, it will produce an error, displaying a deprecation message, which can be suppressed or downgraded to a warning or a note. If suppressed, it will still produce a warning message displaying a deprecation message. Users can continue using voptclassic in 2022.1 either by suppressing or downgrading the error message. However, voptclassic is not recommended and vopt should be used instead. _______________________________________________________________________ Base Product Specifications in 2022.1 * [Supported Platforms] Linux RHEL 7 x86/x86-64 Linux RHEL 8 x86/x86-64 Linux SLES 12 x86/x86-64 Linux SLES 15 x86/x86-64 Windows 10 x86/x64 [Supported GCC Compilers (for SystemC)] gcc-7.4.0-linux/gcc-7.4.0-linux_x86_64 gcc-5.3.0-linux/gcc-5.3.0-linux_x86_64 gcc-4.7.4-linux/gcc-4.7.4-linux_x86_64 gcc-7.4.0-mingw32vc15 gcc-7.4.0-mingw64vc15 [OVL (shipped with product)] v2.8.1 [Licensing] FLEXnet v11.16.4.0 SALT v1.4.3.0 _______________________________________________________________________ Compatibility Issues with Release 2022.1 Key Information Compatibility * QSIM-74070 - (source) Starting 2022.1 release, OSVVM and UVVM libraries are no longer shipped in Questa installation. Users needing these libraries can directly download them to compile and use with QuestaSim * [nodvtid] - (source, results) Starting from 2023.1 release: 1. For linux and linux_x86_64: 1. GCC 5.3.0 and GCC 4.7.4 will no longer be supported and they will no longer be distributed with the release. * For linux_aarch64: 1. GCC 5.4.0 will no longer be supported and it will no longer be distributed with the release. SystemVerilog Compatibility * QSIM-74505 - (source, results) Added an option (-svext=numscale) to allow a scale factor to immediately follow a numeric literal (e.g., "10u"). Supported scale factors include: 'T' for 10**12, 'G' for 10**9, 'M' for 10**6, 'K' or 'k' for 10**3, 'm' for 10**-3, 'u' for 10**-6, 'n' for 10**-9, 'p' for 10**-12, 'f' for 10**-15, and 'a' for 10**-18. * QSIM-68970 - (results) In some cases, a constraint involving a right-shift >> expression where the shift amount (RHS) is equal to 32 would be incorrectly evaluated by randomize(). This issue has been fixed. * [nodvtid] - (results) This is a fix to a VPI bug when the caller attempts to get a VPI handle using a single index on a reg variable with more than 2 indexes (i.e. a top index select from a 3 or more dimensional reg). VPI would supply a handle with incorrect typing (vpiRegBit) in this case. Incorrect typing can cause related problems with other VPI requests on the returned object handle such as vpi_get_value(). The typing of objects after this fix is vpiReg. * QSIM-73554 - (results) Tagging severity clarification (Note/Warning/Error/Fatal) with UI-Msg. * QSIM-74566 - (results) A real value expression connected to a vector input port should behave as a continuous assignment from the real value to the vector port, but instead, the value was converted with an implicit $realtobits. This non-LRM compliant behavior has been corrected. Use the vsim -svext=rtob option to retain the non-LRM compliant behavior. * QSIM-74263 - (results) In some rare cases, randomize() would generate an invalid solution (a solution which does not satisfy all of the specified constraints) when evaluating constraints involving indexed expressions. This issue has been fixed. * QSIM-73535 - (results) In order to make the behavior of randomize() calls involving constraints with random indices consistent, the following changes to the DEFAULT behavior of randomize() have been made: 1. out-of-bound random index expressions will not be allowed in any context (2-state, 4-state, packed, or unpacked) 2. the "-svrandext=impvecindex" extension is removed and replaced by the "-svrandext=oobidx" extension The "oobidx" (-svrandext=oobidx) extension will allow an out-of-bounds (OOB) value for an indexed-expression w/ random indices if any of the following criterion is fulfilled: + The base-expression of indexed-expression is a 2-state packed type, i.e. array, vector etc. + The base-expression of indexed-expression is an unpacked array of 2-state packed elements. The "oobidx" extension will be DISABLED by default. VHDL Compatibility * QSIM-70291 - (source, results) For array of record , under oem or incr flow , the crash was happening .We have to consider array of record td .The fix has been put to 2020.x, 2021.x and mainline. * QSIM-74868 - (source, results) The API used was wrong. Change in API suggested . No fix was required. * QSIM-69871 - (results) The drivers associated with an output port may be initialized incorrectly if the formal port and the actual signal both have no explicit initial value and the subtypes of the port and actual have different 'left values. This does not happen in all cases. It requires several other optimizations to occur including the port's entity being inlined. A work around is to place an explicit initial value on the port. * QSIM-75726 - (results) The behavior of -autoorder on vcom depended on design units already present in libraries begin referenced in the source. During vcom's autoorder scanning vcom could incorrect believe an identifier referred to a precompiled design unit in a library. This would result the loading of that design unit and a matching loading message. A change has been made to prevent vcom from loading any design unit from a library during the scan. The result is some loading message are not longer appear in the transcript. Some loading message are generated at different locations in the transcript. This change may impact qrun's automatic design root detection. In general it will determine more design roots the previous but it also will be consistent and independent of compile order. Mixed Language Compatibility * QSIM-68231 - (results) In previous releases, Verilog instances from VHDL had their ports always made visible for reading and writing. That is no longer the case. By default the ports are not visible for any access unless they have been explicit set by the user or something in the design like signal_spy or sdf_annotation automatically adds access. The user may have to modify the vopt command line to add needed visibility. * [nodvtid] - (results) Previous releases would have port visibility turned on for a Verilog module instantiated from VHDL architecture. This has changed to not be the default behavior. As a result, logging, forcing, examining of a port may require that addition of +acc or -access switches to vopt to enable visibility of such ports. Power Aware Compatibility * QSIM-73032 - (results) Complex optimizable assignments are now treated as buffer assignments and no corruption semantics are applied on them. Example - assign out = p1 ? a : b; Here, p1 is parameter and can be evaluated at elab time. The above assignment will now be treated as buffer assignment and out will not be corrupted. For backward compatibility, a new vopt option -pa_disable=optfeedthru has been added. Use this option to get the old corruption behavior. * QSIM-75624 - (results) vopt -pa_disable=gluelogiciso option will now report sink port(s) of each inserted isolation cell in report.pa.txt. * QSIM-74937 - (results) vopt -pa_disable=gluelogiciso option will now report sink port(s) of each inserted isolation cell in report.pa.txt. * QSIM-75565 - (results) Now reset value is correctly shown in ISO_CLAMP_DIFF_AS_RESET check in report.static.txt for concatenated style ports like age,gender,kind as shown below. assign {age, gender, kind}= gen; always @(posedge clk) begin if (!rstn) begin gen ={10'b0, 1'b0, 5'b01000}; end else begin gen = {age_i, gender_i, kind_i}; end end * QSIM-68902 - (results) for Liberty cell which have is_soi attribute true in the design, tool will start using the vct specified on the connecting net for bias pin connection of cell ports to the specified net. * QSIM-74407 - (results) Here fix is not to ignore external specification for macro instances and top level instance but ignore it for all other instances. Also removed option "vopt -pa_disable-hierrelsuppattr" because this behavior will be made default. Current tool default behavior is - process external context specification for all instances. It is changed as follows - 1. by default UPF3.1 external context specification will be followed i.e. external context specification will be ignored for nonmacro hierarchical instances. It will be honored only for top level design or macro instances. 2. if user specifies vopt -pa_enable=hierrelsuppattr then external context specification will be honored for all instances. * QSIM-73005 - (results) Here I am making vopt -pa_enable=hardmacroboundary default enable. Also set_design_attributes -is_hard_macro/-is_soft_macro will be supported irrespective of upf_version specified in UPF file. Here I am creating an anonymous power domain for hard macro if it doesn't have it's own. Also I am associating hard macro anonymous power domain primary with parent power domain primary. Anonymous power domain name format is as per below UPF 3.1 LRM statement. All hard instances whose primary power domain are same will be part of same anonymous power domain. Anonymous power creation scope will be it's parent instance because it's primary is associated with parent domain primary. Anonymous power domain will be reported in PA reports however I am not adding anonymous power domain activity info messages in vsim. For anonymous power domains, the name of the power domain will be a tool-generated ID of following format. #UPFANONPD# e.g. /top/dut_i/macro/#UPFANONPD1# * QSIM-73747 - (results) Default value of vopt -pa_enable=orderbysupply is changed to TRUE from FALSE. So that means now ISO, LS cells of a port will be ordered by their supplies. * [nodvtid] - (results) Added support for -switch_type fine_grain and -instance for create_power_switch upf command * QSIM-59534 - (results) Added support for -instance and -switch_type fine_grain for create_power_switch upf command SystemC Compatibility * QSIM-74417 - (source, results) Starting from 2023.1 release: 1. For linux and linux_x86_64: 1. GCC 5.3.0 and GCC 4.7.4 will no longer be supported and they will no longer be distributed with the release. * For linux_aarch64: 1. GCC 5.4.0 will no longer be supported and it will no longer be distributed with the release. _______________________________________________________________________ SystemVerilog Defects Repaired in 2022.1 * QSIM-68752 - In some rare cases, a randomize() call with in-line constraints would cause simulation to crash after being invoked multiple times. This issue has been fixed. * QSIM-69038 - In some cases, a function call to a DPI function in a constraint context would trigger an internal error during vopt. This issue has been fixed. * QSIM-68551 - In some cases, a constraint containing bit/part-select on an element of a non-random unpacked array would trigger an internal error during randomize(). This issue has been fixed. * QSIM-68970 - (results) In some cases, a constraint involving a right-shift >> expression where the shift amount (RHS) is equal to 32 would be incorrectly evaluated by randomize(). This issue has been fixed. * QSIM-67215 - Default argument values for classes defined in packages would sometimes generate an internal "(vsim-184)" error message. This error occurred when the default value included a call to a class method. * QSIM-69242 - In some rare cases, an internal error would occur during a randomize() call involving a random packed array. This issue has been fixed. * QSIM-69623 - In some cases involving SVA assertions, vsim would crash during simulation when the RNG trace tool is enabled. This issue has been fixed. * QSIM-69542 - In some rare cases, randomize() would generate an invalid solution when evaluating a scenario involving constraints that refer to a virtual interface. This issue has been fixed. * QSIM-70177 - Vsim hangs when using -glsnegtchk level3 * QSIM-70154 - In some rare cases, a call to randomize() would cause simulation to hang (without issuing a timeout). This issue has been fixed. * QSIM-70213 - Vsim would sometimes crash after doing a "restart" in designs using SystemVerilog associative arrays or structs with default field values. * [nodvtid] - Single line comments found within SV macros are now captured with the -lint du switch. * QSIM-68968 - An enum variable may only be assigned to same enum type variable or one of its value. otherwise it would be a violation for SV strong typing rules for enum date type. [ e.g.-assigning a default value to structure having enum variable] In case of violation it gives a suppressible error now . We can suppress the error to preserve the previous behavior. * QSIM-72424 - In some rare cases, randomize() would cause the simulation to crash when evaluating a constraint referring to an indexed multi-dimensional unpacked array having an out-of-bounds index. This issue has been fixed. * QSIM-70409 - In some rare cases, a randomize() call would cause simulation to crash when evaluating a constraint involving a non-random associative array. This issue has been fixed. * QSIM-70002 - In some cases, randomize() would incorrectly evaluate an if/else constraint if the condition expression contained a division or modulo expression where the divisor could be 0. This issue has been fixed. * QSIM-70103 - In some cases, randomize() would incorrectly evaluate an if/else constraint if the condition expression contained a division or modulo expression where the divisor could be 0. This issue has been fixed. * QSIM-72564 - In some cases, randomize() would produce a -solvefaildebug constraint contradiction report where the displayed values of non-random variables are incorrect. This issue has been fixed. * QSIM-72561 - In some rare cases, randomize() would trigger a (vsim-7209) error "randomize() succeeded but there was an intermediate solver failure due to an internal error". This issue has been fixed. * QSIM-72422 - Extended support for randomize() calls involving dependent array.size() and array.sum() constraints (more scenarios involving these constraints can now be successfully evaluated). * [nodvtid] - (results) This is a fix to a VPI bug when the caller attempts to get a VPI handle using a single index on a reg variable with more than 2 indexes (i.e. a top index select from a 3 or more dimensional reg). VPI would supply a handle with incorrect typing (vpiRegBit) in this case. Incorrect typing can cause related problems with other VPI requests on the returned object handle such as vpi_get_value(). The typing of objects after this fix is vpiReg. * QSIM-69312 - Vsim (error id - 3908) will report error if actual modport is of different type than formal modport in a module. * QSIM-72811 - A suppressible error will be given with this change whenever there is multi-assignment in always_ff. * QSIM-73554 - (results) Tagging severity clarification (Note/Warning/Error/Fatal) with UI-Msg. * QSIM-74569 - SV designs with a large number of virtual interface types used in a large number of parameterized classes would sometimes crash in vsim elaboration. * QSIM-74566 - (results) A real value expression connected to a vector input port should behave as a continuous assignment from the real value to the vector port, but instead, the value was converted with an implicit $realtobits. This non-LRM compliant behavior has been corrected. Use the vsim -svext=rtob option to retain the non-LRM compliant behavior. * QSIM-75121 - In some rare cases, randomize() would trigger an internal error when evaluating a constraint involving a random index expression on an array with a large number of elements. This issue has been fixed. * QSIM-75091 - In some rare cases, randomize() would fail with a timeout error when evaluating a scenario involving 'soft' constraints. This issue has been fixed. * QSIM-75061 - Declaring a production named 'state' within the context of a 'randsequence' statement would trigger a spurious "Production 'state' already declared in this randsequence" error. This issue has been fixed. * QSIM-74932 - In some rare cases, a randomize() call would hang when '-solvefaildebug=2' was enabled. This issue has been fixed. * QSIM-74381 - For randomize() calls, enabling '-solvefaildebug=2' is expected to negatively impact performance (expected worst-case impact of 30%). However, in some rare cases, randomize() would run up to 100x slower when '-solvefaildebug=2' was enabled. This issue has been fixed. * QSIM-74508 - Iterative (foreach) constraints are now supported for the following variable types: + enumerated type + packed struct/union * QSIM-73372 - Attempting to randomize a random variable of 4-state enumerated type, where the enumerated type defines values containing 'x' and 'z' bits, would trigger a spurious "Invalid X or Z in a state expression value within a constraint" error. This issue has been fixed. Note: Given such a scenario, any enum values containing 'x' and 'z' bits would be ignored as valid values during randomization. * QSIM-74118 - An internal error would be triggered when evaluating a randomize() call involving a random index constraint on a non-random array of string elements. This issue has been fixed. * QSIM-73985 - Previous versions of Questa would incorrectly interpret an unbased/unsized constant literal '1 on the RHS of an 'inside' or 'dist' operator. This issue has been fixed. Backwards compatibility for the old (broken) behavior is provided via the compile-time SystemVerilog extension "-svext=+idlitres". * QSIM-74263 - (results) In some rare cases, randomize() would generate an invalid solution (a solution which does not satisfy all of the specified constraints) when evaluating constraints involving indexed expressions. This issue has been fixed. _______________________________________________________________________ VHDL Defects Repaired in 2022.1 * QSIM-69871 - (results) The drivers associated with an output port may be initialized incorrectly if the formal port and the actual signal both have no explicit initial value and the subtypes of the port and actual have different 'left values. This does not happen in all cases. It requires several other optimizations to occur including the port's entity being inlined. A work around is to place an explicit initial value on the port. * QSIM-70266 - Vopt could crash in some cases where a variable of a protected type is declared in a subprogram. * QSIM-70190 - This fixes the Qsim-70190, that is when there was duplicate instantiation of a module in -autoorder for full path names no warning was given, this fixes that now for full path name also warning are given. * QSIM-70517 - Use of an alias or aggregate as an out parameter to a concurrent procedure call could cause vsim to crash. This issue has been fixed. * QSIM-70160 - In certain cases optimization in processes with shared variable was a vsim elaboration crash. This has been fixed. * QSIM-68647 - For certain cases with protected types vcom used to crash. This has been fixed. * QSIM-68520 - For some cases of processes with wait statements there used to be a fatal error in vsim due to optimizations. This is now fixed. * QSIM-68838 - For certain cases the sine function of the math real package was giving incorrect assertion. This has been fixed. * QSIM-54676 - The behavior of the standard_arith functions is changed, if any of the inputs is NULL the output of the operator will be false. * QSIM-72353 - The said failure in which the wrong index was being driven has been fixed. * QSIM-56228 - Fixed issue where message error levels were incorrectly changed when referencing a package.This could happen if the -suppess/-error/-warning settings are identical for all design units. * QSIM-73842 - In vsim, an elaboration time crash could occur if an entity has a generic that is of type signed, unsigned, or std_logic_vector. The generic must also have a default value expression other than an aggregate or literal. This requires the entity to be compiled with the -2008 switch. Since the issue is bad code generation vopt must be re-run again to resolve the problem. * [nodvtid] - vopt time could be excessive if a signal for generate or a group of nested generates elaborated to a large number of total iterations. * QSIM-75002 - In selected and conditional assignments, an error could incorrectly be generated if an integer value was raised to a static expression that had a negative value. This could occur during vcom or vopt and the expression in question either would not or may not be executed during simulation. * QSIM-75434 - When multiple files are specified to vcom, some error message would report the correct line number for error message but the file give would be incorrect. Vcom incorrectly always reported the first file provided on vcom command line. The work around is to compile the files individually. * QSIM-70291 - (source, results) For array of record , under oem or incr flow , the crash was happening .We have to consider array of record td .The fix has been put to 2020.x, 2021.x and mainline. * QSIM-73611 - In some cases vcom -refresh_marked complains about _lock in a library which doesn't needs to be opened. This issue has been fixed. * QSIM-75726 - (results) The behavior of -autoorder on vcom depended on design units already present in libraries begin referenced in the source. During vcom's autoorder scanning vcom could incorrect believe an identifier referred to a precompiled design unit in a library. This would result the loading of that design unit and a matching loading message. A change has been made to prevent vcom from loading any design unit from a library during the scan. The result is some loading message are not longer appear in the transcript. Some loading message are generated at different locations in the transcript. This change may impact qrun's automatic design root detection. In general it will determine more design roots the previous but it also will be consistent and independent of compile order. * QSIM-75885 - A crash could occur in a process that did not contain a wait statement directly and called a VHDL-2008 procedure that is an instance of a generic subprogram. * QSIM-74868 - (source, results) The API used was wrong. Change in API suggested . No fix was required. * QSIM-74001 - For certain specific For loops an incorrect out of range error was generated. This has been fixed. * QSIM-74606 - For certain cases, while unrolling for-generate loop, vopt used to crash. This has been fixed. * QSIM-75001 - For some specific cases of clocked processes where variable is written in conditional block, vsim use to give incorrect result. This has been fixed. * QSIM-74564 - The order of the location of procedures and their mappings in VHDL file, used to affect compilation. This defect has been fixed _______________________________________________________________________ Mixed Language Defects Repaired in 2022.1 * QSIM-68231 - (results) In previous releases, Verilog instances from VHDL had their ports always made visible for reading and writing. That is no longer the case. By default the ports are not visible for any access unless they have been explicit set by the user or something in the design like signal_spy or sdf_annotation automatically adds access. The user may have to modify the vopt command line to add needed visibility. _______________________________________________________________________ Verification Management Defects Repaired in 2022.1 * VM-11453 - When VRM re-queues a script due to a failure, the VRM Results window will display "Rerun Pending" instead of "Running" for the time between the initial failure and the time the script is re-launched a second time. * VM-14727 - Fixed bug where large quantity of log output from tests executed as a grid array job could result in a "max size for a Tcl value exceeded" message and subsequent failure. _______________________________________________________________________ Power Aware Defects Repaired in 2022.1 * QSIM-69493 - Starting 2020.1 tool is interpreting '.' differently in set_port_attributes -elements {.} command. Earlier dot used to mean current scope but now dot means set_design_top command. This change is done to align tool with UPF 1801-2108 LRM statement shown below. I added an option -pa_enable=dotascurrentscope' to switch to old behavior before 2020.1. "If -elements is specified and the element_list is . (a dot), the command applies to the design top instance." * QSIM-69114 - The tool now accepts the clamp value the same length as part/bit select of candidate port in isolation strategy. Also the tool reports that the bit/part select clamp value specified in isolation strategy is matching the bit/part select reset value (present in HDL/RTL) as "ISO_CLAMP_SAME_AS_RESET " in report.static.txt. * QSIM-68982 - Added bitiwse checking of isolation strategy clamp value and set_port_attributes -clamp_value for ISO_CLAMP_MISMATCH static check for vector port whose bit select/part select specified in isolation strategy or set_port_attributes command. * QSIM-68500 - Tool was not applying isolation on wire struct type port. Fixed it. * QSIM-72381 - If "load_upf -scope " is present in UPF file then we were only changing current scope to "-scope " while parsing loaded UPF file. But design top instance was not changed to "-scope ". As per IEEE 2018 UPF LRM (shown below) design top instance should also change to "-scope " and design top module should be set to module of that instance as quoted below. Here I am fixing this issue. After this change if "load_upf -scope " is present in UPF file then both current scope and design top instance will be set to "-scope " and design top module will be set to module of that instance. If -scope is specified, each instance name in the instance name list shall be a simple name or a hierarchical name rooted in the current scope. In this case, load_upf executes the commands in the scope of each instance, as follows: a) The current scope and "design top instance are both set to the instance, and the design top module is set to the module type of that instance;" b) The commands in the specified UPF file are then executed in the scope of the instance; c) The current scope, design top instance, and design top module then revert to their previous values. * QSIM-70252 - Here issue is if both ISO and LS strategy are present in use_interface_cell then tool is not picking up "use_interface_cell -lib_cells library cells". Now use_interface_cell will consider -lib_cells library cells if both ISO and LS strategy are present or only one of them is present. * QSIM-73032 - (results) Complex optimizable assignments are now treated as buffer assignments and no corruption semantics are applied on them. Example - assign out = p1 ? a : b; Here, p1 is parameter and can be evaluated at elab time. The above assignment will now be treated as buffer assignment and out will not be corrupted. For backward compatibility, a new vopt option -pa_disable=optfeedthru has been added. Use this option to get the old corruption behavior. * QSIM-74361 - Added verror info in vopt warning 9859 as follows Verror: | If an isolation strategy is path based semantics that means it will be inserted in some fanout edges of placed port but not all fanout edges of the placed port then isolation will not be inserted in gluelogic edge under -pa_disable=gluelogiciso option and this warning will come. Here gluelogic means access logic (like assign statement or always block) without module boundary. Purpose of this warning is to inform user that this path does not have proper module boundary and user should put gluelogic inside proper module boundary to get isolation cell. For details on path-based semantics, see "Path-Based Semantics For Power Aware Strategies" in Power Aware User Manual. * QSIM-75624 - (results) vopt -pa_disable=gluelogiciso option will now report sink port(s) of each inserted isolation cell in report.pa.txt. * QSIM-74937 - (results) vopt -pa_disable=gluelogiciso option will now report sink port(s) of each inserted isolation cell in report.pa.txt. * QSIM-75565 - (results) Now reset value is correctly shown in ISO_CLAMP_DIFF_AS_RESET check in report.static.txt for concatenated style ports like age,gender,kind as shown below. assign {age, gender, kind}= gen; always @(posedge clk) begin if (!rstn) begin gen ={10'b0, 1'b0, 5'b01000}; end else begin gen = {age_i, gender_i, kind_i}; end end * QSIM-73316 - + Currently, tool doesn't have support for splitting liberty information bitwise on a bus and expects all bits to have same information. + The goal is to enable user to provide liberty information specific to a bit, which can be different from the other bits on the same port. + Below liberty attributes need to be handled under this supported. 1. related_power_pin 2. related_ground_pin 3. related_bias_pin 4. power_down_function 5. direction * QSIM-59544 - + The objective is to align the semantics of '-ack_port' option of UPF command 'create_power_switch' with UPF 3.1. + A power switch is in an off state when the (explicit or default) -off_state is True. An off power switch begins to turn on when an -on_state or -on_partial_state condition becomes True. A power switch is in a fully on state when some -on_state condition is True. A fully on power switch begins to turn off when the last remaining -on_state condition that was True becomes False, or when an explicit -off_state condition becomes True. + If an ack_port argument is specified, the Boolean expression is optional. If a Boolean expression is specified for ack_port, it shall be a constant (0 or 1) or a simple expression in terms of the control ports of the power switch. The default value of this simple expression is taken to be the constant 1. + If the Boolean expression for -ack_port is a constant 0 or 1, that constant value is driven onto the specified port_name delay time units after the switch begins to turn on and the inverse of the constant value is driven onto the specified port_name delay time units after the switch begins to turn off. If the switch goes into an ERROR state, then a corrupted value is driven onto the ack_port immediately. For verification, the initial value of the specified ack_port is the inverse of the constant value, which indicates that the power switch is in the OFF state at time zero. + If a Boolean expression for -ack_port is specified as a nonconstant value and the switch is in a state that is not an ERROR state, then the result of the Boolean expression is driven onto the specified port_name delay time units after a control port transition. If the switch goes into an ERROR state, then a corrupted value is driven onto the ack_port, immediately. + If -supply_set is specified for a switch, it powers logic or timing-control circuitry within the switch. When the supply set simstate is anything other than NORMAL, the acknowledge ports are corrupted. + This semantic is enabled with vopt option -pa_upfversion=3.1 Previous semantic remains in place otherwise * QSIM-72870 - Objective is to flag a note at report.static.txt if the user has disabled one or more static checks and point to the file that have these disable commands. _______________________________________________________________________ General Enhancements in 2022.1 * QSIM-70009 - Enhanced xprop to support code coverage under vopt option "-xprop_enable=codecoverage" _______________________________________________________________________ User Interface Enhancements in 2022.1 * QSIM-72524 - The vsim SystemVerilog constrained-random extension "genmodseedfix" has been deprecated. Use of this switch (-svrandext=genmodseedfix) will trigger a warning. This extension will be removed in a future release. _______________________________________________________________________ SystemVerilog Enhancements in 2022.1 * QSIM-68953 - vsim-3837 is made suppressible. Before the fix we used to give error on below multiple assignments. Now the error is made suppressible. The result of suppressing the error is not defined. logic a; assign a = 1; assign a = 0; * QSIM-68664 - Added option "-class_randstate " to the 'bp' command to specify that the breakpoint should only be triggered when the randstate of 'this' in the context of the breakpoint (if any) matches the specified randstate_string. If there is no 'this' within the context of the breakpoint, this condition will be ignored. * QSIM-68665 - Added a new RNG trace option (vsim -rngtraceopt) "showthis" that will append the class name and ciid of 'this' in the context of an RNG trace event (if any) to each output line generated by RNG trace (vsim -rngtrace). If there is no 'this' in the context of an RNG trace event, no additional output is appended. The format of the appended output will be "[@]". * QSIM-68666 - Added vsim option "-rngtracesplit=" specifying that the RNG trace output file should be split when the number of events recorded by the output file exceeds . This option only applies when an RNG trace output file is specified via "vsim -rngtrace=". When "-rngtracesplit=" is specified, the filename of the output file will be modified such that the suffix "." is appended to the filename, where is a number (starting from 0) indicating the individual partitions of the RNG trace output. * QSIM-68447 - The error (vlog-2934) "Argument for randomize() function must be a field of 'this'" can now be downgraded to a warning or suppressed. * QSIM-69835 - The declaration of 'pure' constraints within the context of an abstract class are now supported. * QSIM-16674 - wait_order(a,b,c) PassStmt else FailStmt [ optional] The wait_order construct suspends the calling process until all of the specified events are triggered in the given order (left to right) or any of the untriggered events are triggered out of order and thus causes the operation to fail. For wait_order to succeed, at any point in the sequence, the subsequent events, which shall all be untriggered at this point or the sequence would have already failed, shall be triggered in the prescribed once an event occurs in the prescribed order, it can be triggered again without causing the construct to fail Upon failure of construct , If fail statement is specified, then the given failure statement is executed . If the fail statement is not specified, a failure generates a run-time error. Examples: wait_order(a,b,c) : suspends the current process until events a, b, and c trigger in the order a -> b -> c. If the events trigger out of order, a run-time error is generated as failure statement is not specified wait_order( a, b, c ) else $display( "Error: events out of order" ); upon failure a user message is displayed without an run time error * QSIM-74505 - (source, results) Added an option (-svext=numscale) to allow a scale factor to immediately follow a numeric literal (e.g., "10u"). Supported scale factors include: 'T' for 10**12, 'G' for 10**9, 'M' for 10**6, 'K' or 'k' for 10**3, 'm' for 10**-3, 'u' for 10**-6, 'n' for 10**-9, 'p' for 10**-12, 'f' for 10**-15, and 'a' for 10**-18. * QSIM-73146 - Changed the compile-time SystemVerilog extension "ifslvbefr" (-svext=ifslvbefr) to be DISABLED by default. + When this extension is DISABLED, a compile-time warning for solve/before constraints in conditional contexts will be issued. If -pedanticerrors is specified, the warning is elevated to an error. + When this extension is ENABLED, no compile-time warning for solve/before constraints in conditional contexts are reported. Changed the compile-time SystemVerilog extension "softunique" (-svext=softunique) to be DISABLED by default. + When this extension is DISABLED, a compile-time warning for 'soft unique' constraints will be issued. If -pedanticerrors is specified, the warning is elevated to an error. + When this extension is ENABLED, no compile-time warning for 'soft unique' constraints are reported. Changed the warning for non-LRM compliant 'dist' constraint with 'randc' target from simulation-time to compile-time. If -pedanticerrors is specified, the warning is elevated to an error. * QSIM-74376 - A warning will now be issued during a randomize() call involving a random variable of 4-state enumerated type, where the enumerated type defines values containing 'x' and 'z' bits. Note: Given such a scenario, any enum values containing 'x' and 'z' bits would be ignored as valid values during randomization. * QSIM-62212 - Added compile time extension"-svext=+stdrandarg" that allows hier-ref and indexed variable exprs as arguments to randomize() calls without triggering vlog-2961 warnings. This extension is DISABLED by default. Running with -pedanticerrors will elevate the vlog-2961 warning to an error (unless the stdrandarg extension is enabled). * QSIM-73535 - (results) In order to make the behavior of randomize() calls involving constraints with random indices consistent, the following changes to the DEFAULT behavior of randomize() have been made: 1. out-of-bound random index expressions will not be allowed in any context (2-state, 4-state, packed, or unpacked) 2. the "-svrandext=impvecindex" extension is removed and replaced by the "-svrandext=oobidx" extension The "oobidx" (-svrandext=oobidx) extension will allow an out-of-bounds (OOB) value for an indexed-expression w/ random indices if any of the following criterion is fulfilled: + The base-expression of indexed-expression is a 2-state packed type, i.e. array, vector etc. + The base-expression of indexed-expression is an unpacked array of 2-state packed elements. The "oobidx" extension will be DISABLED by default. _______________________________________________________________________ VHDL Enhancements in 2022.1 * QSIM-67576 - For some specific cases of calling to_integer function where argument size is greater than 32 bit, we use to trim the argument and reduce it to 32 bit without giving a warning. Now for such cases warning will be produced. * [nodvtid] - Fixed Qsim 9190 vhdl precedence order error returned. _______________________________________________________________________ SystemC Enhancements in 2022.1 * QSIM-69083 - + Starting 2022.1, std::thread is supported on the Windows platform for SystemC designs. + Note: + It is known that some #define might cause compilation errors, now that including the SystemC header #include "systemc.h" implicitly includes the MinGW std::thread headers + For example: adding the line #define m 50 before #include "systemc.h" will cause a compilation error on Windows because the MinGW std::thread headers have some variable named m QSIM-74417 - (source, results) Starting from 2023.1 release: 1. For linux and linux_x86_64: 1. GCC 5.3.0 and GCC 4.7.4 will no longer be supported and they will no longer be distributed with the release. For linux_aarch64: 1. GCC 5.4.0 will no longer be supported and it will no longer be distributed with the release. _______________________________________________________________________ Mixed Language Enhancements in 2022.1 * [nodvtid] - (results) Previous releases would have port visibility turned on for a Verilog module instantiated from VHDL architecture. This has changed to not be the default behavior. As a result, logging, forcing, examining of a port may require that addition of +acc or -access switches to vopt to enable visibility of such ports. _______________________________________________________________________ Power Aware Enhancements in 2022.1 * QSIM-69997 - Tool will stop generating 'report.mspa.txt' file. * QSIM-69893 - + DEFAULT Behavior o By default, the tool does not re-evaluate initial blocks that contains the $finish or $stop statements, but if replay control is applied explicitly on a specific initial block using the sim_replay_control or set_design_attributes command, the tool re-evaluates that initial block. o Replay control applied globally on the whole design (-pa_enable=reevalinitial / set_design_attributes {qpa_replay_init} ) will have least precedence (lower than sim_replay_control or set_design_attributes set on an element). + -pa_enable=reevalinitall o Re-evaluates initial blocks that contains the $finish or $stop statements. + -pa_disable=reevalinitall o Disables re-evaluating the initial blocks that do not have any assignment statements, but if replay control is applied explicitly on a specific initial block using the sim_replay_control or set_design_attributes command, the tool re-evaluates that initial block. * QSIM-69456 - Tool will not dump 'report.de.txt ' file with vopt option '-pa_genrpt'. User will need to explicitly use 'pa_genrpt=de' option to generate the file. * QSIM-72344 - Tool will give Error if name of an UPF object clashes with name of a design object. * QSIM-69968 - In 'pa_checks' command, for option ' -glitch_window