Release Notes For Questa Intel FPGA Edition 2021.2 Apr 14 2021 Copyright 1991-2021 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. 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End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/terms_conditions/enduser.cfm. _______________________________________________________________________ * How to Get Support For information on how to obtain technical support, visit the support page at [1]http://supportnet.mentor.com _______________________________________________________________________ Index to Release Notes * [2]Key Information * [3]Release Announcements in 2021.2 * [4]Base Product Specifications in 2021.2 * [5]Compatibility Issues with Release 2021.2 * [6]SystemVerilog Defects Repaired in 2021.2 * [7]VHDL Defects Repaired in 2021.2 * [8]Mixed Language Defects Repaired in 2021.2 * [9]Power Aware Defects Repaired in 2021.2 * [10]SystemVerilog Enhancements in 2021.2 * [11]Power Aware Enhancements in 2021.2 * [12]Document Revision History in 2021.2 _______________________________________________________________________ Key Information * Starting 2021.1 release, Redhat Enterprise Linux (RHEL) 6 platform and Suse Enterprise Linux (SLES) 11 will not be supported. * QSIM-64029 - There is no licensing change between 2020.x and 2021.1. However, if you are migrating to 2021.1 from a release older than 2020.1, please note that release 2021.1 uses FLEXnet v11.16.4.0. For floating licenses, it will be necessary to verify that the vendor daemon (i.e., mgcld) and the license server (i.e., lmgrd) have FLEXnet versions equal to or greater than 11.16.4.0. If the current FLEXnet version of your vendor daemon and lmgrd are less than 11.16.4.0 then it will be necessary to stop your license server and restart it using the vendor daemon and lmgrd contained in this release. If you use node locked licenses you don't need to do anything. This release will update licensing to MSL v2020_1 with MGLS v9.23_5.5.0 and PCLS v9.23_5.3.0 In summary, this release uses the following license versions: + FLEXnet v11.16.4.0 + MSL v2020_1 + MGLS v9.23_5.5.0 + PCLS v9.23_5.3.0 * QSIM-62239 - For newly supported operating systems, like RHEL8, it is required to have the libnsl-devel package installed on the system to have the cosim functionality work as expected. * QSIM-67636 - For newly supported operating systems, like RHEL8, a linking error "[13]liblto_plugin.so: wrong ELF class: ELFCLASS32" might show up while building 32-bit libraries when using GCC versions other than the Versions we officially support. To fix/workaround this error, the flag '-fno-use-linker-plugin' should be passed to the linker command line. This applies to: + 'sccom' when using user specified GCC installation other than the supported ones + Using the shipped GCC executables directly to build 32-bit libraries/executables (using gcc/g++ commands). * QSIM-523 - SystemC/GCC changes starting 2021.1 + SystemC is now supported for the win64 platform + SystemC/DPI/PLI/VPI/FLI default compiler (MinGW GCC) for Windows, both win32 and win64, has been upgraded to 7.4.0 + MinGW GCC 4.2.1 for win32 and MinGW GCC 4.5.0 for win64 are no longer supported and will no longer be distributed with the release + Warnings may be emitted when %ll specifiers for long long 64 bit wide types are used with printf/scanf functions families on Windows when MinGW GCC 7.4.0 is being used + To suppress those warnings, the flag __USE_MINGW_ANSI_STDIO should be defined and set to 1 by passing -D__USE_MINGW_ANSI_STDIO=1 command line option QSIM-57794 - When Visual Studio 2017 is being used for C compilation, compilation errors due to missing printf/scanf functions families definitions may appear. To fix this issue #include should be added for the printf/scanf function families definitions to be available. The Register Assistant version included within this release has been upgraded to RUVM/2021.2. RUVM/2021.2 is a native 64bit application. _______________________________________________________________________ Release Announcements in 2021.2 * Due to enhanced security restrictions with web browser PDF plug-ins, some links do not function. Links in HTML documentation are fully functional. Clicking a link within a PDF viewed in a web browser may result in no action, or it may load the title page of the current PDF manual (instead of the intended target in the PDF manual). The unresolved link behavior occurs in all web browsers on Windows and Linux platforms. Because of this behavior, the navigational experience of PDF manuals is compromised. PDF is ideal for printing because of its page-oriented layout. Use the HTML manuals to search for topics, navigate between topics, and click links to examples, videos, reference material, and other related technical content. For information about Adobe's discontinued support of Adobe Reader on Linux platforms and your available options, refer to Knowledge Article MG596568 on SupportNet. Linux is a registered trademark of Linus Torvalds in the U.S. and other countries. _______________________________________________________________________ Base Product Specifications in 2021.2 * [Supported Platforms] Linux RHEL 7 x86/x86-64 Linux RHEL 8 x86/x86-64 Linux SLES 12 x86/x86-64 Windows 10 x86/x64 [Supported GCC Compilers (for SystemC)] gcc-7.4.0-linux/gcc-7.4.0-linux_x86_64 gcc-5.3.0-linux/gcc-5.3.0-linux_x86_64 gcc-4.7.4-linux/gcc-4.7.4-linux_x86_64 gcc-7.4.0-mingw32vc15 gcc-7.4.0-mingw64vc15 [OVL (shipped with product)] v2.8.1 [VHDL OSVVM (shipped with product)] v2014.07 [VHDL UVVM (shipped with product)] UVVM v2019.11.25 [Licensing] FLEXnet v11.16.4.0 MSL v2020_1 MGLS v9.23_5.5.0 PCLS v9.23.5.3.0 _______________________________________________________________________ Compatibility Issues with Release 2021.2 SystemVerilog Compatibility * QSIM-68970 - (results) In some cases, a constraint involving a right-shift >> expression where the shift amount (RHS) is equal to 32 would be incorrectly evaluated by randomize(). This issue has been fixed. VHDL Compatibility * QSIM-67808 - (results) Issue is Fixed * QSIM-69871 - (results) The drivers associated with an output port may be initialized incorrectly if the formal port and the actual signal both have no explicit initial value and the subtypes of the port and actual have different 'left values. This does not happen in all cases. It requires several other optimizations to occur including the port's entity being inlined. A work around is to place an explicit initial value on the port. Mixed Language Compatibility * QSIM-68231 - (results) In previous releases, Verilog instances from VHDL had their ports always made visible for reading and writing. That is no longer the case. By default the ports are not visible for any access unless they have been explicit set by the user or something in the design like signal_spy or sdf_annotation automatically adds access. The user may have to modify the vopt command line to add needed visibility. Power Aware Compatibility * QSIM-68654 - (results) vopt note 9570 has been updated for new power state semantics (UPF version 3.0 and 3.1). Simstate remains undefined in case it is not explicitly defined in UPF by the user for new power state semantics. Note message before : ** Note: ** Note: (vopt-9570) Default NORMAL simstate applied to power state of Supply set . Note message after updating : ** Note: ** Note: (vopt-9570) Simstate not specified for power state of Supply set . * QSIM-64513 - (results) Added reason for marking states as unreachable and undetermined during PST analysis in report.pst.txt _______________________________________________________________________ SystemVerilog Defects Repaired in 2021.2 * QSIM-68752 - In some rare cases, a randomize() call with in-line constraints would cause simulation to crash after being invoked multiple times. This issue has been fixed. * QSIM-69038 - In some cases, a function call to a DPI function in a constraint context would trigger an internal error during vopt. This issue has been fixed. * QSIM-68551 - In some cases, a constraint containing bit/part-select on an element of a non-random unpacked array would trigger an internal error during randomize(). This issue has been fixed. * QSIM-68970 - (results) In some cases, a constraint involving a right-shift >> expression where the shift amount (RHS) is equal to 32 would be incorrectly evaluated by randomize(). This issue has been fixed. * QSIM-67215 - Default argument values for classes defined in packages would sometimes generate an internal "(vsim-184)" error message. This error occurred when the default value included a call to a class method. * QSIM-69242 - In some rare cases, an internal error would occur during a randomize() call involving a random packed array. This issue has been fixed. * QSIM-69623 - In some cases involving SVA assertions, vsim would crash during simulation when the RNG trace tool is enabled. This issue has been fixed. * QSIM-69542 - In some rare cases, randomize() would generate an invalid solution when evaluating a scenario involving constraints that refer to a virtual interface. This issue has been fixed. _______________________________________________________________________ VHDL Defects Repaired in 2021.2 * QSIM-67808 - (results) Issue is Fixed * QSIM-66464 - Fixed an issue related to assigning value to multi-dimensional array through access type variable. * QSIM-65768 - For some specific cases of procedures having "wait for 0 ns" construct inside, vsim used to give incorrect simulation results. This has been fixed. * QSIM-67949 - Stopped the warning that was being given out during elaboration time due to aliasing of an external reference signal. * QSIM-69871 - (results) The drivers associated with an output port may be initialized incorrectly if the formal port and the actual signal both have no explicit initial value and the subtypes of the port and actual have different 'left values. This does not happen in all cases. It requires several other optimizations to occur including the port's entity being inlined. A work around is to place an explicit initial value on the port. _______________________________________________________________________ Mixed Language Defects Repaired in 2021.2 * QSIM-68231 - (results) In previous releases, Verilog instances from VHDL had their ports always made visible for reading and writing. That is no longer the case. By default the ports are not visible for any access unless they have been explicit set by the user or something in the design like signal_spy or sdf_annotation automatically adds access. The user may have to modify the vopt command line to add needed visibility. _______________________________________________________________________ Power Aware Defects Repaired in 2021.2 * QSIM-68591 - There were issues in save and restore event at time zero in retention protocol, leading to vsim error 8933. It has been fixed now. * QSIM-69493 - Starting 2020.1 tool is interpreting '.' differently in set_port_attributes -elements {.} command. Earlier dot used to mean current scope but now dot means set_design_top command. This change is done to align tool with UPF 1801-2108 LRM statement shown below. I added an option -pa_enable=dotascurrentscope' to switch to old behavior before 2020.1. "If -elements is specified and the element_list is . (a dot), the command applies to the design top instance." * QSIM-69114 - The tool now accepts the clamp value the same length as part/bit select of candidate port in isolation strategy. Also the tool reports that the bit/part select clamp value specified in isolation strategy is matching the bit/part select reset value (present in HDL/RTL) as "ISO_CLAMP_SAME_AS_RESET " in report.static.txt. * QSIM-68982 - Added bitiwse checking of isolation strategy clamp value and set_port_attributes -clamp_value for ISO_CLAMP_MISMATCH static check for vector port whose bit select/part select specified in isolation strategy or set_port_attributes command. * QSIM-68500 - Tool was not applying isolation on wire struct type port. Fixed it. * QSIM-69261 - Fixed crash in vopt caused due to on demand module loading in case of map_isolation_cell * QSIM-69565 - Fixed crash caused due to a different coding style in a VHDL block. * QSIM-69562 - Fixed crash in vopt related to case sensitivity of library names. * QSIM-68654 - (results) vopt note 9570 has been updated for new power state semantics (UPF version 3.0 and 3.1). Simstate remains undefined in case it is not explicitly defined in UPF by the user for new power state semantics. Note message before : ** Note: ** Note: (vopt-9570) Default NORMAL simstate applied to power state of Supply set . Note message after updating : ** Note: ** Note: (vopt-9570) Simstate not specified for power state of Supply set . _______________________________________________________________________ SystemVerilog Enhancements in 2021.2 * QSIM-68953 - vsim-3837 is made suppressible. Before the fix we used to give error on below multiple assignments. Now the error is made suppressible. The result of suppressing the error is not defined. logic a; assign a = 1; assign a = 0; * QSIM-68664 - Added option "-class_randstate " to the 'bp' command to specify that the breakpoint should only be triggered when the randstate of 'this' in the context of the breakpoint (if any) matches the specified randstate_string. If there is no 'this' within the context of the breakpoint, this condition will be ignored. * QSIM-68665 - Added a new RNG trace option (vsim -rngtraceopt) "showthis" that will append the class name and ciid of 'this' in the context of an RNG trace event (if any) to each output line generated by RNG trace (vsim -rngtrace). If there is no 'this' in the context of an RNG trace event, no additional output is appended. The format of the appended output will be "[@]". * QSIM-68666 - Added vsim option "-rngtracesplit=" specifying that the RNG trace output file should be split when the number of events recorded by the output file exceeds . This option only applies when an RNG trace output file is specified via "vsim -rngtrace=". When "-rngtracesplit=" is specified, the filename of the output file will be modified such that the suffix "." is appended to the filename, where is a number (starting from 0) indicating the individual partitions of the RNG trace output. * QSIM-68447 - The error (vlog-2934) "Argument for randomize() function must be a field of 'this'" can now be downgraded to a warning or suppressed. _______________________________________________________________________ Power Aware Enhancements in 2021.2 * QSIM-62103 - 1. Added support set_simstate_behavior PORT_CORR_ONLY/SIMSTATE_ONLY/DISABLE. ENABLE is supported under option -pa_upfversion=3.1. 2 .Added support for UPF_is_power_aware_model attribute. 3. Added support for find_objects -traverse_macros. 4. Added support for creating an anonymous power domain for a hard macro if it does not have it's own. * QSIM-55257 - connect_support_net -ports argument now accepts wreal type. The -vct supports upf supply net to wreal connection and vice versa. Example vcts are shown below. create_hdl2upf_vct wreal2upf \ -hdl_type {sv real} \ -table {{`wrealZState OFF} {`wrealXState UNDETERMINED} {<0.9 UNDETERMINED} {>=0.9 PARTIAL_ON} {<1.2 PARTIAL_ON} {>=1.2 FULL_ON}} create_upf2hdl_vct upf2wreal \ -hdl_type {sv real} \ -table {{OFF `wrealZState} {UNDETERMINED `wrealXState}} Consider the following design. Use the following commands to make the upf supply net to wreal connection and vice versa. create_supply_net vdd create_supply_net vdd2 connect_supply_net vdd -ports t/wr -vct upf2wreal connect_supply_net vdd2 -ports t/wr2 -vct wreal2upf wreal_vct.png * QSIM-62974 - PA Dynamic Check 'QPA_GLITCH_ASSERT_ERR' can now be controlled by below commands + (VOPT) pa_checks -checkIds {ugc} o -glitch_window (new option added) o -elements o -domain o -strategies o -powerswitches + (VSIM) pa msg -pa_checks=ugc o -elements o -domain o -strategies o -powerswitches pa msg '-glitch_window' option is now deprecated and will not work. * QSIM-64513 - (results) Added reason for marking states as unreachable and undetermined during PST analysis in report.pst.txt _______________________________________________________________________ Document Revision History in 2021.2 * Revision - Changes - Status/Date + 6.3 - Modifications to improve the readability and comprehension of the content. Approved by Tim Peeke. All technical enhancements, changes, and fixes are listed in this document for all products in this release. Approved by Bryan Ramirez. - Released/April 2021 + 6.2 - Modifications to improve the readability and comprehension of the content. Approved by Tim Peeke. All technical enhancements, changes, and fixes are listed in this document for all products in this release. Approved by Bryan Ramirez. - Released/March 2021 + 6.1 - Modifications to improve the readability and comprehension of the content. Approved by Tim Peeke. All technical enhancements, changes, and fixes are listed in this document for all products in this release. Approved by Bryan Ramirez. - Released/February 2021 * Author: In-house procedures and working practices require multiple authors for documents. All associated authors for each topic within this document are tracked within the document source. * Revision History: Released documents maintain a revision history of up to four revisions. For earlier revision history, refer to earlier releases of documentation which are available on Support Center (http://support.mentor.com).