alt_sld_fab_0

2023.11.28.10:10:49 Datasheet
Overview

Memory Map

alt_sld_fab_0

alt_sld_fab_0 v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_0_alt_sld_fab_0

alt_sld_fab v19.2.0


Parameters

DESIGN_HASH 6ae27d7513b1a6617ae5
NODE_COUNT 14
MAX_WIDTH 0
SETTINGS {fabric agilex_config_reset_release dir agent psig 142e1a3c} {fabric config_clock dir agent psig b4c631e1} {fabric agilex_config_reset_release dir agent psig 142e1a3c} {fabric agilex_config_reset_release dir agent psig 142e1a3c} {fabric agilex_config_reset_release dir agent psig 142e1a3c} {fabric agilex_config_reset_release dir agent psig 142e1a3c} {fabric agilex_config_reset_release dir agent psig 142e1a3c} {fabric agilex_config_reset_release dir agent psig 142e1a3c} {fabric agilex_config_reset_release dir agent psig 142e1a3c} {fabric agilex_config_reset_release dir agent psig 142e1a3c} {fabric agilex_config_reset_release dir agent psig 142e1a3c} {fabric agilex_config_reset_release dir agent psig 142e1a3c} {fabric sld dir agent mfr_code 110 type_code 132 version 1 instance -1 ir_width 3 bridge_agent 0 prefer_host { } psig 9b67919e} {fabric config_clock dir agent psig b4c631e1}
CLOCKS {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} }
AGENTS
EP_INFOS {hpath {reset_release_inst|s10_user_rst_clkgate_0|config_reset_release_endpoint|ep} } {hpath {bts_xcvr__tiles|z1577b_x5_y166_n0__reset_controller|x_f_tile_soft_reset_ctlr_sip_v1|clock_endpoint|ep} } {hpath {bts_xcvr__tiles|z1577b_x5_y166_n0__reset_controller|x_f_tile_soft_reset_ctlr_sip_v1|rst_release_ip_inst|ep} } {hpath {bts_xcvr__tiles|z1577b_x5_y166_n0__avmm1_0|ai_arb_01.av1_ai_inst|rst_release_ep|ep} } {hpath {bts_xcvr__tiles|z1577b_x5_y166_n0__avmm2_12|ai_arb_01.av2_ai_inst|rst_release_ep|ep} } {hpath {bts_xcvr__tiles|z1577b_x5_y166_n0__avmm2_13|ai_arb_01.av2_ai_inst|rst_release_ep|ep} } {hpath {bts_xcvr__tiles|z1577b_x5_y166_n0__avmm2_14|ai_arb_01.av2_ai_inst|rst_release_ep|ep} } {hpath {bts_xcvr__tiles|z1577b_x5_y166_n0__avmm2_15|ai_arb_01.av2_ai_inst|rst_release_ep|ep} } {hpath {bts_xcvr__tiles|z1577b_x5_y166_n0__avmm2_16|ai_arb_01.av2_ai_inst|rst_release_ep|ep} } {hpath {bts_xcvr__tiles|z1577b_x5_y166_n0__avmm2_17|ai_arb_01.av2_ai_inst|rst_release_ep|ep} } {hpath {bts_xcvr__tiles|z1577b_x5_y166_n0__avmm2_18|ai_arb_01.av2_ai_inst|rst_release_ep|ep} } {hpath {bts_xcvr__tiles|z1577b_x5_y166_n0__avmm2_19|ai_arb_01.av2_ai_inst|rst_release_ep|ep} } {hpath {q_sys_u0|master_0|master_0|jtag_phy_embedded_in_jtag_master|node|sld_virtual_jtag_component|sld_virtual_jtag_impl_inst|jtag_signal_adapter|sld_jtag_endpoint_adapter_impl_inst|sld_agent_ep_inst|ep} } {hpath {q_sys_u0|systemclk_f_0|systemclk_f_0|x_sip|clock_endpoint|ep} }
MIRROR 0
TOP_HUB 1
COMPOSED_SETTINGS {fabric agilex_config_reset_release dir agent} {fabric config_clock dir agent} {fabric agilex_config_reset_release dir agent} {fabric agilex_config_reset_release dir agent} {fabric agilex_config_reset_release dir agent} {fabric agilex_config_reset_release dir agent} {fabric agilex_config_reset_release dir agent} {fabric agilex_config_reset_release dir agent} {fabric agilex_config_reset_release dir agent} {fabric agilex_config_reset_release dir agent} {fabric agilex_config_reset_release dir agent} {fabric agilex_config_reset_release dir agent} {fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host {} } {fabric config_clock dir agent}
DEVICE_FAMILY Agilex 7
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_0_alt_sld_fab_0_splitter

altera_sld_splitter v19.2.0
alt_sld_fab_0_alt_sld_fab_0_sldfabric clock_0   alt_sld_fab_0_alt_sld_fab_0_splitter
  clock_12
node_0  
  node_12
alt_sld_fab_0_alt_sld_fab_0_clockfabric clk_0  
  clk_1
clk_1  
  clk_13
alt_sld_fab_0_alt_sld_fab_0_agilexconfigreset conf_reset_0  
  conf_reset_0
conf_reset_1  
  conf_reset_2
conf_reset_2  
  conf_reset_3
conf_reset_3  
  conf_reset_4
conf_reset_4  
  conf_reset_5
conf_reset_5  
  conf_reset_6
conf_reset_6  
  conf_reset_7
conf_reset_7  
  conf_reset_8
conf_reset_8  
  conf_reset_9
conf_reset_9  
  conf_reset_10
conf_reset_10  
  conf_reset_11


Parameters

FRAGMENTS {{name conf_reset type reset dir end ports { {conf_reset reset in 1 0} } properties { {synchronousEdges {None} } } } } {{name clk type clock dir end ports { {clk clk in 1 0} } } } {{name conf_reset type reset dir end ports { {conf_reset reset in 1 0} } properties { {synchronousEdges {None} } } } } {{name conf_reset type reset dir end ports { {conf_reset reset in 1 0} } properties { {synchronousEdges {None} } } } } {{name conf_reset type reset dir end ports { {conf_reset reset in 1 0} } properties { {synchronousEdges {None} } } } } {{name conf_reset type reset dir end ports { {conf_reset reset in 1 0} } properties { {synchronousEdges {None} } } } } {{name conf_reset type reset dir end ports { {conf_reset reset in 1 0} } properties { {synchronousEdges {None} } } } } {{name conf_reset type reset dir end ports { {conf_reset reset in 1 0} } properties { {synchronousEdges {None} } } } } {{name conf_reset type reset dir end ports { {conf_reset reset in 1 0} } properties { {synchronousEdges {None} } } } } {{name conf_reset type reset dir end ports { {conf_reset reset in 1 0} } properties { {synchronousEdges {None} } } } } {{name conf_reset type reset dir end ports { {conf_reset reset in 1 0} } properties { {synchronousEdges {None} } } } } {{name conf_reset type reset dir end ports { {conf_reset reset in 1 0} } properties { {synchronousEdges {None} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 3 23} {irq irq out 1 1} {ir_out ir_out out 3 2} } clock clock assign {debug.controlledBy {link_12} } moduleassign {debug.virtualInterface.link_12 {debug.endpointLink {fabric sld index 1} } } } } {{name clk type clock dir end ports { {clk clk in 1 0} } } }
EXAMPLE
ADD_INTERFACE_ASGN 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_0_alt_sld_fab_0_jtagpins

altera_jtag_wys_atom v19.2.0


Parameters

DEVICE_FAMILY_ID 14
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_0_alt_sld_fab_0_sldfabric

altera_sld_jtag_hub v19.2.0
alt_sld_fab_0_alt_sld_fab_0_jtagpins clock   alt_sld_fab_0_alt_sld_fab_0_sldfabric
  clock
node  
  node
alt_sld_fab_0_alt_sld_fab_0_configresetfabric conf_reset_out_0  
  conf_reset_out
clock_0   alt_sld_fab_0_alt_sld_fab_0_splitter
  clock_12
node_0  
  node_12
ident   alt_sld_fab_0_alt_sld_fab_0_ident
  ident_0


Parameters

DEVICE_FAMILY Agilex 7
SETTINGS {mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host {} }
COUNT 1
N_SEL_BITS 1
N_NODE_IR_BITS 4
NODE_INFO 00001100001000000110111000000000
COMPILATION_MODE 0
BROADCAST_FEATURE 0
FORCE_IR_CAPTURE_FEATURE 1
FORCE_PRE_1_4_FEATURE 0
NEGEDGE_TDO_LATCH 0
ENABLE_SOFT_CORE_CONTROLLER 0
BRIDGE_HOST 0
USE_TCK_ENA 0
BRIDGE_START_INDEX 2
CONN_INDEX 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_0_alt_sld_fab_0_ident

altera_connection_identification_hub v19.2.0
alt_sld_fab_0_alt_sld_fab_0_sldfabric ident   alt_sld_fab_0_alt_sld_fab_0_ident
  ident_0


Parameters

DESIGN_HASH 6ae27d7513b1a6617ae5
COUNT 1
SETTINGS {width 4 latency 0}
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_0_alt_sld_fab_0_configresetfabric

intel_configuration_debug_reset_release_hub v20.3


Parameters

SETTINGS {is_source 0}
COUNT 1
SOURCE_PROVIDED 0
DEVICE_FAMILY_ID 3
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_0_alt_sld_fab_0_intosc

altera_internal_oscillator_atom v19.1.1


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_0_alt_sld_fab_0_clockfabric

altera_config_clock_fabric v19.1
alt_sld_fab_0_alt_sld_fab_0_intosc clock   alt_sld_fab_0_alt_sld_fab_0_clockfabric
  clock
clk_0   alt_sld_fab_0_alt_sld_fab_0_splitter
  clk_1
clk_1  
  clk_13


Parameters

DERIVED_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 2
SETTINGS {} {}
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_0_alt_sld_fab_0_agilexconfigreset

intel_agilex_reset_release_from_sdm v20.3


Parameters

SETTINGS {} {} {} {} {} {} {} {} {} {} {}
COUNT 11
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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