Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
q_sys_inst|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_010|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_010 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_009|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_009 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_008|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_008 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_007 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_006 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_005 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_004 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_003 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_mux|arb|adder |
44 |
22 |
0 |
22 |
22 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_mux|arb |
15 |
0 |
4 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_mux |
1345 |
0 |
0 |
0 |
133 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_demux_010 |
125 |
1 |
2 |
1 |
123 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_demux_009 |
125 |
1 |
2 |
1 |
123 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_demux_008 |
125 |
1 |
2 |
1 |
123 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_demux_007 |
125 |
1 |
2 |
1 |
123 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_demux_006 |
125 |
1 |
2 |
1 |
123 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_demux_005 |
125 |
1 |
2 |
1 |
123 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_demux_004 |
125 |
1 |
2 |
1 |
123 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_demux_003 |
125 |
1 |
2 |
1 |
123 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_demux_002 |
125 |
1 |
2 |
1 |
123 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_demux_001 |
125 |
1 |
2 |
1 |
123 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|rsp_demux |
125 |
1 |
2 |
1 |
123 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|cmd_mux_010 |
125 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|cmd_mux_009 |
125 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|cmd_mux_008 |
125 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|cmd_mux_007 |
125 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|cmd_mux_006 |
125 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|cmd_mux_005 |
125 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|cmd_mux_004 |
125 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|cmd_mux_003 |
125 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|cmd_mux_002 |
125 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|cmd_mux_001 |
125 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|cmd_mux |
125 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|cmd_demux |
145 |
121 |
2 |
121 |
1343 |
121 |
121 |
121 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|master_0_master_limiter |
248 |
0 |
0 |
0 |
256 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_011|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_011 |
114 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_010|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_010 |
114 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_009|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_009 |
114 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_008|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_008 |
114 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_007|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_007 |
114 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_006|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_006 |
114 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_005|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_005 |
114 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_004|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_004 |
114 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_003|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_003 |
114 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_002|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_002 |
114 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_001|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router_001 |
114 |
0 |
2 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router|the_default_decode |
0 |
15 |
0 |
15 |
15 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|router |
114 |
0 |
6 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|system_max_id_0_slv_agent_rsp_fifo |
154 |
39 |
0 |
39 |
113 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|system_max_id_0_slv_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|system_max_id_0_slv_agent |
312 |
39 |
48 |
39 |
336 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_en_sdm_s1_agent_rsp_fifo |
154 |
39 |
0 |
39 |
113 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_en_sdm_s1_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_en_sdm_s1_agent |
312 |
39 |
48 |
39 |
336 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_led_y_s1_agent_rsp_fifo |
154 |
39 |
0 |
39 |
113 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_led_y_s1_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_led_y_s1_agent |
312 |
39 |
48 |
39 |
336 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_led_g_s1_agent_rsp_fifo |
154 |
39 |
0 |
39 |
113 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_led_g_s1_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_led_g_s1_agent |
312 |
39 |
48 |
39 |
336 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_pb_s1_agent_rsp_fifo |
154 |
39 |
0 |
39 |
113 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_pb_s1_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_pb_s1_agent |
312 |
39 |
48 |
39 |
336 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_dipsw_s1_agent_rsp_fifo |
154 |
39 |
0 |
39 |
113 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_dipsw_s1_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_dipsw_s1_agent |
312 |
39 |
48 |
39 |
336 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_3_csr_agent_rsp_fifo |
154 |
39 |
0 |
39 |
113 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_3_csr_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_3_csr_agent |
312 |
39 |
48 |
39 |
336 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_2_csr_agent_rsp_fifo |
154 |
39 |
0 |
39 |
113 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_2_csr_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_2_csr_agent |
312 |
39 |
48 |
39 |
336 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_1_csr_agent_rsp_fifo |
154 |
39 |
0 |
39 |
113 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_1_csr_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_1_csr_agent |
312 |
39 |
48 |
39 |
336 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_power_max10_csr_agent_rsp_fifo |
154 |
39 |
0 |
39 |
113 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_power_max10_csr_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_power_max10_csr_agent |
312 |
39 |
48 |
39 |
336 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_0_csr_agent_rsp_fifo |
154 |
39 |
0 |
39 |
113 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_0_csr_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_0_csr_agent |
312 |
39 |
48 |
39 |
336 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|master_0_master_agent |
200 |
37 |
91 |
37 |
146 |
37 |
37 |
37 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|system_max_id_0_slv_translator |
115 |
5 |
29 |
5 |
72 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_en_sdm_s1_translator |
115 |
6 |
33 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_led_y_s1_translator |
115 |
6 |
33 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_led_g_s1_translator |
115 |
6 |
33 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_pb_s1_translator |
115 |
6 |
33 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|pio_dipsw_s1_translator |
115 |
6 |
33 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_3_csr_translator |
115 |
6 |
28 |
6 |
72 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_2_csr_translator |
115 |
6 |
28 |
6 |
72 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_1_csr_translator |
115 |
6 |
28 |
6 |
72 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_power_max10_csr_translator |
115 |
6 |
28 |
6 |
72 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|i2c_0_csr_translator |
115 |
6 |
28 |
6 |
72 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0|master_0_master_translator |
116 |
13 |
2 |
13 |
109 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|mm_interconnect_0 |
426 |
0 |
1 |
0 |
306 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|pio_pb |
10 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|pio_led_y |
6 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|pio_led_g |
9 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|pio_en_sdm |
38 |
31 |
31 |
31 |
33 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|pio_dipsw |
10 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|p2b_adapter |
14 |
8 |
2 |
8 |
20 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|b2p_adapter |
22 |
0 |
2 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|transacto|p2m |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|transacto |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|p2b |
22 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|b2p |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|fifo |
53 |
41 |
0 |
41 |
10 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|timing_adt |
12 |
0 |
3 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser|crosser |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser |
13 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|output_stage |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser |
14 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_inserter |
12 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_remover |
12 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming |
20 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming |
19 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|jtag_phy_embedded_in_jtag_master|node |
4 |
3 |
0 |
3 |
8 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0|jtag_phy_embedded_in_jtag_master |
38 |
27 |
0 |
27 |
11 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|master_0 |
36 |
0 |
0 |
0 |
70 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10|u_rxfifo|the_dp_ram|auto_generated |
22 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10|u_rxfifo |
13 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10|u_txfifo|the_dp_ram|auto_generated |
24 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10|u_txfifo |
15 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10|u_txout |
29 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10|u_clk_cnt |
65 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10|u_condt_gen |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10|u_condt_det |
9 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10|u_spksupp |
12 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10|u_txshifter |
20 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10|u_rxshifter |
11 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10|u_mstfsm |
26 |
0 |
7 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10|u_csr |
89 |
10 |
37 |
10 |
106 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_power_max10 |
60 |
18 |
0 |
18 |
34 |
18 |
18 |
18 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3|u_rxfifo|the_dp_ram|auto_generated |
14 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3|u_rxfifo |
13 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3|u_txfifo|the_dp_ram|auto_generated |
16 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3|u_txfifo |
15 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3|u_txout |
29 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3|u_clk_cnt |
65 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3|u_condt_gen |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3|u_condt_det |
9 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3|u_spksupp |
12 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3|u_txshifter |
20 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3|u_rxshifter |
11 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3|u_mstfsm |
26 |
0 |
7 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3|u_csr |
81 |
10 |
37 |
10 |
106 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_3 |
60 |
18 |
0 |
18 |
34 |
18 |
18 |
18 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2|u_rxfifo|the_dp_ram|auto_generated |
14 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2|u_rxfifo |
13 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2|u_txfifo|the_dp_ram|auto_generated |
16 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2|u_txfifo |
15 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2|u_txout |
29 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2|u_clk_cnt |
65 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2|u_condt_gen |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2|u_condt_det |
9 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2|u_spksupp |
12 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2|u_txshifter |
20 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2|u_rxshifter |
11 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2|u_mstfsm |
26 |
0 |
7 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2|u_csr |
81 |
10 |
37 |
10 |
106 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_2 |
60 |
18 |
0 |
18 |
34 |
18 |
18 |
18 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1|u_rxfifo|the_dp_ram|auto_generated |
14 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1|u_rxfifo |
13 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1|u_txfifo|the_dp_ram|auto_generated |
16 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1|u_txfifo |
15 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1|u_txout |
29 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1|u_clk_cnt |
65 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1|u_condt_gen |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1|u_condt_det |
9 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1|u_spksupp |
12 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1|u_txshifter |
20 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1|u_rxshifter |
11 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1|u_mstfsm |
26 |
0 |
7 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1|u_csr |
81 |
10 |
37 |
10 |
106 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_1 |
60 |
18 |
0 |
18 |
34 |
18 |
18 |
18 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0|u_rxfifo|the_dp_ram|auto_generated |
14 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0|u_rxfifo |
13 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0|u_txfifo|the_dp_ram|auto_generated |
16 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0|u_txfifo |
15 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0|u_txout |
29 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0|u_clk_cnt |
65 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0|u_condt_gen |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0|u_condt_det |
9 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0|u_spksupp |
12 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0|u_txshifter |
20 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0|u_rxshifter |
11 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0|u_mstfsm |
26 |
0 |
7 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0|u_csr |
81 |
10 |
37 |
10 |
106 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|i2c_0 |
60 |
18 |
0 |
18 |
34 |
18 |
18 |
18 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst|system_max_id_0 |
76 |
0 |
24 |
0 |
58 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
q_sys_inst |
67 |
32 |
0 |
32 |
20 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|max_load_monitor_inst |
7 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|ready_synchronizer |
36 |
0 |
0 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|timing_adapter_0|altera_pfl2_timing_adapter |
36 |
0 |
0 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|timing_adapter_0 |
36 |
0 |
0 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|data_format_adapter_0|altera_pfl2_data_format_adapter |
12 |
0 |
0 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|data_format_adapter_0 |
12 |
0 |
0 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller|nconfig_sync |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller|nreconfigure_sync |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller|enable_sync |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller|condone_sync |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller|nstatus_sync |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller|counter|auto_generated |
21 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_cfg_controller |
22 |
2 |
0 |
2 |
71 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_up_converter|compressed_fifo|data_counter|auto_generated |
5 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_up_converter|compressed_fifo|read_pointer|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_up_converter|compressed_fifo|write_pointer|auto_generated |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_up_converter|compressed_fifo |
13 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_up_converter|counter|auto_generated |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_up_converter |
9 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera|addr_counter|auto_generated |
32 |
0 |
0 |
0 |
29 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera|cfg_counter|auto_generated |
8 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera|tcounter|auto_generated |
8 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_qspi_cfg_micron_altera |
66 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg|altera_pfl2_reset |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_cfg |
16 |
0 |
1 |
0 |
47 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_pgm|jtag_compliant_counter|auto_generated |
4 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_pgm|active_device_counter|auto_generated |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_pgm|bit_counter|auto_generated |
4 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0|altera_pfl2_qspi_pgm |
14 |
7 |
0 |
7 |
21 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst|parallel_flash_loader_2_0 |
10 |
0 |
0 |
0 |
38 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|pfl2_inst |
10 |
0 |
0 |
0 |
38 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst|max_pgm_sel_inst |
9 |
0 |
1 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
max_pfl_ctrl_inst |
16 |
0 |
0 |
0 |
48 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
fan_ctrl_inst |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
pb_filter_inst|filter_circuit_pb_inst5 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
pb_filter_inst|filter_circuit_pb_inst4 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
pb_filter_inst|filter_circuit_pb_inst3 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
pb_filter_inst|filter_circuit_pb_inst2 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
pb_filter_inst|filter_circuit_pb_inst1 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
pb_filter_inst|filter_circuit_pb_inst0 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
pb_filter_inst |
8 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |