Release Notes For Questa Sim - Intel FPGA Edition 2023.1 Jan 23 2023 Copyright 1991-2023 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a third-party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. The following are trademarks of of Mentor Graphics Corporation: Questa, ModelSim, JobSpy, and Signal Spy. A current list of Mentor Graphics trademarks may be viewed at www.mentor.com/terms_conditions/trademarks.cfm. End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/terms_conditions/enduser.cfm. _______________________________________________________________________ * How to Get Support For information on how to obtain technical support, visit the support page at [1]http://supportnet.mentor.com _______________________________________________________________________ Index to Release Notes * [2]Key Information * [3]Release Announcements in 2023.1 * [4]Base Product Specifications in 2023.1 * [5]Compatibility Issues with Release 2023.1 * [6]SystemVerilog Defects Repaired in 2023.1 * [7]VHDL Defects Repaired in 2023.1 * [8]SystemC Defects Repaired in 2023.1 * [9]Qwave logging Defects Repaired in 2023.1 * [10]User Interface Enhancements in 2023.1 * [11]SystemVerilog Enhancements in 2023.1 * [12]VHDL Enhancements in 2023.1 * [13]Power Aware Enhancements in 2023.1 * [14]Document Revision History in 2023.1 _______________________________________________________________________ Key Information * The vhdl2008 technote located at docs/technotes/vhdl2008.note has been removed. * QSIM-78417 - There is no change between 2022.4 and 2023.1 with regards to the FLEXnet version used, it continues to be FLEXnet v11.16.4.0. For floating licenses, it will be necessary to verify that the vendor daemon (i.e., mgcld) and the license server (i.e., lmgrd) have FLEXnet versions equal to or greater than 11.16.4.0. If the current FLEXnet version of your vendor daemon and lmgrd are less than 11.16.4.0 then it will be necessary to stop your license server and restart it using the vendor daemon and lmgrd contained in this release. If you use node locked licenses you don't need to do anything. This release will update licensing to SALT v1.6.1.0. In summary, this release uses the following license versions: + FLEXnet v11.16.4.0 + SALT v1.6.1.0 * QSIM-78850 - + GNU GCC has a known change in behavior starting GCC-9 which causes performance degradation compared to previous versions during the compilation of code that heavily uses inline functions. + This is observable as well on the last version that we currently support (GCC-10.3.0). + The performance degradation is reported in [15]https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89584 + This affects the compilation time of code that heavily makes use of large inline functions. * This is due to the default value of "max-inline-insns-single" changing from 400 to 70. This value dictates the maximum number of instructions for a single inline function. SystemC/DPI/FLI/PLI/VPI code that heavily makes use of large inline functions might face performance degradation during the compilation when GCC-10.3.0 is used. To overcome this change, user can pass "--param max-inline-insns-single=400" to the GCC command or sccom command. QSIM-74070 - (source) Starting 2022.1 release, OSVVM and UVVM libraries are no longer shipped in Questa installation. Users needing these libraries can directly download them to compile and use with QuestaSim (source) For protected HDL source (Verilog and VHDL), legacy ciphers (data_method) "3des-cbc", "des-cbc", "blowfish-cbc", and "cast128-cbc" are no longer supported for either encryption (in vhencrypt/vencrypt) or for decryption (in vcom/vlog). Further, encoding method (enctype) "uuencode" is no longer supported. These are all deprecated by IEEE Std. 1735-2014. For further assistance, please contact a Siemens representative. (source, results) Starting from 2023.1 release: 1. For linux and linux_x86_64: 1. GCC 5.3.0 and GCC 4.7.4 will no longer be supported and they will no longer be distributed with the release. For linux_aarch64: 1. GCC 5.4.0 will no longer be supported and it will no longer be distributed with the release. QSIM-78838 - Vopt would sometimes generate this internal error on index expressions: ** Error: test.sv(7): Questa has encountered an unexpected internal error: ../../src/vlog/vgenindex.c(1205). Please contact Questa support at https://support.sw.siemens.com/ QSIM-75015 - (source, results) GCC changes starting 2023.1: 1. GCC 10.3.0 is now available for linux, linux_x86_64 and linux_aarch64 platforms as the SystemC/DPI/FLI/PLI/VPI default compiler 2. GCC 7.4.0 is still available for all platforms and is the SystemC/DPI/FLI/PLI/VPI default compiler for win32, win64 platforms. 3. For linux and linux_x86_64: + GCC 5.3.0 and GCC 4.7.4 have been dropped and will no longer be supported or distributed with the release 4. For linux_aarch64: + GCC 5.4.0 has been dropped and will no longer be supported or distributed with the release GDB changes starting 2023.1: 1. GDB 10.2.0 is now the only GDB version being shipped for all platforms and is what's used for the CDebug feature _______________________________________________________________________ Release Announcements in 2023.1 * Due to enhanced security restrictions with web browser PDF plug-ins, some links do not function. Links in HTML documentation are fully functional. Clicking a link within a PDF viewed in a web browser may result in no action, or it may load the title page of the current PDF manual (instead of the intended target in the PDF manual). The unresolved link behavior occurs in all web browsers on Windows and Linux platforms. Because of this behavior, the navigational experience of PDF manuals is compromised. PDF is ideal for printing because of its page-oriented layout. Use the HTML manuals to search for topics, navigate between topics, and click links to examples, videos, reference material, and other related technical content. For information about Adobe's discontinued support of Adobe Reader on Linux platforms and your available options, refer to Knowledge Article MG596568 on SupportNet. Linux is a registered trademark of Linus Torvalds in the U.S. and other countries. * Notice of Accessibility For ModelSim, Questa SIM, and Visualizer Debug Environment products, U.S. English is the only language supported. * QSIM-75179 - voptclassic is deprecated from 2022.1 and subsequent releases. If voptclassic is used either directly or by setting environment variable QUESTA_CLASSIC_VOPT, it will produce an error, displaying a deprecation message, which can be suppressed or downgraded to a warning or a note. If suppressed, it will still produce a warning message displaying a deprecation message. Users can continue using voptclassic in 2022.1 either by suppressing or downgrading the error message. However, voptclassic is not recommended and vopt should be used instead. * QSIM-81283 - voptclassic is deprecated from 2023.1 and subsequent releases. If voptclassic is used either directly or by setting environment variable QUESTA_CLASSIC_VOPT, it will produce an un-suppressible error, displaying a deprecation message. User should use vopt instead. _______________________________________________________________________ Base Product Specifications in 2023.1 * [Supported Platforms] Linux RHEL 7 x86/x86-64 Linux RHEL 8 x86/x86-64 Linux SLES 12 x86/x86-64 Linux SLES 15 x86/x86-64 Windows 10 x86/x64 [Supported GCC Compilers (for SystemC)] gcc-7.4.0-linux/gcc-7.4.0-linux_x86_64 gcc-10.3.0-linux/gcc-10.3.0-linux_x86_64 gcc-7.4.0-mingw32vc16 gcc-7.4.0-mingw64vc16 [OVL (shipped with product)] v2.8.1 [Licensing] FLEXnet v11.16.4.0 SALT v1.6.1.0 _______________________________________________________________________ Compatibility Issues with Release 2023.1 Key Information Compatibility * QSIM-74070 - (source) Starting 2022.1 release, OSVVM and UVVM libraries are no longer shipped in Questa installation. Users needing these libraries can directly download them to compile and use with QuestaSim * [nodvtid] - (source) For protected HDL source (Verilog and VHDL), legacy ciphers (data_method) "3des-cbc", "des-cbc", "blowfish-cbc", and "cast128-cbc" are no longer supported for either encryption (in vhencrypt/vencrypt) or for decryption (in vcom/vlog). Further, encoding method (enctype) "uuencode" is no longer supported. These are all deprecated by IEEE Std. 1735-2014. For further assistance, please contact a Siemens representative. * [nodvtid] - (source, results) Starting from 2023.1 release: 1. For linux and linux_x86_64: 1. GCC 5.3.0 and GCC 4.7.4 will no longer be supported and they will no longer be distributed with the release. * For linux_aarch64: 1. GCC 5.4.0 will no longer be supported and it will no longer be distributed with the release. QSIM-75015 - (source, results) GCC changes starting 2023.1: 1. GCC 10.3.0 is now available for linux, linux_x86_64 and linux_aarch64 platforms as the SystemC/DPI/FLI/PLI/VPI default compiler 2. GCC 7.4.0 is still available for all platforms and is the SystemC/DPI/FLI/PLI/VPI default compiler for win32, win64 platforms. 3. For linux and linux_x86_64: + GCC 5.3.0 and GCC 4.7.4 have been dropped and will no longer be supported or distributed with the release 4. For linux_aarch64: + GCC 5.4.0 has been dropped and will no longer be supported or distributed with the release GDB changes starting 2023.1: 1. GDB 10.2.0 is now the only GDB version being shipped for all platforms and is what's used for the CDebug feature SystemVerilog Compatibility * QSIM-77345 - (source) Improved compile-time checks which validate the LRM compliance of the arguments specified for a class::randomize() function call. These additional checks may elicit new/additional (vlog-2934) errors at compile time. Note that specifying non-LRM compliant arguments to class::randomize() will elicit (vsim-7210) errors during simulation when the corresponding randomize() call is executed (even if no vlog-2934 error was triggered or was suppressed during compile time). * QSIM-76386 - (results) Previous versions of Questa would incorrectly seed the initial/always processes within generate blocks with the same seed. This issue has been fixed. To provide backward-compatibility (i.e. restore the previous non-LRM compliant behavior), disable the SystemVerilog constrained-random extension "geninitialseedfix" (i.e. "vsim -svrandext=-geninitialseedfix"). The "geninitialseedfix" extension is enabled by default (i.e. initial/always processes within generate blocks are seeded in an LRM-compliant fashion). * QSIM-77637 - (results) In some rare cases, randomize() would trigger a spurious failure (constraint contradiction) due to the incorrect evaluation of a 'unique' constraint. This issue has been fixed. * QSIM-77468 - (results) In some rare cases, randomize() would produce different solutions for the same testbench on different platforms (e.g. Windows vs. Linux). This issue has been fixed. * QSIM-79531 - (results) In some rare cases, randomize() would incorrectly evaluate scenarios having constraints involving real-type multiplication. This bug would effectively cause randomize() to miss generating some valid solutions. This issue has been fixed. * QSIM-78119 - (results) In some rare cases, randomize() would generate the same solution for multiple array elements of random unpacked arrays. This issue has been fixed. * QSIM-78840 - (results) In some rare cases, randomize() would incorrectly evaluate an if/else constraint having a random condition expression containing a division or modulo expression where the divisor could be zero. This issue has been fixed. * QSIM-78574 - (results) In some rare cases, a randomize() call that fails (i.e. has a return value of 0) will incorrectly modify the value of one or more random variables. This issue has been fixed. * QSIM-78567 - (results) In some rare cases, randomize() would incorrectly evaluate a satisfiable equality constraint as unsatisfiable, causing a spurious randomize failure. This issue has been fixed. * QSIM-76384 - (results) Major changes were made to the underlying implementation related to randomization of 'randc' variables. As a result, the statistical randomness of randomize() solutions for 'randc' variables has been significantly improved. * QSIM-80957 - (results) During a call to randomize(), constraint expressions involving the builtin function call associatve_array::exists() would force all of the elements of a random associative array to be solved prior to executing the exists() function, which could result in spurious randomize() errors. This behavior has been changed such that the exists() function can be executed before any of the elements of the random associative array have been solved, avoiding the related spurious errors observed with the prior behavior. * QSIM-80759 - (results) Calls to $urandom and $urandom_range that were made from SystemVerilog functions that were executed via DPI "out-of-the-blue" calls (when "-dpioutoftheblue 1" is specified on the vsim command line) would generate the same results for different SvSeed values (specified via "-sv_seed" vsim option). This issue has been fixed. * QSIM-80301 - (results) In some rare cases, randomize() would incorrectly evaluate (or trigger a spurious failure) for a constraint involving an array.sum() reduction function on array of 1-bit elements. This issue has been fixed. * QSIM-79826 - (results) In some cases, randomize() would incorrectly reverse the order of elements for an unpacked array argument when executing a function call specified within the context of a constraint. This issue has been fixed. * QSIM-79148 - (results) Aliased $stack to $stacktrace for ease of VCS compatiblity * QSIM-78955 - (results) Significant improvements have been made to the -solvefaildebug constraint contradiction report generated when randomize() fails due to unsatisfiable constraint(s). The report now filters out more of the unrelated random variables and constraints (reducing noise), and the "Where" section of the output has been reorganized in a hierarchical fashion (significantly improving readability). * QSIM-77629 - (results) The vsim SystemVerilog constrained-random language extension "randcext" (-svrandext=randcext) is now enabled by default. This extension allows 'randc' and other 'rand' variables to be solved in simultaneously in the same randset. VHDL Compatibility * QSIM-75569 - (source, results) for JIRA 75569 Process(ALL) - A VHDL 2008 language construct supported under -2008 switch , will be supported under -permissive flag as well - Questa will however issue a warning like : "** Warning: src/test1.vhd(47): (vcom-1441) Process(ALL) is not defined for this version of the language." * [nodvtid] - (source, results) vsim-86 suppressible error is now downgraded to vsim-86 suppressible warning. * QSIM-80910 - (results) A boolean operation on std_logic_vector or std_ulogic_vector had one operator that is compiled 2008 and another operand compiled as not 2008, an internal error would be thrown. This has been resolved but in doing so, some usages of to_signed/to_unsigned function will not report assertion warnings at simulation time instead of being silent. User Interface Compatibility * QSIM-76675 - (source) The vsim SystemVerilog constrained-random extension "pathseed" (e.g. "vsim -svrandext=+pathseed") has been deprecated and is replaced by the compile-time (vlog/vopt) SystemVerilog extension "pathseed" (e.g. "vlog -svext=+pathseed"). This change has been made to facilitate optimizations that are performed by vopt that are dependent on the state of this extension. * QSIM-77773 - (source) The deprecated vsim SystemVerilog constrained-random extension "pathseed" (-svrandext=pathseed) has been disabled/removed. Any attempt to use this will trigger a (vsim-12458) error. Note that this extension was replaced by the vopt "pathseed" extension (-svext=pathseed). * QSIM-80968 - (results) "write report -capacity" is now deprecated, and "capstats" can be used instead. Command mapping: + write report -capacity => capstats -decl + -l => -du+details -decl + -s => -du+details -decl + -line => -line -decl + [filename] => -filename [filename] + [-qdas | -assertions | -classes | -cvg | -solver | -vmem] => -decl _______________________________________________________________________ SystemVerilog Defects Repaired in 2023.1 * [nodvtid] - vlog -E output fixed for toggle coverage directive * QSIM-76986 - In some rare cases, randomize() would fail with a BDD-engine error (SolveGraphMaxSize or SolveGraphMaxEval exceeded) even when Questa is invoked with default solve-engine configuration options (i.e. when "-solveengine auto" is specified). This issue has been fixed. * QSIM-76940 - In some rare cases, randomize() would issue a spurious (vsim-7140) error "Illegal binary operation '==' on unpacked type in constraint" for constraint expressions involving non-random strings and/or string literals. This issue has been fixed. * QSIM-76386 - (results) Previous versions of Questa would incorrectly seed the initial/always processes within generate blocks with the same seed. This issue has been fixed. To provide backward-compatibility (i.e. restore the previous non-LRM compliant behavior), disable the SystemVerilog constrained-random extension "geninitialseedfix" (i.e. "vsim -svrandext=-geninitialseedfix"). The "geninitialseedfix" extension is enabled by default (i.e. initial/always processes within generate blocks are seeded in an LRM-compliant fashion). * QSIM-76144 - In some rare cases, randomize() would cause vsim to crash when evaluating scenarios involving extremely large random arrays. This issue has been fixed. * QSIM-76913 - In some rare cases, randomize() would cause vsim to crash when evaluating a scenario involving variables that are being logged (wlf/qwavedb). This issue has been fixed. * QSIM-76207 - When randomize() fails due to a constraint contradiction and -solvefailtestcase enabled, the generated testcase would sometimes be missing enumerated type declarations for enumerated type values that are referred to by the generated constraint expressions. This issue has been fixed. * QSIM-75174 - Questa would issue a (vsim-7134) "Array index value greater than 32 bits not supported" error when evaluating a randomize() call involving an indexed constraint expression having a resolved type > 32 bits wide, even when the value of the index is within the bounds of the associated array/vector (e.g. "myarray[index64] == 123" where "index64" is a 64-bit variable equal to 0). Error handling for these kinds of cases has been improved -- a (vsim-7134) error will now only be issued if the value of the index is greater than or equal to 2^31. * QSIM-76198 - Vsim would sometimes generate a bad pointer error during elaboration in designs using virtual interrface types. * [nodvtid] - Certain SystemVerilog static class references to forward declarations within the same scope failed to compile. * QSIM-77637 - (results) In some rare cases, randomize() would trigger a spurious failure (constraint contradiction) due to the incorrect evaluation of a 'unique' constraint. This issue has been fixed. * QSIM-77519 - In some rare cases, randomize() would trigger a fatal internal error when evaluating scenarios involving random dynamic arrays. This issue has been fixed. * QSIM-77468 - (results) In some rare cases, randomize() would produce different solutions for the same testbench on different platforms (e.g. Windows vs. Linux). This issue has been fixed. * QSIM-77791 - Simulations would sometimes run very slowly (>10x slower) when solver profiling is enabled with randset details (e.g. "vsim -fprofile+solver -solverfprof=+randsets"). This issue has been fixed. * QSIM-77345 - (source) Improved compile-time checks which validate the LRM compliance of the arguments specified for a class::randomize() function call. These additional checks may elicit new/additional (vlog-2934) errors at compile time. Note that specifying non-LRM compliant arguments to class::randomize() will elicit (vsim-7210) errors during simulation when the corresponding randomize() call is executed (even if no vlog-2934 error was triggered or was suppressed during compile time). * QSIM-78794 - Vopt would sometimes generate this error when using localparams in a parameterized class: ** Error: test.sv(16): Questa has encountered an unexpected internal error: ../../src/vlog/vgentd.c(6724). Please contact Questa support at http://supportnet.mentor.com/ * QSIM-79531 - (results) In some rare cases, randomize() would incorrectly evaluate scenarios having constraints involving real-type multiplication. This bug would effectively cause randomize() to miss generating some valid solutions. This issue has been fixed. * QSIM-78119 - (results) In some rare cases, randomize() would generate the same solution for multiple array elements of random unpacked arrays. This issue has been fixed. * QSIM-78840 - (results) In some rare cases, randomize() would incorrectly evaluate an if/else constraint having a random condition expression containing a division or modulo expression where the divisor could be zero. This issue has been fixed. * QSIM-78574 - (results) In some rare cases, a randomize() call that fails (i.e. has a return value of 0) will incorrectly modify the value of one or more random variables. This issue has been fixed. * QSIM-78567 - (results) In some rare cases, randomize() would incorrectly evaluate a satisfiable equality constraint as unsatisfiable, causing a spurious randomize failure. This issue has been fixed. * [nodvtid] - The -dp_dump_systask_filenames switch reported null entries. * QSIM-76384 - (results) Major changes were made to the underlying implementation related to randomization of 'randc' variables. As a result, the statistical randomness of randomize() solutions for 'randc' variables has been significantly improved. * QSIM-80957 - (results) During a call to randomize(), constraint expressions involving the builtin function call associatve_array::exists() would force all of the elements of a random associative array to be solved prior to executing the exists() function, which could result in spurious randomize() errors. This behavior has been changed such that the exists() function can be executed before any of the elements of the random associative array have been solved, avoiding the related spurious errors observed with the prior behavior. * QSIM-80759 - (results) Calls to $urandom and $urandom_range that were made from SystemVerilog functions that were executed via DPI "out-of-the-blue" calls (when "-dpioutoftheblue 1" is specified on the vsim command line) would generate the same results for different SvSeed values (specified via "-sv_seed" vsim option). This issue has been fixed. * QSIM-80522 - In some rare cases, randomize() would cause vsim to crash. This issue has been fixed. * QSIM-80301 - (results) In some rare cases, randomize() would incorrectly evaluate (or trigger a spurious failure) for a constraint involving an array.sum() reduction function on array of 1-bit elements. This issue has been fixed. * QSIM-79826 - (results) In some cases, randomize() would incorrectly reverse the order of elements for an unpacked array argument when executing a function call specified within the context of a constraint. This issue has been fixed. * QSIM-79751 - Previously, (vopt-2924) warnings (Non-LRM compliant use of 'randc' variable in 'dist' constraint) were generated only for 'dist' constraints where the LHS is a simple reference to a 'randc' variable. These warnings have been extended to 'dist' constraints where the LHS is a complex expression containing one or more references to a 'randc' variables. * QSIM-77749 - In some rare cases involving constraints with references to virtual interfaces, randomize() would trigger an internal error when -solverecord is enabled on the vsim command line. This issue has been fixed. * [nodvtid] - In some rare cases, a randomize() call would trigger an internal error (in slvBDDIntlSet.c) when evaluating a randset with the BDD solve engine. This issue has been fixed. _______________________________________________________________________ VHDL Defects Repaired in 2023.1 * QSIM-76328 - Attribute expression like : mysignal(i)'length do not actually require the indexing of mysignal to occur. Vcom would do a index constraint check if i was know at vcom or vopt time and issue an error. At simulation time the check was not done so the tool was inconsistent. We have downgrade the vcom/vopt check to just a warning. * QSIM-76493 - Designs using direct instantiation could fail during the first pass of -autoorder. Prior to 2022.1 the failure would only occur if the referenced entity was not previously compiled or scanned prior to the direct instantiation. Starting in 2022.1 it would always fail. --autoorder has been fixed so that the presence of the entity is not need for the initial scan. * QSIM-75328 - In vopt, if an formal generic had a constrained array subtype, vopt would us the acutal expression's index constrains instead of the formal when evaluating expression referencing the formal generic. This could produce cases where generate would either not be evaluated by vopt or evaluated incorrectly. It could also cause dependent generic expression to produce incorrect results. This fix now use the formal generic's index constraint. * QSIM-76545 - Similar problem that was fixed for QSIM-75328. Incorrect index constraints would be applied in vopt to formal generic that had a index constrains explicitly associated with it. * QSIM-77525 - When the PathSeparator or SignalSpyPathSeparator is set to '.' there would be problems resolving record fields of VHDL signals. A change has been made to the name resolution routines to correctly determine if '.' is a field separator or a hierarchical path separator and take appropriate action. * QSIM-74586 - For some specific cases of case expressions where generic is used, we use to give incorrect error vopt-1014 error. This has been fixed. * QSIM-77337 - When a package is instantiated as a generic package in the generic clause of an entity and the formal instance name of that package is used in the port clause of the same entity to access a user-defined vector type then a fatal error is obtained. This has been fixed now. * QSIM-75963 - When reporting values inside procedures in certain situation, the values reported were incorrect. This has been fixed. * QSIM-78076 - In certain situations while doing concat operations, VOPT used to give internal error. This has been fixed. * QSIM-77949 - In certain situations, tick_last_value was not properly getting updated for some VHDL signals in mixed language boundary. This has been fixed. * QSIM-77008 - In certain situations tick_high attribute when used on time values was giving vopt error. This has been fixed. * QSIM-79144 - VHDL 2008 generic packages that contain deferred constant of an array or a record type could generate incorrect results. * QSIM-79470 - When using 2008 VHDL if-elsif-else generate, null range errors could be reported on branches that may not be used during elaboration. Checks now correct determine if a branch may or maynot be used. If the branch will not be used no warning or error is issued. If a branch may be used a warning is issued. If a branch will be used and error is reported. * QSIM-78602 - LAST_EVENT attribute was not functioning correctly in certain situation inside VHDL clocked process. This has been fixed. * QSIM-79905 - In some cases vopt would compute the results of comparing two one-dimensional array of arrays and generate and incorrect result. This has been fixed. * QSIM-80134 - If a generic package contains a protected type and the protected type contains type declarations, simulation could crash. Moving the type declarations from within the protected type will work around the issue. * QSIM-77753 - When doing auto order on a large number of files, the second pass could trigger a crash. Changes have been made so the crash no longer occurs. * QSIM-80348 - If a constant is declared within a subprogram and is initialized with an expression that calls a nested subprogram. If the call to the subprogram is an operand to an binary operator. incorrect optimization could occur that results in a crash. * QSIM-80456 - A multi-dimensional array of std_logic could crash during simulation if it is a port whose actual connection is a slice or index expression, the port is of mode out or inout and the signal assignment has a delay. * [nodvtid] - Error messages 1594 and 1595, given error about using a function prior to its elaboration, have been enhanced to report the location of the usage of the function along with the declaration location of the function. * QSIM-80785 - If a configuration adds a new library clause not present in the architecture being configured, and objects from this library are used in a generic map or port map. If named association is used or expressions other than object or index express, a vopt-1136 error, unknown identifier could occur. * QSIM-80910 - (results) A boolean operation on std_logic_vector or std_ulogic_vector had one operator that is compiled 2008 and another operand compiled as not 2008, an internal error would be thrown. This has been resolved but in doing so, some usages of to_signed/to_unsigned function will not report assertion warnings at simulation time instead of being silent. * QSIM-80977 - If direct instantiation occurred in a architecture and the port map or generic map referenced locally declared constants, incorrect values could be used. This could result incorrect vopt errors or incorrect simulation results. * QSIM-80880 - Use of the VHDL 2008's unaffected keyword could trigger a crash in vopt. This has been resolved. * QSIM-79977 - When a vector's range is defined by range attribute on an unconstrained type port in certain situation, an incorrect fatal error is obtained for matching array lengths. This has been fixed. * QSIM-81246 - If a VHDL expression is large and reuses the same object repeatedly, vopt time could be so long as to appear to be hung. The analysis of such expressions has been modified to no longer have this issue. _______________________________________________________________________ SystemC Defects Repaired in 2023.1 * QSIM-65914 - Allow unconnected bits on SC-SV boundaries by: + Change error vsim-3685 to be suppressible. When doing so the unconnected bits will take on their default value. + If the user passed "-svext=dmsbw" to vopt, the error will be downgraded to a warning and the extra bits will be forced to Zero values. _______________________________________________________________________ Qwave logging Defects Repaired in 2023.1 * QSIM-76677 - Changes to dynamic arrays, queues, and associative arrays that occur during SystemVerilog randomize() calls were not being logged. This issue has been fixed. _______________________________________________________________________ User Interface Enhancements in 2023.1 * QSIM-76675 - (source) The vsim SystemVerilog constrained-random extension "pathseed" (e.g. "vsim -svrandext=+pathseed") has been deprecated and is replaced by the compile-time (vlog/vopt) SystemVerilog extension "pathseed" (e.g. "vlog -svext=+pathseed"). This change has been made to facilitate optimizations that are performed by vopt that are dependent on the state of this extension. * QSIM-80782 - The vsim command line arg -capacity is not allowed with -fprofile * QSIM-77773 - (source) The deprecated vsim SystemVerilog constrained-random extension "pathseed" (-svrandext=pathseed) has been disabled/removed. Any attempt to use this will trigger a (vsim-12458) error. Note that this extension was replaced by the vopt "pathseed" extension (-svext=pathseed). * QSIM-80968 - (results) "write report -capacity" is now deprecated, and "capstats" can be used instead. Command mapping: + write report -capacity => capstats -decl + -l => -du+details -decl + -s => -du+details -decl + -line => -line -decl + [filename] => -filename [filename] + [-qdas | -assertions | -classes | -cvg | -solver | -vmem] => -decl _______________________________________________________________________ SystemVerilog Enhancements in 2023.1 * QSIM-75460 - Added support for non-LRM compliant system task "$srandom" via the SystemVerilog constrained-random extension "srandom" (vsim -svrandext=srandom). When this extension is disabled, "$srandom" is interpreted as a user-defined PLI system task; if no user-defined PLI for "$srandom" is found, an error will be issued during elaboration. When this extension is enabled, any occurrence of "$srandom(seed)" will be evaluated as "process::self().srandom(seed)". Specifying "vsim -pedantic_errors" disables the "srandom" extension (even if it is enabled via -svrandext=+srandom). This extension is enabled by default. * QSIM-75519 - Questa now supports indexed part-select expressions with random base expressions in constraints when the SystemVerilog constrained-random extension "randindex" is enabled (vsim -svrandext=randindex). Note: this extension is enabled by default. * QSIM-75287 - The default values for the following modelsim.ini [vsim] variables related to randomize() have been increased: + SolveArrayResizeMax: default = 65535 (previously 10000) + SolveArrayResizeWarn: default = 65535 (previously 10000) * [nodvtid] - Default initializers may be used within ternary expressions and bit-wise logical-OR operators in certain circumstances * QSIM-75459 - Falcon Solver Profiler enhancements: + Save pre-formatted solver profile report to file + After loading an FDB containing solver profile data in Visualizer, the context menu for the solver profile session node (Solver performance profiler) contains a "Solver profile report..." menu item. Selecting this menu item will popup a file dialog window. The pre-formatted solver profile report will be saved to the specified target file. * Save testcase for Randset to file * Use "vsim -fprofile+solver -solverfprof=+randsets,+testgen" to instruct the Falcon solver profiler to store testcase data for profiled randsets. * After loading an FDB containing solver profile data in Visualizer which was generated with "-solverfprof=+randsets,+testgen", the context menu for items of the "Randsets" panel contains a "Save testcase..." menu item. Selecting this menu item will popup a file dialog window. The testcase(s) for the selected randset(s) will be saved to the specified target file. QSIM-79148 - (results) Aliased $stack to $stacktrace for ease of VCS compatiblity QSIM-78955 - (results) Significant improvements have been made to the -solvefaildebug constraint contradiction report generated when randomize() fails due to unsatisfiable constraint(s). The report now filters out more of the unrelated random variables and constraints (reducing noise), and the "Where" section of the output has been reorganized in a hierarchical fashion (significantly improving readability). QSIM-77629 - (results) The vsim SystemVerilog constrained-random language extension "randcext" (-svrandext=randcext) is now enabled by default. This extension allows 'randc' and other 'rand' variables to be solved in simultaneously in the same randset. [nodvtid] - Added new option "-writealltoplevels " that records the names of all top level modules and compilation units (including the one specified with -cuname) in a specified file. This option allows seamless flow when CU packages need to be explicitly specified as vopt top levels (in response to vlog-2650 messages). _______________________________________________________________________ VHDL Enhancements in 2023.1 * QSIM-75569 - (source, results) for JIRA 75569 Process(ALL) - A VHDL 2008 language construct supported under -2008 switch , will be supported under -permissive flag as well - Questa will however issue a warning like : "** Warning: src/test1.vhd(47): (vcom-1441) Process(ALL) is not defined for this version of the language." * [nodvtid] - (source, results) vsim-86 suppressible error is now downgraded to vsim-86 suppressible warning. _______________________________________________________________________ Power Aware Enhancements in 2023.1 * QSIM-76854 - + Flathiertestplan is a new flavor of testplan added in PA. This testplan has been added under option "-pa_enable=flathiertestplan". + This testplan will have separate groups for all the control signals and PST (Power state Table) present in the entire UPF/Design. + Below are the groups over which user can navigate. o Power Domain Simstate o Control Signals o Supply set o Power Switch o Power State Table o Power State Group o Composite Domain o Port and Net o Strategy Simstate o Power Domain States _______________________________________________________________________ Document Revision History in 2023.1 * Revision - Changes - Status/Date 8.0 - Modifications to improve the readability and comprehension of the content. Approved by Tim Peeke. All technical enhancements, changes, and fixes are listed in this document for all products in this release. Approved by Bryan Ramirez. - Released/January 2023 * Author: In-house procedures and working practices require multiple authors for documents. All associated authors for each topic within this document are tracked within the document source. * Revision History: Released documents maintain a revision history of up to four revisions. For earlier revision history, refer to earlier releases of documentation which are available on Support Center (http://support.mentor.com).