ed_synth_emif_ph2_0

2024.03.14.10:22:51 Datasheet
Overview

Memory Map
  emif_ph2_inst
t0_axilnoc 
t0_axi4noc 

emif_ph2_inst

emif_ph2 v6.1.0


Parameters

MEM_TECHNOLOGY_AUTO_BOOL true
MEM_TECHNOLOGY_AUTO MEM_TECHNOLOGY_DDR5
MEM_FORMAT MEM_FORMAT_DISCRETE
MEM_TOPOLOGY MEM_TOPOLOGY_FLYBY
MEM_NUM_RANKS 1
MEM_NUM_CHANNELS 1
MEM_DEVICE_DQ_WIDTH 16
MEM_COMPS_PER_RANK 2
MEM_AC_MIRRORING_AUTO_BOOL true
MEM_AC_MIRRORING_AUTO false
PHY_NOC_EN_AUTO_BOOL true
PHY_NOC_EN_AUTO true
CTRL_ECC_MODE_AUTO_BOOL true
CTRL_ECC_MODE_AUTO CTRL_ECC_MODE_DISABLED
MEM_TOTAL_DQ_WIDTH 32
PHY_AC_PLACEMENT_AUTO_BOOL true
PHY_AC_PLACEMENT_AUTO PHY_AC_PLACEMENT_AUTO
PHY_MEMCLK_FREQ_MHZ_AUTO_BOOL true
PHY_MEMCLK_FREQ_MHZ_AUTO 2200.0
MEM_PRESET_FILE_EN true
MEM_PRESET_FILE_QPRS /nfs/png/disks/psg_board_1/annagu/FP82/qii24.1b107/bts_ddr5_x32_4400_hydra16_long/ddr5_5600_bin_4400.qprs
MEM_PRESET_ID_AUTO_BOOL true
MEM_PRESET_ID_AUTO Custom Preset
PHY_REFCLK_FREQ_MHZ_AUTO_BOOL false
PHY_REFCLK_FREQ_MHZ 100.0
PHY_IO_VOLTAGE 1.1
GRP_PHY_AC_AUTO_BOOL true
GRP_PHY_AC_X_R_S_AC_OUTPUT_OHM_AUTO RTT_PHY_OUT_34_CAL
GRP_PHY_CLK_AUTO_BOOL true
GRP_PHY_CLK_X_R_S_CK_OUTPUT_OHM_AUTO RTT_PHY_OUT_34_CAL
GRP_PHY_DATA_AUTO_BOOL true
GRP_PHY_DATA_X_DQ_IO_STD_TYPE_AUTO PHY_IO_STD_TYPE_POD
GRP_PHY_DATA_X_R_S_DQ_OUTPUT_OHM_AUTO RTT_PHY_OUT_34_CAL
GRP_PHY_DATA_X_DQ_SLEW_RATE_AUTO PHY_SLEW_RATE_FASTEST
GRP_PHY_DATA_X_R_T_DQ_INPUT_OHM_AUTO RTT_PHY_IN_50_CAL
GRP_PHY_DATA_X_DQ_VREF_AUTO 71.82
GRP_PHY_IN_AUTO_BOOL true
GRP_PHY_IN_X_R_T_REFCLK_INPUT_OHM_AUTO LVDS_DIFF_TERM_ON
GRP_PHY_DFE_AUTO_BOOL true
GRP_PHY_DFE_X_TAP_1_AUTO PHY_DFE_TAP_1_DDR5_1
GRP_PHY_DFE_X_TAP_2_AUTO PHY_DFE_TAP_2_3_DDR5_n1
GRP_PHY_DFE_X_TAP_3_AUTO PHY_DFE_TAP_2_3_DDR5_0
GRP_PHY_DFE_X_TAP_4_AUTO PHY_DFE_TAP_4_DDR5_0
GRP_MEM_ODT_DQ_AUTO_BOOL true
GRP_MEM_ODT_DQ_X_TGT_WR_AUTO MEM_RTT_COMM_1
GRP_MEM_ODT_DQ_X_RON_AUTO MEM_DRIVE_STRENGTH_7
GRP_MEM_DQ_VREF_AUTO_BOOL true
GRP_MEM_DQ_VREF_X_VALUE_AUTO 74.5
GRP_MEM_ODT_CA_AUTO_BOOL false
GRP_MEM_ODT_CA_X_CA MEM_RTT_CA_DDR5_6
GRP_MEM_ODT_CA_X_CS MEM_RTT_CA_DDR5_6
GRP_MEM_ODT_CA_X_CK MEM_RTT_CA_DDR5_6
GRP_MEM_VREF_CA_AUTO_BOOL false
GRP_MEM_VREF_CA_X_CA_VALUE 75.0
GRP_MEM_VREF_CA_X_CS_VALUE 75.0
GRP_MEM_DFE_AUTO_BOOL true
GRP_MEM_DFE_X_TAP_1_AUTO MEM_DFE_TAP_1_n45
GRP_MEM_DFE_X_TAP_2_AUTO MEM_DFE_TAP_2_n15
GRP_MEM_DFE_X_TAP_3_AUTO MEM_DFE_TAP_3_n5
GRP_MEM_DFE_X_TAP_4_AUTO MEM_DFE_TAP_4_0
USER_EXTRA_PARAMETERS BYTE_SWIZZLE_CH0=1,0,X,X,2,3,X,X; PIN_SWIZZLE_CH0_DQS1=9,11,13,15,10,8,14,12; PIN_SWIZZLE_CH0_DQS0=1,7,3,5,6,4,0,2; PIN_SWIZZLE_CH0_DQS2=17,23,19,21,18,22,16,20; PIN_SWIZZLE_CH0_DQS3=25,31,29,27,26,30,28,24;
DEBUG_TOOLS_EN false
AXI_SIDEBAND_ACCESS_MODE_AUTO_BOOL true
AXI_SIDEBAND_ACCESS_MODE_AUTO NOC
INSTANCE_ID 0
EX_DESIGN_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GEN_SYNTH true
EX_DESIGN_GEN_SIM false
EX_DESIGN_CORE_CLK_FREQ_MHZ_AUTO_BOOL true
EX_DESIGN_CORE_CLK_FREQ_MHZ_AUTO 495
EX_DESIGN_CORE_REFCLK_FREQ_MHZ 100
EX_DESIGN_NOC_REFCLK_FREQ_MHZ_AUTO_BOOL true
EX_DESIGN_NOC_REFCLK_FREQ_MHZ_AUTO 100
EX_DESIGN_HYDRA_REMOTE CONFIG_INTF_MODE_REMOTE_JTAG
EX_DESIGN_PMON_ENABLED true
EX_DESIGN_HYDRA_PROG emif_tg_emulation_long
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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