MEM_TECHNOLOGY_AUTO_BOOL |
false |
MEM_TECHNOLOGY |
MEM_TECHNOLOGY_LPDDR5 |
MEM_FORMAT |
MEM_FORMAT_DISCRETE |
MEM_TOPOLOGY |
MEM_TOPOLOGY_FLYBY |
MEM_NUM_RANKS |
1 |
MEM_NUM_CHANNELS |
2 |
MEM_DEVICE_DQ_WIDTH |
16 |
MEM_COMPS_PER_RANK |
1 |
MEM_AC_MIRRORING_AUTO_BOOL |
true |
MEM_AC_MIRRORING_AUTO |
false |
PHY_FSP1_EN |
false |
PHY_NOC_EN_AUTO_BOOL |
true |
PHY_NOC_EN_AUTO |
true |
CTRL_ECC_MODE_AUTO_BOOL |
true |
CTRL_ECC_MODE_AUTO |
CTRL_ECC_MODE_DISABLED |
MEM_TOTAL_DQ_WIDTH |
32 |
PHY_AC_PLACEMENT_AUTO_BOOL |
true |
PHY_AC_PLACEMENT_AUTO |
PHY_AC_PLACEMENT_FULL |
PHY_MEMCLK_FSP0_FREQ_MHZ_AUTO_BOOL |
true |
PHY_MEMCLK_FSP0_FREQ_MHZ_AUTO |
2750.0 |
MEM_PRESET_FILE_EN_FSP0 |
true |
MEM_PRESET_FILE_QPRS_FSP0 |
/nfs/png/disks/psg_board_1/annagu/FP82/qii24.1b107/bts_lpddr5_5500/lpddr5_6400bin_5500.qprs |
MEM_PRESET_ID_FSP0_AUTO_BOOL |
true |
MEM_PRESET_ID_FSP0_AUTO |
Custom Preset |
PHY_REFCLK_FREQ_MHZ_AUTO_BOOL |
false |
PHY_REFCLK_FREQ_MHZ |
100.0 |
PHY_IO_VOLTAGE |
0.7 |
GRP_PHY_AC_AUTO_BOOL |
true |
GRP_PHY_AC_X_R_S_AC_OUTPUT_OHM_AUTO |
RTT_PHY_OUT_40_CAL |
GRP_PHY_CLK_AUTO_BOOL |
true |
GRP_PHY_CLK_X_R_S_CK_OUTPUT_OHM_AUTO |
RTT_PHY_OUT_40_CAL |
GRP_PHY_DATA_AUTO_BOOL |
true |
GRP_PHY_DATA_X_DQ_IO_STD_TYPE_AUTO |
PHY_IO_STD_TYPE_LVSTL |
GRP_PHY_DATA_X_R_S_DQ_OUTPUT_OHM_AUTO |
RTT_PHY_OUT_40_CAL |
GRP_PHY_DATA_X_DQ_SLEW_RATE_AUTO |
PHY_SLEW_RATE_FASTEST |
GRP_PHY_DATA_X_R_T_DQ_INPUT_OHM_AUTO |
RTT_PHY_IN_40_CAL |
GRP_PHY_DATA_X_DQ_VREF_AUTO |
14.67 |
GRP_PHY_IN_AUTO_BOOL |
true |
GRP_PHY_IN_X_R_T_REFCLK_INPUT_OHM_AUTO |
LVDS_DIFF_TERM_ON |
GRP_PHY_DFE_AUTO_BOOL |
true |
GRP_PHY_DFE_X_TAP_1_AUTO |
PHY_DFE_TAP_1_LP5_0 |
GRP_PHY_DFE_X_TAP_2_AUTO |
PHY_DFE_TAP_2_3_LP5_0 |
GRP_PHY_DFE_X_TAP_3_AUTO |
PHY_DFE_TAP_2_3_LP5_0 |
GRP_PHY_DFE_X_TAP_4_AUTO |
PHY_DFE_TAP_4_LP5_0 |
GRP_MEM_ODT_DQ_AUTO_BOOL |
true |
GRP_MEM_ODT_DQ_X_TGT_WR_AUTO |
MEM_RTT_COMM_6 |
GRP_MEM_ODT_DQ_X_RON_AUTO |
MEM_DRIVE_STRENGTH_6 |
GRP_MEM_ODT_DQ_X_WCK_AUTO |
MEM_RTT_COMM_4 |
GRP_MEM_DQ_VREF_AUTO_BOOL |
true |
GRP_MEM_DQ_VREF_X_VALUE_AUTO |
24.0 |
GRP_MEM_ODT_CA_AUTO_BOOL |
true |
GRP_MEM_ODT_CA_X_CA_COMM_AUTO |
MEM_RTT_COMM_4 |
GRP_MEM_ODT_CA_X_CA_ENABLE_AUTO |
MEM_RTT_COMM_EN_TRUE |
GRP_MEM_ODT_CA_X_CS_ENABLE_AUTO |
MEM_RTT_COMM_EN_TRUE |
GRP_MEM_ODT_CA_X_CK_ENABLE_AUTO |
MEM_RTT_COMM_EN_FALSE |
GRP_MEM_VREF_CA_AUTO_BOOL |
true |
GRP_MEM_VREF_CA_X_CA_VALUE_AUTO |
50.0 |
GRP_MEM_DFE_AUTO_BOOL |
true |
GRP_MEM_DFE_X_TAP_1_AUTO |
MEM_DFE_TAP_1_LP5_OFF |
USER_EXTRA_PARAMETERS |
BYTE_SWIZZLE_CH0=1,0,X,X,X,X,X,X; PIN_SWIZZLE_CH0_DQS1=9,11,8,10,13,15,14,12; PIN_SWIZZLE_CH0_DQS0=6,7,4,5,0,3,2,1; BYTE_SWIZZLE_CH1= X,X,X,X,X,X,1,0; PIN_SWIZZLE_CH1_DQS1=15,8,10,9,11,13,12,14; PIN_SWIZZLE_CH1_DQS0=7,6,4,5,3,2,1,0; |
DEBUG_TOOLS_EN |
false |
AXI_SIDEBAND_ACCESS_MODE_AUTO_BOOL |
true |
AXI_SIDEBAND_ACCESS_MODE_AUTO |
NOC |
INSTANCE_ID |
0 |
EX_DESIGN_HDL_FORMAT |
HDL_FORMAT_VERILOG |
EX_DESIGN_GEN_SYNTH |
true |
EX_DESIGN_GEN_SIM |
false |
EX_DESIGN_CORE_CLK_FREQ_MHZ_AUTO_BOOL |
true |
EX_DESIGN_CORE_CLK_FREQ_MHZ_AUTO |
495 |
EX_DESIGN_CORE_REFCLK_FREQ_MHZ |
100 |
EX_DESIGN_NOC_REFCLK_FREQ_MHZ_AUTO_BOOL |
true |
EX_DESIGN_NOC_REFCLK_FREQ_MHZ_AUTO |
100 |
EX_DESIGN_HYDRA_REMOTE |
CONFIG_INTF_MODE_REMOTE_JTAG |
EX_DESIGN_PMON_ENABLED |
true |
EX_DESIGN_HYDRA_PROG |
emif_tg_emulation |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |