ed_synth_perf_monch0

2024.03.14.10:22:26 Datasheet
Overview

Memory Map
perf_monch0 perf_monch0_axi4l_bridge perf_monch0_pmon_jamb perf_monch0_unit_monitor_0
 src_axi4  m0  master  src_axi4
  perf_monch0
sink_axi4 
  perf_monch0_axi4l_bridge
s0  0x0000_0000 - 0x000f_ffff
  perf_monch0_global_monitor
csr_apb3  0x0000_0000 - 0x0000_00ff 0x0000_0000 - 0x0000_00ff
  perf_monch0_unit_monitor_0
csr_apb3  0x0000_0100 - 0x0000_01ff 0x0000_0100 - 0x0000_01ff
sink_axi4 

perf_monch0

pmon v1.0.0


Parameters

EXPORT_JTAG true
MONITOR_0_UNIT_ID 0
MONITOR_0_MEM_AXI4_ARADDR_WIDTH 44
MONITOR_0_MEM_AXI4_AWADDR_WIDTH 44
MONITOR_0_MEM_AXI4_USE_ARUSER true
MONITOR_0_MEM_AXI4_ARUSER_WIDTH 1
MONITOR_0_MEM_AXI4_USE_ARLOCK true
MONITOR_0_MEM_AXI4_USE_ARCACHE true
MONITOR_0_MEM_AXI4_USE_ARQOS true
MONITOR_0_MEM_AXI4_USE_ARREGION false
MONITOR_0_MEM_AXI4_USE_AWUSER true
MONITOR_0_MEM_AXI4_AWUSER_WIDTH 1
MONITOR_0_MEM_AXI4_USE_AWLOCK true
MONITOR_0_MEM_AXI4_USE_AWCACHE true
MONITOR_0_MEM_AXI4_USE_AWQOS true
MONITOR_0_MEM_AXI4_USE_AWREGION false
MONITOR_0_MEM_AXI4_ARID_WIDTH 7
MONITOR_0_MEM_AXI4_AWID_WIDTH 7
MONITOR_0_MEM_AXI4_RDATA_WIDTH 256
MONITOR_0_MEM_AXI4_WDATA_WIDTH 256
MONITOR_0_MEM_AXI4_USE_BUSER true
MONITOR_0_MEM_AXI4_BUSER_WIDTH 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

perf_monch0_clk_bridge

altera_clock_bridge v19.2.0


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

perf_monch0_reset_bridge

altera_reset_bridge v19.2.0


Parameters

ACTIVE_LOW_RESET 1
SYNCHRONOUS_EDGES none
O_SYNCHRONOUS_EDGES none
NUM_RESET_OUTPUTS 1
USE_RESET_REQUEST 0
SYNC_RESET 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

perf_monch0_csr_clk_bridge

altera_clock_bridge v19.2.0


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

perf_monch0_csr_reset_controller

hydra_reset_controller v1.0.0
perf_monch0_csr_clk_bridge out_clk   perf_monch0_csr_reset_controller
  clk
out_reset_3   perf_monch0_pmon_jamb
  clk_reset
out_reset_0   perf_monch0_axi4l_bridge
  clk_reset
out_reset_1   perf_monch0_global_monitor
  reset_n
out_reset_1  
  csr_apb3_reset_n
out_reset_2   perf_monch0_unit_monitor_0
  csr_apb3_reset_n


Parameters

USE_IOPLL_LOCKED false
NUM_RESET_INPUTS 1
NUM_RESET_OUTPUTS 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

perf_monch0_axi4l_bridge

altera_axi_bridge v19.4.0
perf_monch0_pmon_jamb master   perf_monch0_axi4l_bridge
  s0
perf_monch0_csr_clk_bridge out_clk  
  clk
perf_monch0_csr_reset_controller out_reset_0  
  clk_reset
m0   perf_monch0_global_monitor
  csr_apb3
m0   perf_monch0_unit_monitor_0
  csr_apb3


Parameters

USE_M0_AWID 0
USE_M0_AWREGION 0
USE_M0_AWLEN 0
USE_M0_AWSIZE 0
USE_M0_AWBURST 0
USE_M0_AWLOCK 0
USE_M0_AWCACHE 0
USE_M0_AWQOS 0
USE_S0_AWREGION 0
USE_S0_AWLOCK 0
USE_S0_AWCACHE 0
USE_S0_AWQOS 0
USE_S0_AWPROT 1
USE_M0_WSTRB 1
USE_S0_WLAST 0
USE_M0_BID 0
USE_M0_BRESP 1
USE_S0_BRESP 1
USE_M0_ARID 0
USE_M0_ARREGION 0
USE_M0_ARLEN 0
USE_M0_ARSIZE 0
USE_M0_ARBURST 0
USE_M0_ARLOCK 0
USE_M0_ARCACHE 0
USE_M0_ARQOS 0
USE_S0_ARREGION 0
USE_S0_ARLOCK 0
USE_S0_ARCACHE 0
USE_S0_ARQOS 0
USE_S0_ARPROT 1
USE_M0_RID 0
USE_M0_RRESP 1
USE_M0_RLAST 0
USE_S0_RRESP 1
M0_ID_WIDTH 8
S0_ID_WIDTH 8
DATA_WIDTH 32
WRITE_ADDR_USER_WIDTH 64
READ_ADDR_USER_WIDTH 64
WRITE_DATA_USER_WIDTH 64
WRITE_RESP_USER_WIDTH 64
READ_DATA_USER_WIDTH 64
ADDR_WIDTH 20
USE_S0_AWUSER 0
USE_S0_ARUSER 0
USE_S0_WUSER 0
USE_S0_RUSER 0
USE_S0_BUSER 0
USE_M0_AWUSER 0
USE_M0_ARUSER 0
USE_M0_WUSER 0
USE_M0_RUSER 0
USE_M0_BUSER 0
AXI_VERSION AXI4-Lite
WRITE_ISSUING_CAPABILITY 16
READ_ISSUING_CAPABILITY 16
COMBINED_ISSUING_CAPABILITY 16
WRITE_ACCEPTANCE_CAPABILITY 16
READ_ACCEPTANCE_CAPABILITY 16
COMBINED_ACCEPTANCE_CAPABILITY 16
ACE_LITE_SUPPORT 0
SYNC_RESET 0
BACKPRESSURE_DURING_RESET 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

perf_monch0_pmon_jamb

altera_jtag_avalon_master v19.1
perf_monch0_csr_clk_bridge out_clk   perf_monch0_pmon_jamb
  clk
perf_monch0_csr_reset_controller out_reset_3  
  clk_reset
master   perf_monch0_axi4l_bridge
  s0


Parameters

USE_PLI 1
PLI_PORT 50000
FAST_VER 0
FIFO_DEPTHS 2
generateLegacySim false
  

Software Assignments

(none)

perf_monch0_global_monitor

pmon_global_monitor v1.0.0
perf_monch0_csr_clk_bridge out_clk   perf_monch0_global_monitor
  clk
out_clk  
  csr_apb3_clk
perf_monch0_csr_reset_controller out_reset_1  
  reset_n
out_reset_1  
  csr_apb3_reset_n
perf_monch0_axi4l_bridge m0  
  csr_apb3


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

perf_monch0_unit_monitor_0

pmon_unit_monitor v1.0.0
perf_monch0_clk_bridge out_clk   perf_monch0_unit_monitor_0
  clk
perf_monch0_reset_bridge out_reset  
  reset_n
perf_monch0_csr_clk_bridge out_clk  
  csr_apb3_clk
perf_monch0_csr_reset_controller out_reset_2  
  csr_apb3_reset_n
perf_monch0_axi4l_bridge m0  
  csr_apb3


Parameters

COUNTER_WIDTH 48
PORT_CTRL_AXI4_AWADDR_WIDTH 44
PORT_CTRL_AXI4_ARADDR_WIDTH 44
PORT_CTRL_AXI4_AWUSER_WIDTH 1
PORT_CTRL_AXI4_USE_AWUSER true
PORT_CTRL_AXI4_USE_AWLOCK false
PORT_CTRL_AXI4_USE_AWCACHE false
PORT_CTRL_AXI4_USE_AWQOS false
PORT_CTRL_AXI4_USE_AWREGION false
PORT_CTRL_AXI4_ARUSER_WIDTH 1
PORT_CTRL_AXI4_USE_ARUSER true
PORT_CTRL_AXI4_USE_ARLOCK false
PORT_CTRL_AXI4_USE_ARCACHE false
PORT_CTRL_AXI4_USE_ARQOS false
PORT_CTRL_AXI4_USE_ARREGION false
PORT_CTRL_AXI4_AWID_WIDTH 7
PORT_CTRL_AXI4_ARID_WIDTH 7
PORT_CTRL_AXI4_WDATA_WIDTH 256
PORT_CTRL_AXI4_RDATA_WIDTH 256
PORT_CTRL_AXI4_WUSER_WIDTH 1
PORT_CTRL_AXI4_RUSER_WIDTH 1
PORT_CTRL_AXI4_BUSER_WIDTH 1
PORT_CTRL_AXI4_USE_BUSER true
PORT_CTRL_AXI4_WSTRB_WIDTH 32
MONITOR_INDEX_IN 0
UNIT_ID 0
ADVANCED_LAT false
LOG_PRINT false
PRINT_INTERMEDIATE_LOG false
WRLAT_FIFO_DEPTH 64
RDLAT_FIFO_DEPTH 64
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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