agilex5_hps_h2f_simulation_tb |
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2023.11.07.09:27:45 | Datasheet |
Parameters
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Software Assignments(none) |
agilex5_hps_h2f_simulation_inst_clk_bfm | clk | agilex5_hps_h2f_simulation_inst_reset_bfm | |
clk | |||
reset | agilex5_hps_h2f_simulation_inst_reset_in | ||
in_reset |
Parameters
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Software Assignments(none) |
Parameters
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Software Assignments(none) |
agilex5_hps_h2f_simulation_inst_clk_bfm | clk | agilex5_hps_h2f_simulation_inst_clock_in | |
in_clk | |||
out_clk | agilex5_hps_h2f_simulation_inst_reset_in | ||
clk | |||
out_clk | agilex5_hps_h2f_simulation_inst_intel_onchip_memory_0 | ||
clk1 | |||
out_clk | agilex5_hps_h2f_simulation_inst_intel_agilex_5_soc_0 | ||
f2sdram_axi_clock | |||
out_clk | |||
fpga2hps_clock | |||
out_clk | |||
hps2fpga_axi_clock | |||
out_clk | |||
lwhps2fpga_axi_clock |
Parameters
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Software Assignments(none) |
agilex5_hps_h2f_simulation_inst_clock_in | out_clk | agilex5_hps_h2f_simulation_inst_intel_agilex_5_soc_0 | |
f2sdram_axi_clock | |||
out_clk | |||
fpga2hps_clock | |||
out_clk | |||
hps2fpga_axi_clock | |||
out_clk | |||
lwhps2fpga_axi_clock | |||
hps2fpga | agilex5_hps_h2f_simulation_inst_intel_onchip_memory_0 | ||
axi_s1 |
Parameters
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Software Assignments(none) |
agilex5_hps_h2f_simulation_inst_intel_agilex_5_soc_0 | hps2fpga | agilex5_hps_h2f_simulation_inst_intel_onchip_memory_0 |
axi_s1 | ||
agilex5_hps_h2f_simulation_inst_clock_in | out_clk | |
clk1 | ||
agilex5_hps_h2f_simulation_inst_reset_in | out_reset | |
reset1 |
Parameters
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Software Assignments
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agilex5_hps_h2f_simulation_inst_clock_in | out_clk | agilex5_hps_h2f_simulation_inst_reset_in | |
clk | |||
agilex5_hps_h2f_simulation_inst_reset_bfm | reset | ||
in_reset | |||
out_reset | agilex5_hps_h2f_simulation_inst_intel_onchip_memory_0 | ||
reset1 |
Parameters
|
Software Assignments(none) |
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