agilex5_hps_f2h_simulation_tb

2024.02.01.01:01:50 Datasheet
Overview

Memory Map

agilex5_hps_f2h_simulation_inst_clk_bfm

altera_avalon_clock_source v19.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

agilex5_hps_f2h_simulation_inst_reset_bfm

altera_avalon_reset_source v19.1
agilex5_hps_f2h_simulation_inst_clk_bfm clk   agilex5_hps_f2h_simulation_inst_reset_bfm
  clk
reset   agilex5_hps_f2h_simulation_inst_reset_in
  in_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

agilex5_hps_f2h_simulation_inst

agilex5_hps_f2h_simulation v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

agilex5_hps_f2h_simulation_inst_clock_in

altera_clock_bridge v19.2.0
agilex5_hps_f2h_simulation_inst_clk_bfm clk   agilex5_hps_f2h_simulation_inst_clock_in
  in_clk
out_clk   agilex5_hps_f2h_simulation_inst_reset_in
  clk
out_clk   agilex5_hps_f2h_simulation_inst_mgc_axi4_master_0
  clock_sink
out_clk   agilex5_hps_f2h_simulation_inst_intel_agilex_5_soc_0
  f2sdram_axi_clock
out_clk  
  fpga2hps_clock
out_clk  
  hps2fpga_axi_clock
out_clk  
  lwhps2fpga_axi_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

agilex5_hps_f2h_simulation_inst_intel_agilex_5_soc_0

intel_agilex_5_soc v2.0.0
agilex5_hps_f2h_simulation_inst_mgc_axi4_master_0 altera_axi4_master   agilex5_hps_f2h_simulation_inst_intel_agilex_5_soc_0
  fpga2hps
agilex5_hps_f2h_simulation_inst_clock_in out_clk  
  f2sdram_axi_clock
out_clk  
  fpga2hps_clock
out_clk  
  hps2fpga_axi_clock
out_clk  
  lwhps2fpga_axi_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

agilex5_hps_f2h_simulation_inst_mgc_axi4_master_0

mgc_axi4_master v2020.1.0.1
agilex5_hps_f2h_simulation_inst_clock_in out_clk   agilex5_hps_f2h_simulation_inst_mgc_axi4_master_0
  clock_sink
agilex5_hps_f2h_simulation_inst_reset_in out_reset  
  reset_sink
altera_axi4_master   agilex5_hps_f2h_simulation_inst_intel_agilex_5_soc_0
  fpga2hps


Parameters

generateLegacySim false
  

Software Assignments

(none)

agilex5_hps_f2h_simulation_inst_reset_in

altera_reset_bridge v19.2.0
agilex5_hps_f2h_simulation_inst_clock_in out_clk   agilex5_hps_f2h_simulation_inst_reset_in
  clk
agilex5_hps_f2h_simulation_inst_reset_bfm reset  
  in_reset
out_reset   agilex5_hps_f2h_simulation_inst_mgc_axi4_master_0
  reset_sink


Parameters

generateLegacySim false
  

Software Assignments

(none)
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