agilex5_hps_f2h_simulation_clock_in

2024.02.01.01:01:43 Datasheet
Overview

Memory Map

clock_in

altera_clock_bridge v19.2.0


Parameters

DERIVED_CLOCK_RATE 50000000
EXPLICIT_CLOCK_RATE 50000000
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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