agilex5_hps_f2h_simulation

2024.02.01.01:01:46 Datasheet
Overview

Memory Map

clock_in

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_agilex_5_soc_0

intel_agilex_5_soc v2.0.0
mgc_axi4_master_0 altera_axi4_master   intel_agilex_5_soc_0
  fpga2hps
clock_in out_clk  
  f2sdram_axi_clock
out_clk  
  fpga2hps_clock
out_clk  
  hps2fpga_axi_clock
out_clk  
  lwhps2fpga_axi_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

mgc_axi4_master_0

mgc_axi4_master v2020.1.0.1
clock_in out_clk   mgc_axi4_master_0
  clock_sink
reset_in out_reset  
  reset_sink
altera_axi4_master   intel_agilex_5_soc_0
  fpga2hps


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_in

altera_reset_bridge v19.2.0
clock_in out_clk   reset_in
  clk
out_reset   mgc_axi4_master_0
  reset_sink


Parameters

generateLegacySim false
  

Software Assignments

(none)
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