agilex5_hps_f2h_simulation |
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2024.02.01.01:01:46 | Datasheet |
Parameters
|
Software Assignments(none) |
mgc_axi4_master_0 | altera_axi4_master | intel_agilex_5_soc_0 |
fpga2hps | ||
clock_in | out_clk | |
f2sdram_axi_clock | ||
out_clk | ||
fpga2hps_clock | ||
out_clk | ||
hps2fpga_axi_clock | ||
out_clk | ||
lwhps2fpga_axi_clock |
Parameters
|
Software Assignments(none) |
clock_in | out_clk | mgc_axi4_master_0 | |
clock_sink | |||
reset_in | out_reset | ||
reset_sink | |||
altera_axi4_master | intel_agilex_5_soc_0 | ||
fpga2hps |
Parameters
|
Software Assignments(none) |
clock_in | out_clk | reset_in | |
clk | |||
out_reset | mgc_axi4_master_0 | ||
reset_sink |
Parameters
|
Software Assignments(none) |
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