q_sys

2024.07.05.15:39:01 Datasheet
Overview
  clk_0  q_sys

All Components
   System_max_ID_0 System_max_ID 1.0
   i2c_0 altera_avalon_i2c 22.1
   i2c_1 altera_avalon_i2c 22.1
   i2c_2 altera_avalon_i2c 22.1
   i2c_3 altera_avalon_i2c 22.1
   i2c_4 altera_avalon_i2c 22.1
   i2c_5 altera_avalon_i2c 22.1
   i2c_6 altera_avalon_i2c 22.1
   i2c_7 altera_avalon_i2c 22.1
   i2c_8 altera_avalon_i2c 22.1
   i2c_9 altera_avalon_i2c 22.1
   i2c_power_max10 altera_avalon_i2c 22.1
   pio_dipsw altera_avalon_pio 22.1
   pio_led_g altera_avalon_pio 22.1
   pio_led_y altera_avalon_pio 22.1
   pio_mux_dipsw altera_avalon_pio 22.1
   pio_pb altera_avalon_pio 22.1
Memory Map
bmc_i2c dac_i2c_access_reg_0 fmca_i2c_slave fmcb_i2c_slave master_0
 avalon_master  avalon_master  avalon_master  avalon_master  master
  System_max_ID_0
slv  0x00000000 0x00000000 0x00000000 0x00000000
  i2c_0
csr  0x00000200
  i2c_1
csr  0x00000300
  i2c_2
csr  0x00000400
  i2c_3
csr  0x00000500
  i2c_4
csr  0x00000000 0x00000600
  i2c_5
csr  0x00000800
  i2c_6
csr  0x00000700
  i2c_7
csr  0x00001000
  i2c_8
csr  0x00001100
  i2c_9
csr  0x00001200
  i2c_power_max10
csr  0x00000900
  pio_dipsw
s1  0x00000090
  pio_led_g
s1  0x00000060
  pio_led_y
s1  0x00000070
  pio_mux_dipsw
s1  0x00000080
  pio_pb
s1  0x00500000

System_max_ID_0

System_max_ID v1.0
bmc_i2c avalon_master   System_max_ID_0
  slv
fmcb_i2c_slave avalon_master  
  slv
fmca_i2c_slave avalon_master  
  slv
master_0 master  
  slv
clk_0 clk  
  clock
clk_reset  
  reset


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

bmc_i2c

altera_i2cslave_to_avlmm_bridge v22.1
clk_0 clk   bmc_i2c
  clock
clk_reset  
  reset
avalon_master   System_max_ID_0
  slv


Parameters

I2C_SLAVE_ADDRESS 85
BYTE_ADDRESSING 2
ADDRESS_STEALING 0
READ_ONLY 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

clk_0

clock_source v22.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

dac_i2c_access_reg_0

dac_i2c_access_reg v1.0
clk_0 clk   dac_i2c_access_reg_0
  clock
clk_reset  
  reset_sink
avalon_master   i2c_4
  csr
interrupt_receiver  
  interrupt_sender


Parameters

AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

fmca_i2c_slave

altera_i2cslave_to_avlmm_bridge v22.1
clk_0 clk   fmca_i2c_slave
  clock
clk_reset  
  reset
avalon_master   System_max_ID_0
  slv


Parameters

I2C_SLAVE_ADDRESS 86
BYTE_ADDRESSING 2
ADDRESS_STEALING 0
READ_ONLY 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

fmcb_i2c_slave

altera_i2cslave_to_avlmm_bridge v22.1
clk_0 clk   fmcb_i2c_slave
  clock
clk_reset  
  reset
avalon_master   System_max_ID_0
  slv


Parameters

I2C_SLAVE_ADDRESS 87
BYTE_ADDRESSING 2
ADDRESS_STEALING 0
READ_ONLY 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

i2c_0

altera_avalon_i2c v22.1
master_0 master   i2c_0
  csr
clk_0 clk  
  clock
clk_reset  
  reset_sink


Parameters

USE_AV_ST 0
FIFO_DEPTH 4
FIFO_DEPTH_LOG2 2
clockRate 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

FIFO_DEPTH 4
FREQ 50000000
USE_AV_ST 0

i2c_1

altera_avalon_i2c v22.1
master_0 master   i2c_1
  csr
clk_0 clk  
  clock
clk_reset  
  reset_sink


Parameters

USE_AV_ST 0
FIFO_DEPTH 4
FIFO_DEPTH_LOG2 2
clockRate 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

FIFO_DEPTH 4
FREQ 50000000
USE_AV_ST 0

i2c_2

altera_avalon_i2c v22.1
master_0 master   i2c_2
  csr
clk_0 clk  
  clock
clk_reset  
  reset_sink


Parameters

USE_AV_ST 0
FIFO_DEPTH 4
FIFO_DEPTH_LOG2 2
clockRate 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

FIFO_DEPTH 4
FREQ 50000000
USE_AV_ST 0

i2c_3

altera_avalon_i2c v22.1
master_0 master   i2c_3
  csr
clk_0 clk  
  clock
clk_reset  
  reset_sink


Parameters

USE_AV_ST 0
FIFO_DEPTH 4
FIFO_DEPTH_LOG2 2
clockRate 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

FIFO_DEPTH 4
FREQ 50000000
USE_AV_ST 0

i2c_4

altera_avalon_i2c v22.1
dac_i2c_access_reg_0 avalon_master   i2c_4
  csr
interrupt_receiver  
  interrupt_sender
master_0 master  
  csr
clk_0 clk  
  clock
clk_reset  
  reset_sink


Parameters

USE_AV_ST 0
FIFO_DEPTH 4
FIFO_DEPTH_LOG2 2
clockRate 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

FIFO_DEPTH 4
FREQ 50000000
USE_AV_ST 0

i2c_5

altera_avalon_i2c v22.1
master_0 master   i2c_5
  csr
clk_0 clk  
  clock
clk_reset  
  reset_sink


Parameters

USE_AV_ST 0
FIFO_DEPTH 4
FIFO_DEPTH_LOG2 2
clockRate 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

FIFO_DEPTH 4
FREQ 50000000
USE_AV_ST 0

i2c_6

altera_avalon_i2c v22.1
master_0 master   i2c_6
  csr
clk_0 clk  
  clock
clk_reset  
  reset_sink


Parameters

USE_AV_ST 0
FIFO_DEPTH 4
FIFO_DEPTH_LOG2 2
clockRate 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

FIFO_DEPTH 4
FREQ 50000000
USE_AV_ST 0

i2c_7

altera_avalon_i2c v22.1
master_0 master   i2c_7
  csr
clk_0 clk  
  clock
clk_reset  
  reset_sink


Parameters

USE_AV_ST 0
FIFO_DEPTH 4
FIFO_DEPTH_LOG2 2
clockRate 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

FIFO_DEPTH 4
FREQ 50000000
USE_AV_ST 0

i2c_8

altera_avalon_i2c v22.1
master_0 master   i2c_8
  csr
clk_0 clk  
  clock
clk_reset  
  reset_sink


Parameters

USE_AV_ST 0
FIFO_DEPTH 4
FIFO_DEPTH_LOG2 2
clockRate 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

FIFO_DEPTH 4
FREQ 50000000
USE_AV_ST 0

i2c_9

altera_avalon_i2c v22.1
master_0 master   i2c_9
  csr
clk_0 clk  
  clock
clk_reset  
  reset_sink


Parameters

USE_AV_ST 0
FIFO_DEPTH 4
FIFO_DEPTH_LOG2 2
clockRate 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

FIFO_DEPTH 4
FREQ 50000000
USE_AV_ST 0

i2c_power_max10

altera_avalon_i2c v22.1
master_0 master   i2c_power_max10
  csr
clk_0 clk  
  clock
clk_reset  
  reset_sink


Parameters

USE_AV_ST 0
FIFO_DEPTH 64
FIFO_DEPTH_LOG2 6
clockRate 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

FIFO_DEPTH 64
FREQ 50000000
USE_AV_ST 0

master_0

altera_jtag_avalon_master v22.1
clk_0 clk   master_0
  clk
clk_reset  
  clk_reset
master   i2c_0
  csr
master   i2c_power_max10
  csr
master   i2c_1
  csr
master   i2c_2
  csr
master   i2c_3
  csr
master   i2c_4
  csr
master   i2c_6
  csr
master   i2c_5
  csr
master   i2c_7
  csr
master   i2c_8
  csr
master   i2c_9
  csr
master   pio_dipsw
  s1
master   pio_pb
  s1
master   pio_led_g
  s1
master   pio_led_y
  s1
master   pio_mux_dipsw
  s1
master   System_max_ID_0
  slv


Parameters

USE_PLI 0
PLI_PORT 50000
COMPONENT_CLOCK 0
FAST_VER 0
FIFO_DEPTHS 2
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M16SCU324C8G
AUTO_DEVICE_SPEEDGRADE 8
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

pio_dipsw

altera_avalon_pio v22.1
master_0 master   pio_dipsw
  s1
clk_0 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
clockRate 50000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 8
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_led_g

altera_avalon_pio v22.1
master_0 master   pio_led_g
  s1
clk_0 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 6
clockRate 50000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 6
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_led_y

altera_avalon_pio v22.1
master_0 master   pio_led_y
  s1
clk_0 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 2
clockRate 50000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_mux_dipsw

altera_avalon_pio v22.1
master_0 master   pio_mux_dipsw
  s1
clk_0 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 12
clockRate 50000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 12
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_pb

altera_avalon_pio v22.1
master_0 master   pio_pb
  s1
clk_0 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 6
clockRate 50000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 6
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0
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