agilex5_hps_h2f_simulation_tb

2023.11.07.09:27:45 Datasheet
Overview

Memory Map

agilex5_hps_h2f_simulation_inst_clk_bfm

altera_avalon_clock_source v19.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

agilex5_hps_h2f_simulation_inst_reset_bfm

altera_avalon_reset_source v19.1
agilex5_hps_h2f_simulation_inst_clk_bfm clk   agilex5_hps_h2f_simulation_inst_reset_bfm
  clk
reset   agilex5_hps_h2f_simulation_inst_reset_in
  in_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

agilex5_hps_h2f_simulation_inst

agilex5_hps_h2f_simulation v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

agilex5_hps_h2f_simulation_inst_clock_in

altera_clock_bridge v19.2.0
agilex5_hps_h2f_simulation_inst_clk_bfm clk   agilex5_hps_h2f_simulation_inst_clock_in
  in_clk
out_clk   agilex5_hps_h2f_simulation_inst_reset_in
  clk
out_clk   agilex5_hps_h2f_simulation_inst_intel_onchip_memory_0
  clk1
out_clk   agilex5_hps_h2f_simulation_inst_intel_agilex_5_soc_0
  f2sdram_axi_clock
out_clk  
  fpga2hps_clock
out_clk  
  hps2fpga_axi_clock
out_clk  
  lwhps2fpga_axi_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

agilex5_hps_h2f_simulation_inst_intel_agilex_5_soc_0

intel_agilex_5_soc v2.0.0
agilex5_hps_h2f_simulation_inst_clock_in out_clk   agilex5_hps_h2f_simulation_inst_intel_agilex_5_soc_0
  f2sdram_axi_clock
out_clk  
  fpga2hps_clock
out_clk  
  hps2fpga_axi_clock
out_clk  
  lwhps2fpga_axi_clock
hps2fpga   agilex5_hps_h2f_simulation_inst_intel_onchip_memory_0
  axi_s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

agilex5_hps_h2f_simulation_inst_intel_onchip_memory_0

intel_onchip_memory v1.4.7
agilex5_hps_h2f_simulation_inst_intel_agilex_5_soc_0 hps2fpga   agilex5_hps_h2f_simulation_inst_intel_onchip_memory_0
  axi_s1
agilex5_hps_h2f_simulation_inst_clock_in out_clk  
  clk1
agilex5_hps_h2f_simulation_inst_reset_in out_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE agilex5_hps_h2f_simulation_intel_onchip_memory_0_intel_onchip_memory_0
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 65536
WRITABLE 1

agilex5_hps_h2f_simulation_inst_reset_in

altera_reset_bridge v19.2.0
agilex5_hps_h2f_simulation_inst_clock_in out_clk   agilex5_hps_h2f_simulation_inst_reset_in
  clk
agilex5_hps_h2f_simulation_inst_reset_bfm reset  
  in_reset
out_reset   agilex5_hps_h2f_simulation_inst_intel_onchip_memory_0
  reset1


Parameters

generateLegacySim false
  

Software Assignments

(none)
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