agilex5_hps_f2sdram_simulation_tb |
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2023.11.08.08:51:51 | Datasheet |
Parameters
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Software Assignments(none) |
agilex5_hps_f2sdram_simulation_inst_clk_bfm | clk | agilex5_hps_f2sdram_simulation_inst_reset_bfm | |
clk | |||
reset | agilex5_hps_f2sdram_simulation_inst_reset_in | ||
in_reset |
Parameters
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Software Assignments(none) |
Parameters
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Software Assignments(none) |
agilex5_hps_f2sdram_simulation_inst_clk_bfm | clk | agilex5_hps_f2sdram_simulation_inst_clock_in | |
in_clk | |||
out_clk | agilex5_hps_f2sdram_simulation_inst_reset_in | ||
clk | |||
out_clk | agilex5_hps_f2sdram_simulation_inst_mgc_axi4_master_0 | ||
clock_sink | |||
out_clk | agilex5_hps_f2sdram_simulation_inst_intel_agilex_5_soc_0 | ||
f2sdram_axi_clock | |||
out_clk | |||
fpga2hps_clock | |||
out_clk | |||
hps2fpga_axi_clock | |||
out_clk | |||
lwhps2fpga_axi_clock |
Parameters
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Software Assignments(none) |
agilex5_hps_f2sdram_simulation_inst_mgc_axi4_master_0 | altera_axi4_master | agilex5_hps_f2sdram_simulation_inst_intel_agilex_5_soc_0 |
f2sdram | ||
agilex5_hps_f2sdram_simulation_inst_clock_in | out_clk | |
f2sdram_axi_clock | ||
out_clk | ||
fpga2hps_clock | ||
out_clk | ||
hps2fpga_axi_clock | ||
out_clk | ||
lwhps2fpga_axi_clock |
Parameters
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Software Assignments(none) |
agilex5_hps_f2sdram_simulation_inst_clock_in | out_clk | agilex5_hps_f2sdram_simulation_inst_mgc_axi4_master_0 | |
clock_sink | |||
agilex5_hps_f2sdram_simulation_inst_reset_in | out_reset | ||
reset_sink | |||
altera_axi4_master | agilex5_hps_f2sdram_simulation_inst_intel_agilex_5_soc_0 | ||
f2sdram |
Parameters
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Software Assignments(none) |
agilex5_hps_f2sdram_simulation_inst_clock_in | out_clk | agilex5_hps_f2sdram_simulation_inst_reset_in | |
clk | |||
agilex5_hps_f2sdram_simulation_inst_reset_bfm | reset | ||
in_reset | |||
out_reset | agilex5_hps_f2sdram_simulation_inst_mgc_axi4_master_0 | ||
reset_sink |
Parameters
|
Software Assignments(none) |
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