q_sys_hmc

2014.04.17.09:58:32 Datasheet
Overview
  ext_clk_50  q_sys_hmc
  refclk 
  mSGDMA_0_clk 
  mSGDMA_0_clk_0 
  reset 

All Components
   fpga_sdram altera_mem_if_ddr3_emif 13.1
   master_driver_msgdma_0 master_driver_msgdma 1.0
   mSGDMA_0 mSGDMA_hmc 1.0
   mSGDMA_0_prbs_pattern_generator prbs_pattern_generator 1.1
   mSGDMA_0_prbs_pattern_checker prbs_pattern_checker 1.1
   mSGDMA_0_dispatcher_write modular_sgdma_dispatcher 1.0
   mSGDMA_0_dispatcher_read modular_sgdma_dispatcher 1.0
   mSGDMA_0_mm_bridge_slv altera_avalon_mm_bridge 13.1
   mSGDMA_0_status_mon_0 status_mon 1.0
   mSGDMA_0_timer_0 altera_avalon_timer 13.1
   mSGDMA_0_freq_counter_0 freq_counter 1.0
   mm_bridge_0 altera_avalon_mm_bridge 13.1
Memory Map
master_driver_msgdma_0 mSGDMA_0 mSGDMA_0_dma_write_master mSGDMA_0_dma_read_master mm_traffic_generator_0
 avalon_master  dma_read_master  dma_write_master  Data_Write_Master  Data_Read_Master  avl
  fpga_sdram
avl_0  0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
csr 
  master_driver_msgdma_0
csr 
  mSGDMA_0
mm_bridge_slv 
  mSGDMA_0_prbs_pattern_generator
csr  0x00200040
  mSGDMA_0_prbs_pattern_checker
csr  0x00200000
  mSGDMA_0_dispatcher_write
CSR  0x00200060
Descriptor_Slave  0x002000a0
  mSGDMA_0_dispatcher_read
CSR  0x00200080
Descriptor_Slave  0x002000b0
  mSGDMA_0_status_mon_0
slv  0x00281200
  mSGDMA_0_timer_0
s1  0x00281000
  mSGDMA_0_freq_counter_0
csr  0x00290000

ext_clk_50

clock_source v13.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

fpga_sdram

altera_mem_if_ddr3_emif v13.1
pll_0 outclk0   fpga_sdram
  mp_wfifo_clk_0
outclk0  
  mp_rfifo_clk_0
outclk0  
  mp_cmd_clk_0
outclk0  
  mp_rfifo_clk_1
outclk0  
  mp_wfifo_clk_1
outclk0  
  csr_clk
outclk0  
  mp_rfifo_clk_2
outclk0  
  mp_wfifo_clk_2
outclk0  
  mp_rfifo_clk_3
outclk0  
  mp_wfifo_clk_3
refclk clk  
  pll_ref_clk
clk_reset  
  global_reset
clk_reset  
  soft_reset
clk_reset  
  mp_cmd_reset_n_0
clk_reset  
  mp_rfifo_reset_n_0
clk_reset  
  mp_wfifo_reset_n_0
clk_reset  
  mp_rfifo_reset_n_1
clk_reset  
  mp_wfifo_reset_n_1
clk_reset  
  mp_rfifo_reset_n_2
clk_reset  
  mp_wfifo_reset_n_2
clk_reset  
  mp_rfifo_reset_n_3
clk_reset  
  mp_wfifo_reset_n_3
clk_reset  
  csr_reset_n
mSGDMA_0_dma_read_master Data_Read_Master  
  avl_0
mSGDMA_0_dma_write_master Data_Write_Master  
  avl_0
mSGDMA_0_status_mon_0 status  
  status
mm_traffic_generator_0 avl  
  avl_0
afi_clk   pll_0
  refclk


Parameters

AC_ROM_MR0 0010000100001
AC_ROM_MR0_MIRR 0010001000001
AC_ROM_MR0_CALIB
AC_ROM_MR0_DLL_RESET 0010100100000
AC_ROM_MR0_DLL_RESET_MIRR 0010011000000
AC_ROM_MR1 0000001000100
AC_ROM_MR1_MIRR 0000000100100
AC_ROM_MR1_CALIB
AC_ROM_MR1_OCD_ENABLE
AC_ROM_MR2 0000000000000
AC_ROM_MR2_MIRR 0000000000000
AC_ROM_MR3 0000000000000
AC_ROM_MR3_MIRR 0000000000000
USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true
MR0_BL 1
MR0_BT 0
MR0_CAS_LATENCY 2
MR0_DLL 1
MR0_WR 2
MR0_PD 0
MR1_DLL 0
MR1_ODS 0
MR1_RTT 3
MR1_AL 0
MR1_WL 0
MR1_TDQS 0
MR1_QOFF 0
MR1_DQS 0
MR1_RDQS 0
MR2_CWL 0
MR2_ASR 0
MR2_SRT 0
MR2_SRF 0
MR2_RTT_WR 0
MR3_MPR_RF 0
MR3_MPR 0
MR3_MPR_AA 0
MEM_IF_READ_DQS_WIDTH 5
MEM_IF_WRITE_DQS_WIDTH 5
SCC_DATA_WIDTH 1
MEM_IF_ADDR_WIDTH 14
MEM_IF_ADDR_WIDTH_MIN 13
MEM_IF_ROW_ADDR_WIDTH 14
MEM_IF_COL_ADDR_WIDTH 10
MEM_IF_DM_WIDTH 5
MEM_IF_CS_PER_RANK 1
MEM_IF_NUMBER_OF_RANKS 1
MEM_IF_CS_PER_DIMM 1
MEM_IF_CONTROL_WIDTH 1
MEM_BURST_LENGTH 8
MEM_LEVELING false
MEM_IF_DQS_WIDTH 5
MEM_IF_CS_WIDTH 1
MEM_IF_CHIP_BITS 1
MEM_IF_BANKADDR_WIDTH 3
MEM_IF_DQ_WIDTH 40
MEM_IF_CK_WIDTH 1
MEM_IF_CLK_EN_WIDTH 1
MEM_IF_CLK_PAIR_COUNT 1
DEVICE_WIDTH 1
MEM_CLK_MAX_NS 1.25
MEM_CLK_MAX_PS 1250.0
MEM_TRC 20
MEM_TRAS 14
MEM_TRCD 6
MEM_TRP 6
MEM_TREFI 3120
MEM_TRFC 64
CFG_TCCD 1
MEM_TWR 6
MEM_TFAW 16
MEM_TRRD 4
MEM_TRTP 4
MEM_DQS_TO_CLK_CAPTURE_DELAY 450
MEM_CLK_TO_DQS_CAPTURE_DELAY 100000
MEM_IF_ODT_WIDTH 1
MEM_WTCL_INT 5
FLY_BY true
RDIMM false
LRDIMM false
RDIMM_INT 0
LRDIMM_INT 0
MEM_IF_RD_TO_WR_TURNAROUND_OCT 2
MEM_IF_WR_TO_RD_TURNAROUND_OCT 3
CTL_RD_TO_PCH_EXTRA_CLK 0
CTL_RD_TO_RD_EXTRA_CLK 0
CTL_WR_TO_WR_EXTRA_CLK 0
CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1
CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2
MEM_TYPE DDR3
MEM_MIRROR_ADDRESSING_DEC 0
MEM_ATCL_INT 0
MEM_REGDIMM_ENABLED false
MEM_LRDIMM_ENABLED false
MEM_VENDOR Micron
MEM_FORMAT DISCRETE
AC_PARITY false
RDIMM_CONFIG 0
LRDIMM_EXTENDED_CONFIG 0x000000000000000000
DISCRETE_FLY_BY true
DEVICE_DEPTH 1
MEM_MIRROR_ADDRESSING 0
MEM_CLK_FREQ_MAX 800.0
MEM_ROW_ADDR_WIDTH 14
MEM_COL_ADDR_WIDTH 10
MEM_DQ_WIDTH 40
MEM_DQ_PER_DQS 8
MEM_BANKADDR_WIDTH 3
MEM_IF_DM_PINS_EN true
MEM_IF_DQSN_EN true
MEM_NUMBER_OF_DIMMS 1
MEM_NUMBER_OF_RANKS_PER_DIMM 1
MEM_NUMBER_OF_RANKS_PER_DEVICE 1
MEM_RANK_MULTIPLICATION_FACTOR 1
MEM_CK_WIDTH 1
MEM_CS_WIDTH 1
MEM_CLK_EN_WIDTH 1
ALTMEMPHY_COMPATIBLE_MODE false
NEXTGEN true
MEM_IF_BOARD_BASE_DELAY 10
MEM_IF_SIM_VALID_WINDOW 0
MEM_GUARANTEED_WRITE_INIT false
MEM_VERBOSE true
PINGPONGPHY_EN false
REFRESH_BURST_VALIDATION false
MEM_BL OTF
MEM_BT Sequential
MEM_ASR Manual
MEM_SRT Normal
MEM_PD DLL off
MEM_DRV_STR RZQ/6
MEM_DLL_EN true
MEM_RTT_NOM RZQ/6
MEM_RTT_WR Dynamic ODT off
MEM_WTCL 5
MEM_ATCL Disabled
MEM_TCL 6
MEM_AUTO_LEVELING_MODE true
MEM_USER_LEVELING_MODE Leveling
MEM_INIT_EN false
MEM_INIT_FILE
DAT_DATA_WIDTH 32
TIMING_TIS 170
TIMING_TIH 120
TIMING_TDS 10
TIMING_TDH 45
TIMING_TDQSQ 100
TIMING_TQH 0.38
TIMING_TDQSCK 225
TIMING_TDQSCKDS 450
TIMING_TDQSCKDM 900
TIMING_TDQSCKDL 1200
TIMING_TDQSS 0.27
TIMING_TQSH 0.4
TIMING_TDSH 0.18
TIMING_TDSS 0.18
MEM_TINIT_US 500
MEM_TINIT_CK 200000
MEM_TDQSCK 1
MEM_TMRD_CK 4
MEM_TRAS_NS 35.0
MEM_TRCD_NS 13.75
MEM_TRP_NS 13.75
MEM_TREFI_US 7.8
MEM_TRFC_NS 160.0
CFG_TCCD_NS 2.5
MEM_TWR_NS 15.0
MEM_TWTR 4
MEM_TFAW_NS 40.0
MEM_TRRD_NS 10.0
MEM_TRTP_NS 10.0
RATE Full
MEM_CLK_FREQ 400.0
USE_MEM_CLK_FREQ false
USE_DQS_TRACKING false
FORCE_DQS_TRACKING AUTO
USE_HPS_DQS_TRACKING false
TRK_PARALLEL_SCC_LOAD false
USE_SHADOW_REGS false
FORCE_SHADOW_REGS AUTO
DQ_DDR 1
ADDR_CMD_DDR 0
AFI_RATE_RATIO 1
DATA_RATE_RATIO 2
ADDR_RATE_RATIO 1
AFI_ADDR_WIDTH 14
AFI_BANKADDR_WIDTH 3
AFI_CONTROL_WIDTH 1
AFI_CS_WIDTH 1
AFI_CLK_EN_WIDTH 1
AFI_DM_WIDTH 10
AFI_DQ_WIDTH 80
AFI_ODT_WIDTH 1
AFI_WRITE_DQS_WIDTH 5
AFI_RLAT_WIDTH 6
AFI_WLAT_WIDTH 6
AFI_RRANK_WIDTH 5
AFI_WRANK_WIDTH 5
AFI_CLK_PAIR_COUNT 1
MRS_MIRROR_PING_PONG_ATSO false
SYS_INFO_DEVICE_FAMILY CYCLONEV
PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV
DEVICE_FAMILY Cyclone V
PRE_V_SERIES_FAMILY false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM
DEVICE_FAMILY_PARAM
SPEED_GRADE 7
IS_ES_DEVICE false
DISABLE_CHILD_MESSAGING false
HARD_PHY true
HARD_EMIF true
HHP_HPS false
HHP_HPS_VERIFICATION false
HHP_HPS_SIMULATION false
HPS_PROTOCOL DEFAULT
CUT_NEW_FAMILY_TIMING true
EXPORT_CSR_PORT true
CSR_ADDR_WIDTH 10
CSR_DATA_WIDTH 8
CSR_BE_WIDTH 1
CTL_CS_WIDTH 1
AVL_ADDR_WIDTH 26
AVL_BE_WIDTH 8
AVL_DATA_WIDTH 64
AVL_SYMBOL_WIDTH 8
AVL_NUM_SYMBOLS 8
AVL_SIZE_WIDTH 8
HR_DDIO_OUT_HAS_THREE_REGS false
CTL_ECC_CSR_ENABLED true
DWIDTH_RATIO 2
CTL_ODT_ENABLED true
CTL_OUTPUT_REGD false
CTL_ECC_MULTIPLES_40_72 1
CTL_ECC_MULTIPLES_16_24_40_72 1
CTL_REGDIMM_ENABLED false
LOW_LATENCY false
CONTROLLER_TYPE nextgen_v110
CTL_TBP_NUM 4
CTL_USR_REFRESH 0
CTL_SELF_REFRESH 0
CFG_TYPE 2
CFG_INTERFACE_WIDTH 40
CFG_BURST_LENGTH 8
CFG_ADDR_ORDER 0
CFG_PDN_EXIT_CYCLES 10
CFG_POWER_SAVING_EXIT_CYCLES 5
CFG_MEM_CLK_ENTRY_CYCLES 10
CFG_SELF_RFSH_EXIT_CYCLES 512
CFG_PORT_WIDTH_WRITE_ODT_CHIP 1
CFG_PORT_WIDTH_READ_ODT_CHIP 1
CFG_WRITE_ODT_CHIP 1
CFG_READ_ODT_CHIP 0
LOCAL_CS_WIDTH 0
CFG_CLR_INTR 0
CFG_ENABLE_NO_DM 0
MEM_ADD_LAT 0
CTL_ENABLE_BURST_INTERRUPT_INT false
CTL_ENABLE_BURST_TERMINATE_INT false
CFG_ERRCMD_FIFO_REG 0
CFG_ECC_DECODER_REG 0
CTL_ENABLE_WDATA_PATH_LATENCY false
CFG_STARVE_LIMIT 10
MEM_AUTO_PD_CYCLES 0
AVL_PORT Port 0
AVL_DATA_WIDTH_PORT_0 256
AVL_ADDR_WIDTH_PORT_0 24
PRIORITY_PORT_0 1
WEIGHT_PORT_0 0
CPORT_TYPE_PORT_0 3
AVL_NUM_SYMBOLS_PORT_0 32
LSB_WFIFO_PORT_0 0
MSB_WFIFO_PORT_0 3
LSB_RFIFO_PORT_0 0
MSB_RFIFO_PORT_0 3
AVL_DATA_WIDTH_PORT_1 1
AVL_ADDR_WIDTH_PORT_1 1
PRIORITY_PORT_1 1
WEIGHT_PORT_1 0
CPORT_TYPE_PORT_1 0
AVL_NUM_SYMBOLS_PORT_1 1
LSB_WFIFO_PORT_1 5
MSB_WFIFO_PORT_1 5
LSB_RFIFO_PORT_1 5
MSB_RFIFO_PORT_1 5
AVL_DATA_WIDTH_PORT_2 1
AVL_ADDR_WIDTH_PORT_2 1
PRIORITY_PORT_2 1
WEIGHT_PORT_2 0
CPORT_TYPE_PORT_2 0
AVL_NUM_SYMBOLS_PORT_2 1
LSB_WFIFO_PORT_2 5
MSB_WFIFO_PORT_2 5
LSB_RFIFO_PORT_2 5
MSB_RFIFO_PORT_2 5
AVL_DATA_WIDTH_PORT_3 1
AVL_ADDR_WIDTH_PORT_3 1
PRIORITY_PORT_3 1
WEIGHT_PORT_3 0
CPORT_TYPE_PORT_3 0
AVL_NUM_SYMBOLS_PORT_3 1
LSB_WFIFO_PORT_3 5
MSB_WFIFO_PORT_3 5
LSB_RFIFO_PORT_3 5
MSB_RFIFO_PORT_3 5
AVL_DATA_WIDTH_PORT_4 1
AVL_ADDR_WIDTH_PORT_4 1
PRIORITY_PORT_4 1
WEIGHT_PORT_4 0
CPORT_TYPE_PORT_4 0
AVL_NUM_SYMBOLS_PORT_4 1
LSB_WFIFO_PORT_4 5
MSB_WFIFO_PORT_4 5
LSB_RFIFO_PORT_4 5
MSB_RFIFO_PORT_4 5
AVL_DATA_WIDTH_PORT_5 1
AVL_ADDR_WIDTH_PORT_5 1
PRIORITY_PORT_5 1
WEIGHT_PORT_5 0
CPORT_TYPE_PORT_5 0
AVL_NUM_SYMBOLS_PORT_5 1
LSB_WFIFO_PORT_5 5
MSB_WFIFO_PORT_5 5
LSB_RFIFO_PORT_5 5
MSB_RFIFO_PORT_5 5
ALLOCATED_RFIFO_PORT F0-F3,None,None,None,None,None
ALLOCATED_WFIFO_PORT F0-F3,None,None,None,None,None
ENUM_ATTR_COUNTER_ONE_RESET DISABLED
ENUM_ATTR_COUNTER_ZERO_RESET DISABLED
ENUM_ATTR_STATIC_CONFIG_VALID DISABLED
ENUM_AUTO_PCH_ENABLE_0 DISABLED
ENUM_AUTO_PCH_ENABLE_1 DISABLED
ENUM_AUTO_PCH_ENABLE_2 DISABLED
ENUM_AUTO_PCH_ENABLE_3 DISABLED
ENUM_AUTO_PCH_ENABLE_4 DISABLED
ENUM_AUTO_PCH_ENABLE_5 DISABLED
ENUM_CAL_REQ DISABLED
ENUM_CFG_BURST_LENGTH BL_8
ENUM_CFG_INTERFACE_WIDTH DWIDTH_40
ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512
ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_4
ENUM_CFG_TYPE DDR3
ENUM_CLOCK_OFF_0 DISABLED
ENUM_CLOCK_OFF_1 DISABLED
ENUM_CLOCK_OFF_2 DISABLED
ENUM_CLOCK_OFF_3 DISABLED
ENUM_CLOCK_OFF_4 DISABLED
ENUM_CLOCK_OFF_5 DISABLED
ENUM_CLR_INTR NO_CLR_INTR
ENUM_CMD_PORT_IN_USE_0 TRUE
ENUM_CMD_PORT_IN_USE_1 FALSE
ENUM_CMD_PORT_IN_USE_2 FALSE
ENUM_CMD_PORT_IN_USE_3 FALSE
ENUM_CMD_PORT_IN_USE_4 FALSE
ENUM_CMD_PORT_IN_USE_5 FALSE
ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT0_RFIFO_MAP FIFO_0
ENUM_CPORT0_TYPE BI_DIRECTION
ENUM_CPORT0_WFIFO_MAP FIFO_0
ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT1_RFIFO_MAP FIFO_0
ENUM_CPORT1_TYPE DISABLE
ENUM_CPORT1_WFIFO_MAP FIFO_0
ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT2_RFIFO_MAP FIFO_0
ENUM_CPORT2_TYPE DISABLE
ENUM_CPORT2_WFIFO_MAP FIFO_0
ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT3_RFIFO_MAP FIFO_0
ENUM_CPORT3_TYPE DISABLE
ENUM_CPORT3_WFIFO_MAP FIFO_0
ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT4_RFIFO_MAP FIFO_0
ENUM_CPORT4_TYPE DISABLE
ENUM_CPORT4_WFIFO_MAP FIFO_0
ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT5_RFIFO_MAP FIFO_0
ENUM_CPORT5_TYPE DISABLE
ENUM_CPORT5_WFIFO_MAP FIFO_0
ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL
ENUM_CTL_ECC_ENABLED CTL_ECC_ENABLED
ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED
ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED
ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED
ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT
ENUM_DELAY_BONDING BONDING_LATENCY_0
ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED
ENUM_DISABLE_MERGING MERGING_ENABLED
ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_8
ENUM_ENABLE_ATPG DISABLED
ENUM_ENABLE_BONDING_0 DISABLED
ENUM_ENABLE_BONDING_1 DISABLED
ENUM_ENABLE_BONDING_2 DISABLED
ENUM_ENABLE_BONDING_3 DISABLED
ENUM_ENABLE_BONDING_4 DISABLED
ENUM_ENABLE_BONDING_5 DISABLED
ENUM_ENABLE_BONDING_WRAPBACK DISABLED
ENUM_ENABLE_DQS_TRACKING DISABLED
ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED
ENUM_ENABLE_FAST_EXIT_PPD DISABLED
ENUM_ENABLE_INTR DISABLED
ENUM_ENABLE_NO_DM DISABLED
ENUM_ENABLE_PIPELINEGLOBAL DISABLED
ENUM_GANGED_ARF DISABLED
ENUM_GEN_DBE GEN_DBE_DISABLED
ENUM_GEN_SBE GEN_SBE_DISABLED
ENUM_INC_SYNC FIFO_SET_2
ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0
ENUM_MASK_CORR_DROPPED_INTR DISABLED
ENUM_MASK_DBE_INTR DISABLED
ENUM_MASK_SBE_INTR DISABLED
ENUM_MEM_IF_AL AL_0
ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3
ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8
ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_10
ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1
ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1
ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8
ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4
ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32
ENUM_MEM_IF_MEMTYPE DDR3_SDRAM
ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_14
ENUM_MEM_IF_SPEEDBIN DDR3_1600_8_8_8
ENUM_MEM_IF_TCCD TCCD_4
ENUM_MEM_IF_TCL TCL_6
ENUM_MEM_IF_TCWL TCWL_5
ENUM_MEM_IF_TFAW TFAW_16
ENUM_MEM_IF_TMRD TMRD_4
ENUM_MEM_IF_TRAS TRAS_14
ENUM_MEM_IF_TRC TRC_20
ENUM_MEM_IF_TRCD TRCD_6
ENUM_MEM_IF_TRP TRP_6
ENUM_MEM_IF_TRRD TRRD_4
ENUM_MEM_IF_TRTP TRTP_4
ENUM_MEM_IF_TWR TWR_6
ENUM_MEM_IF_TWTR TWTR_4
ENUM_MMR_CFG_MEM_BL MP_BL_8
ENUM_OUTPUT_REGD DISABLED
ENUM_PDN_EXIT_CYCLES SLOW_EXIT
ENUM_PORT0_WIDTH PORT_256_BIT
ENUM_PORT1_WIDTH PORT_32_BIT
ENUM_PORT2_WIDTH PORT_32_BIT
ENUM_PORT3_WIDTH PORT_32_BIT
ENUM_PORT4_WIDTH PORT_32_BIT
ENUM_PORT5_WIDTH PORT_32_BIT
ENUM_PRIORITY_0_0 WEIGHT_0
ENUM_PRIORITY_0_1 WEIGHT_0
ENUM_PRIORITY_0_2 WEIGHT_0
ENUM_PRIORITY_0_3 WEIGHT_0
ENUM_PRIORITY_0_4 WEIGHT_0
ENUM_PRIORITY_0_5 WEIGHT_0
ENUM_PRIORITY_1_0 WEIGHT_0
ENUM_PRIORITY_1_1 WEIGHT_0
ENUM_PRIORITY_1_2 WEIGHT_0
ENUM_PRIORITY_1_3 WEIGHT_0
ENUM_PRIORITY_1_4 WEIGHT_0
ENUM_PRIORITY_1_5 WEIGHT_0
ENUM_PRIORITY_2_0 WEIGHT_0
ENUM_PRIORITY_2_1 WEIGHT_0
ENUM_PRIORITY_2_2 WEIGHT_0
ENUM_PRIORITY_2_3 WEIGHT_0
ENUM_PRIORITY_2_4 WEIGHT_0
ENUM_PRIORITY_2_5 WEIGHT_0
ENUM_PRIORITY_3_0 WEIGHT_0
ENUM_PRIORITY_3_1 WEIGHT_0
ENUM_PRIORITY_3_2 WEIGHT_0
ENUM_PRIORITY_3_3 WEIGHT_0
ENUM_PRIORITY_3_4 WEIGHT_0
ENUM_PRIORITY_3_5 WEIGHT_0
ENUM_PRIORITY_4_0 WEIGHT_0
ENUM_PRIORITY_4_1 WEIGHT_0
ENUM_PRIORITY_4_2 WEIGHT_0
ENUM_PRIORITY_4_3 WEIGHT_0
ENUM_PRIORITY_4_4 WEIGHT_0
ENUM_PRIORITY_4_5 WEIGHT_0
ENUM_PRIORITY_5_0 WEIGHT_0
ENUM_PRIORITY_5_1 WEIGHT_0
ENUM_PRIORITY_5_2 WEIGHT_0
ENUM_PRIORITY_5_3 WEIGHT_0
ENUM_PRIORITY_5_4 WEIGHT_0
ENUM_PRIORITY_5_5 WEIGHT_0
ENUM_PRIORITY_6_0 WEIGHT_0
ENUM_PRIORITY_6_1 WEIGHT_0
ENUM_PRIORITY_6_2 WEIGHT_0
ENUM_PRIORITY_6_3 WEIGHT_0
ENUM_PRIORITY_6_4 WEIGHT_0
ENUM_PRIORITY_6_5 WEIGHT_0
ENUM_PRIORITY_7_0 WEIGHT_0
ENUM_PRIORITY_7_1 WEIGHT_0
ENUM_PRIORITY_7_2 WEIGHT_0
ENUM_PRIORITY_7_3 WEIGHT_0
ENUM_PRIORITY_7_4 WEIGHT_0
ENUM_PRIORITY_7_5 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0
ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1
ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1
ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1
ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1
ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1
ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1
ENUM_RD_DWIDTH_0 DWIDTH_256
ENUM_RD_DWIDTH_1 DWIDTH_0
ENUM_RD_DWIDTH_2 DWIDTH_0
ENUM_RD_DWIDTH_3 DWIDTH_0
ENUM_RD_DWIDTH_4 DWIDTH_0
ENUM_RD_DWIDTH_5 DWIDTH_0
ENUM_RD_FIFO_IN_USE_0 TRUE
ENUM_RD_FIFO_IN_USE_1 TRUE
ENUM_RD_FIFO_IN_USE_2 TRUE
ENUM_RD_FIFO_IN_USE_3 TRUE
ENUM_RD_PORT_INFO_0 USE_0_1_2_3
ENUM_RD_PORT_INFO_1 USE_NO
ENUM_RD_PORT_INFO_2 USE_NO
ENUM_RD_PORT_INFO_3 USE_NO
ENUM_RD_PORT_INFO_4 USE_NO
ENUM_RD_PORT_INFO_5 USE_NO
ENUM_READ_ODT_CHIP ODT_DISABLED
ENUM_REORDER_DATA NO_DATA_REORDERING
ENUM_RFIFO0_CPORT_MAP CMD_PORT_0
ENUM_RFIFO1_CPORT_MAP CMD_PORT_0
ENUM_RFIFO2_CPORT_MAP CMD_PORT_0
ENUM_RFIFO3_CPORT_MAP CMD_PORT_0
ENUM_SINGLE_READY_0 CONCATENATE_RDY
ENUM_SINGLE_READY_1 CONCATENATE_RDY
ENUM_SINGLE_READY_2 CONCATENATE_RDY
ENUM_SINGLE_READY_3 CONCATENATE_RDY
ENUM_STATIC_WEIGHT_0 WEIGHT_0
ENUM_STATIC_WEIGHT_1 WEIGHT_0
ENUM_STATIC_WEIGHT_2 WEIGHT_0
ENUM_STATIC_WEIGHT_3 WEIGHT_0
ENUM_STATIC_WEIGHT_4 WEIGHT_0
ENUM_STATIC_WEIGHT_5 WEIGHT_0
ENUM_SYNC_MODE_0 ASYNCHRONOUS
ENUM_SYNC_MODE_1 ASYNCHRONOUS
ENUM_SYNC_MODE_2 ASYNCHRONOUS
ENUM_SYNC_MODE_3 ASYNCHRONOUS
ENUM_SYNC_MODE_4 ASYNCHRONOUS
ENUM_SYNC_MODE_5 ASYNCHRONOUS
ENUM_TEST_MODE NORMAL_MODE
ENUM_THLD_JAR1_0 THRESHOLD_32
ENUM_THLD_JAR1_1 THRESHOLD_32
ENUM_THLD_JAR1_2 THRESHOLD_32
ENUM_THLD_JAR1_3 THRESHOLD_32
ENUM_THLD_JAR1_4 THRESHOLD_32
ENUM_THLD_JAR1_5 THRESHOLD_32
ENUM_THLD_JAR2_0 THRESHOLD_16
ENUM_THLD_JAR2_1 THRESHOLD_16
ENUM_THLD_JAR2_2 THRESHOLD_16
ENUM_THLD_JAR2_3 THRESHOLD_16
ENUM_THLD_JAR2_4 THRESHOLD_16
ENUM_THLD_JAR2_5 THRESHOLD_16
ENUM_USE_ALMOST_EMPTY_0 EMPTY
ENUM_USE_ALMOST_EMPTY_1 EMPTY
ENUM_USE_ALMOST_EMPTY_2 EMPTY
ENUM_USE_ALMOST_EMPTY_3 EMPTY
ENUM_USER_ECC_EN DISABLE
ENUM_USER_PRIORITY_0 PRIORITY_1
ENUM_USER_PRIORITY_1 PRIORITY_1
ENUM_USER_PRIORITY_2 PRIORITY_1
ENUM_USER_PRIORITY_3 PRIORITY_1
ENUM_USER_PRIORITY_4 PRIORITY_1
ENUM_USER_PRIORITY_5 PRIORITY_1
ENUM_WFIFO0_CPORT_MAP CMD_PORT_0
ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL
ENUM_WFIFO1_CPORT_MAP CMD_PORT_0
ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL
ENUM_WFIFO2_CPORT_MAP CMD_PORT_0
ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL
ENUM_WFIFO3_CPORT_MAP CMD_PORT_0
ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL
ENUM_WR_DWIDTH_0 DWIDTH_256
ENUM_WR_DWIDTH_1 DWIDTH_0
ENUM_WR_DWIDTH_2 DWIDTH_0
ENUM_WR_DWIDTH_3 DWIDTH_0
ENUM_WR_DWIDTH_4 DWIDTH_0
ENUM_WR_DWIDTH_5 DWIDTH_0
ENUM_WR_FIFO_IN_USE_0 TRUE
ENUM_WR_FIFO_IN_USE_1 TRUE
ENUM_WR_FIFO_IN_USE_2 TRUE
ENUM_WR_FIFO_IN_USE_3 TRUE
ENUM_WR_PORT_INFO_0 USE_0_1_2_3
ENUM_WR_PORT_INFO_1 USE_NO
ENUM_WR_PORT_INFO_2 USE_NO
ENUM_WR_PORT_INFO_3 USE_NO
ENUM_WR_PORT_INFO_4 USE_NO
ENUM_WR_PORT_INFO_5 USE_NO
ENUM_WRITE_ODT_CHIP WRITE_CHIP0_ODT0_CHIP1
INTG_MEM_AUTO_PD_CYCLES 0
INTG_CYC_TO_RLD_JARS_0 1
INTG_CYC_TO_RLD_JARS_1 1
INTG_CYC_TO_RLD_JARS_2 1
INTG_CYC_TO_RLD_JARS_3 1
INTG_CYC_TO_RLD_JARS_4 1
INTG_CYC_TO_RLD_JARS_5 1
INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0
INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0
INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0
INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0
INTG_EXTRA_CTL_CLK_ARF_PERIOD 0
INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0
INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0
INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0
INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0
INTG_EXTRA_CTL_CLK_PDN_PERIOD 0
INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0
INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0
INTG_EXTRA_CTL_CLK_RD_TO_PCH 0
INTG_EXTRA_CTL_CLK_RD_TO_RD 0
INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0
INTG_EXTRA_CTL_CLK_RD_TO_WR 2
INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0
INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0
INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0
INTG_EXTRA_CTL_CLK_WR_TO_PCH 0
INTG_EXTRA_CTL_CLK_WR_TO_RD 3
INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3
INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3
INTG_EXTRA_CTL_CLK_WR_TO_WR 0
INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0
INTG_MEM_IF_TREFI 3120
INTG_MEM_IF_TRFC 64
INTG_RCFG_SUM_WT_PRIORITY_0 0
INTG_RCFG_SUM_WT_PRIORITY_1 0
INTG_RCFG_SUM_WT_PRIORITY_2 0
INTG_RCFG_SUM_WT_PRIORITY_3 0
INTG_RCFG_SUM_WT_PRIORITY_4 0
INTG_RCFG_SUM_WT_PRIORITY_5 0
INTG_RCFG_SUM_WT_PRIORITY_6 0
INTG_RCFG_SUM_WT_PRIORITY_7 0
INTG_SUM_WT_PRIORITY_0 0
INTG_SUM_WT_PRIORITY_1 0
INTG_SUM_WT_PRIORITY_2 0
INTG_SUM_WT_PRIORITY_3 0
INTG_SUM_WT_PRIORITY_4 0
INTG_SUM_WT_PRIORITY_5 0
INTG_SUM_WT_PRIORITY_6 0
INTG_SUM_WT_PRIORITY_7 0
VECT_ATTR_COUNTER_ONE_MASK 0
VECT_ATTR_COUNTER_ONE_MATCH 0
VECT_ATTR_COUNTER_ZERO_MASK 0
VECT_ATTR_COUNTER_ZERO_MATCH 0
VECT_ATTR_DEBUG_SELECT_BYTE 0
INTG_POWER_SAVING_EXIT_CYCLES 5
INTG_MEM_CLK_ENTRY_CYCLES 10
ENUM_ENABLE_BURST_INTERRUPT DISABLED
ENUM_ENABLE_BURST_TERMINATE DISABLED
AV_PORT_0_CONNECT_TO_CV_PORT 0
CV_PORT_0_CONNECT_TO_AV_PORT 0
CV_AVL_DATA_WIDTH_PORT_0 256
CV_AVL_ADDR_WIDTH_PORT_0 24
CV_CPORT_TYPE_PORT_0 3
CV_AVL_NUM_SYMBOLS_PORT_0 32
CV_LSB_WFIFO_PORT_0 0
CV_MSB_WFIFO_PORT_0 3
CV_LSB_RFIFO_PORT_0 0
CV_MSB_RFIFO_PORT_0 3
CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED
CV_ENUM_CMD_PORT_IN_USE_0 TRUE
CV_ENUM_CPORT0_RFIFO_MAP FIFO_0
CV_ENUM_CPORT0_TYPE BI_DIRECTION
CV_ENUM_CPORT0_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_0 DISABLED
CV_ENUM_PORT0_WIDTH PORT_256_BIT
CV_ENUM_PRIORITY_0_0 WEIGHT_0
CV_ENUM_PRIORITY_1_0 WEIGHT_0
CV_ENUM_PRIORITY_2_0 WEIGHT_0
CV_ENUM_PRIORITY_3_0 WEIGHT_0
CV_ENUM_PRIORITY_4_0 WEIGHT_0
CV_ENUM_PRIORITY_5_0 WEIGHT_0
CV_ENUM_PRIORITY_6_0 WEIGHT_0
CV_ENUM_PRIORITY_7_0 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1
CV_ENUM_RD_DWIDTH_0 DWIDTH_256
CV_ENUM_RD_PORT_INFO_0 USE_0_1_2_3
CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0
CV_ENUM_USER_PRIORITY_0 PRIORITY_1
CV_ENUM_WR_DWIDTH_0 DWIDTH_256
CV_ENUM_WR_PORT_INFO_0 USE_0_1_2_3
TG_TEMP_PORT_0 3
AV_PORT_1_CONNECT_TO_CV_PORT 1
CV_PORT_1_CONNECT_TO_AV_PORT 1
CV_AVL_DATA_WIDTH_PORT_1 1
CV_AVL_ADDR_WIDTH_PORT_1 1
CV_CPORT_TYPE_PORT_1 0
CV_AVL_NUM_SYMBOLS_PORT_1 1
CV_LSB_WFIFO_PORT_1 5
CV_MSB_WFIFO_PORT_1 5
CV_LSB_RFIFO_PORT_1 5
CV_MSB_RFIFO_PORT_1 5
CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED
CV_ENUM_CMD_PORT_IN_USE_1 FALSE
CV_ENUM_CPORT1_RFIFO_MAP FIFO_0
CV_ENUM_CPORT1_TYPE DISABLE
CV_ENUM_CPORT1_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_1 DISABLED
CV_ENUM_PORT1_WIDTH PORT_32_BIT
CV_ENUM_PRIORITY_0_1 WEIGHT_0
CV_ENUM_PRIORITY_1_1 WEIGHT_0
CV_ENUM_PRIORITY_2_1 WEIGHT_0
CV_ENUM_PRIORITY_3_1 WEIGHT_0
CV_ENUM_PRIORITY_4_1 WEIGHT_0
CV_ENUM_PRIORITY_5_1 WEIGHT_0
CV_ENUM_PRIORITY_6_1 WEIGHT_0
CV_ENUM_PRIORITY_7_1 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1
CV_ENUM_RD_DWIDTH_1 DWIDTH_0
CV_ENUM_RD_PORT_INFO_1 USE_NO
CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0
CV_ENUM_USER_PRIORITY_1 PRIORITY_1
CV_ENUM_WR_DWIDTH_1 DWIDTH_0
CV_ENUM_WR_PORT_INFO_1 USE_NO
TG_TEMP_PORT_1 0
AV_PORT_2_CONNECT_TO_CV_PORT 2
CV_PORT_2_CONNECT_TO_AV_PORT 2
CV_AVL_DATA_WIDTH_PORT_2 1
CV_AVL_ADDR_WIDTH_PORT_2 1
CV_CPORT_TYPE_PORT_2 0
CV_AVL_NUM_SYMBOLS_PORT_2 1
CV_LSB_WFIFO_PORT_2 5
CV_MSB_WFIFO_PORT_2 5
CV_LSB_RFIFO_PORT_2 5
CV_MSB_RFIFO_PORT_2 5
CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED
CV_ENUM_CMD_PORT_IN_USE_2 FALSE
CV_ENUM_CPORT2_RFIFO_MAP FIFO_0
CV_ENUM_CPORT2_TYPE DISABLE
CV_ENUM_CPORT2_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_2 DISABLED
CV_ENUM_PORT2_WIDTH PORT_32_BIT
CV_ENUM_PRIORITY_0_2 WEIGHT_0
CV_ENUM_PRIORITY_1_2 WEIGHT_0
CV_ENUM_PRIORITY_2_2 WEIGHT_0
CV_ENUM_PRIORITY_3_2 WEIGHT_0
CV_ENUM_PRIORITY_4_2 WEIGHT_0
CV_ENUM_PRIORITY_5_2 WEIGHT_0
CV_ENUM_PRIORITY_6_2 WEIGHT_0
CV_ENUM_PRIORITY_7_2 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1
CV_ENUM_RD_DWIDTH_2 DWIDTH_0
CV_ENUM_RD_PORT_INFO_2 USE_NO
CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0
CV_ENUM_USER_PRIORITY_2 PRIORITY_1
CV_ENUM_WR_DWIDTH_2 DWIDTH_0
CV_ENUM_WR_PORT_INFO_2 USE_NO
TG_TEMP_PORT_2 0
AV_PORT_3_CONNECT_TO_CV_PORT 3
CV_PORT_3_CONNECT_TO_AV_PORT 3
CV_AVL_DATA_WIDTH_PORT_3 1
CV_AVL_ADDR_WIDTH_PORT_3 1
CV_CPORT_TYPE_PORT_3 0
CV_AVL_NUM_SYMBOLS_PORT_3 1
CV_LSB_WFIFO_PORT_3 5
CV_MSB_WFIFO_PORT_3 5
CV_LSB_RFIFO_PORT_3 5
CV_MSB_RFIFO_PORT_3 5
CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED
CV_ENUM_CMD_PORT_IN_USE_3 FALSE
CV_ENUM_CPORT3_RFIFO_MAP FIFO_0
CV_ENUM_CPORT3_TYPE DISABLE
CV_ENUM_CPORT3_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_3 DISABLED
CV_ENUM_PORT3_WIDTH PORT_32_BIT
CV_ENUM_PRIORITY_0_3 WEIGHT_0
CV_ENUM_PRIORITY_1_3 WEIGHT_0
CV_ENUM_PRIORITY_2_3 WEIGHT_0
CV_ENUM_PRIORITY_3_3 WEIGHT_0
CV_ENUM_PRIORITY_4_3 WEIGHT_0
CV_ENUM_PRIORITY_5_3 WEIGHT_0
CV_ENUM_PRIORITY_6_3 WEIGHT_0
CV_ENUM_PRIORITY_7_3 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1
CV_ENUM_RD_DWIDTH_3 DWIDTH_0
CV_ENUM_RD_PORT_INFO_3 USE_NO
CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0
CV_ENUM_USER_PRIORITY_3 PRIORITY_1
CV_ENUM_WR_DWIDTH_3 DWIDTH_0
CV_ENUM_WR_PORT_INFO_3 USE_NO
TG_TEMP_PORT_3 0
AV_PORT_4_CONNECT_TO_CV_PORT 4
CV_PORT_4_CONNECT_TO_AV_PORT 4
CV_AVL_DATA_WIDTH_PORT_4 1
CV_AVL_ADDR_WIDTH_PORT_4 1
CV_CPORT_TYPE_PORT_4 0
CV_AVL_NUM_SYMBOLS_PORT_4 1
CV_LSB_WFIFO_PORT_4 5
CV_MSB_WFIFO_PORT_4 5
CV_LSB_RFIFO_PORT_4 5
CV_MSB_RFIFO_PORT_4 5
CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED
CV_ENUM_CMD_PORT_IN_USE_4 FALSE
CV_ENUM_CPORT4_RFIFO_MAP FIFO_0
CV_ENUM_CPORT4_TYPE DISABLE
CV_ENUM_CPORT4_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_4 DISABLED
CV_ENUM_PORT4_WIDTH PORT_32_BIT
CV_ENUM_PRIORITY_0_4 WEIGHT_0
CV_ENUM_PRIORITY_1_4 WEIGHT_0
CV_ENUM_PRIORITY_2_4 WEIGHT_0
CV_ENUM_PRIORITY_3_4 WEIGHT_0
CV_ENUM_PRIORITY_4_4 WEIGHT_0
CV_ENUM_PRIORITY_5_4 WEIGHT_0
CV_ENUM_PRIORITY_6_4 WEIGHT_0
CV_ENUM_PRIORITY_7_4 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1
CV_ENUM_RD_DWIDTH_4 DWIDTH_0
CV_ENUM_RD_PORT_INFO_4 USE_NO
CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0
CV_ENUM_USER_PRIORITY_4 PRIORITY_1
CV_ENUM_WR_DWIDTH_4 DWIDTH_0
CV_ENUM_WR_PORT_INFO_4 USE_NO
TG_TEMP_PORT_4 0
AV_PORT_5_CONNECT_TO_CV_PORT 5
CV_PORT_5_CONNECT_TO_AV_PORT 5
CV_AVL_DATA_WIDTH_PORT_5 1
CV_AVL_ADDR_WIDTH_PORT_5 1
CV_CPORT_TYPE_PORT_5 0
CV_AVL_NUM_SYMBOLS_PORT_5 1
CV_LSB_WFIFO_PORT_5 5
CV_MSB_WFIFO_PORT_5 5
CV_LSB_RFIFO_PORT_5 5
CV_MSB_RFIFO_PORT_5 5
CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED
CV_ENUM_CMD_PORT_IN_USE_5 FALSE
CV_ENUM_CPORT5_RFIFO_MAP FIFO_0
CV_ENUM_CPORT5_TYPE DISABLE
CV_ENUM_CPORT5_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_5 DISABLED
CV_ENUM_PORT5_WIDTH PORT_32_BIT
CV_ENUM_PRIORITY_0_5 WEIGHT_0
CV_ENUM_PRIORITY_1_5 WEIGHT_0
CV_ENUM_PRIORITY_2_5 WEIGHT_0
CV_ENUM_PRIORITY_3_5 WEIGHT_0
CV_ENUM_PRIORITY_4_5 WEIGHT_0
CV_ENUM_PRIORITY_5_5 WEIGHT_0
CV_ENUM_PRIORITY_6_5 WEIGHT_0
CV_ENUM_PRIORITY_7_5 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1
CV_ENUM_RD_DWIDTH_5 DWIDTH_0
CV_ENUM_RD_PORT_INFO_5 USE_NO
CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0
CV_ENUM_USER_PRIORITY_5 PRIORITY_1
CV_ENUM_WR_DWIDTH_5 DWIDTH_0
CV_ENUM_WR_PORT_INFO_5 USE_NO
TG_TEMP_PORT_5 0
CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0
CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0
CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0
CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0
CV_INTG_RCFG_SUM_WT_PRIORITY_0 0
CV_INTG_SUM_WT_PRIORITY_0 0
CV_INTG_RCFG_SUM_WT_PRIORITY_1 0
CV_INTG_SUM_WT_PRIORITY_1 0
CV_INTG_RCFG_SUM_WT_PRIORITY_2 0
CV_INTG_SUM_WT_PRIORITY_2 0
CV_INTG_RCFG_SUM_WT_PRIORITY_3 0
CV_INTG_SUM_WT_PRIORITY_3 0
CV_INTG_RCFG_SUM_WT_PRIORITY_4 0
CV_INTG_SUM_WT_PRIORITY_4 0
CV_INTG_RCFG_SUM_WT_PRIORITY_5 0
CV_INTG_SUM_WT_PRIORITY_5 0
CV_INTG_RCFG_SUM_WT_PRIORITY_6 0
CV_INTG_SUM_WT_PRIORITY_6 0
CV_INTG_RCFG_SUM_WT_PRIORITY_7 0
CV_INTG_SUM_WT_PRIORITY_7 0
CONTINUE_AFTER_CAL_FAIL false
POWER_OF_TWO_BUS true
SOPC_COMPAT_RESET false
AVL_MAX_SIZE 128
BYTE_ENABLE false
ENABLE_CTRL_AVALON_INTERFACE true
CTL_DEEP_POWERDN_EN false
CTL_SELF_REFRESH_EN false
AUTO_POWERDN_EN false
AUTO_PD_CYCLES 0
CTL_USR_REFRESH_EN false
CTL_AUTOPCH_EN false
CTL_ZQCAL_EN false
ADDR_ORDER 0
CTL_LOOK_AHEAD_DEPTH 4
CONTROLLER_LATENCY 5
CFG_REORDER_DATA false
STARVE_LIMIT 10
CTL_CSR_ENABLED true
CTL_CSR_CONNECTION EXPORT
CTL_ECC_ENABLED true
CTL_HRB_ENABLED false
CTL_ECC_AUTO_CORRECTION_ENABLED false
MULTICAST_EN false
CTL_DYNAMIC_BANK_ALLOCATION false
CTL_DYNAMIC_BANK_NUM 4
DEBUG_MODE false
ENABLE_BURST_MERGE false
CTL_ENABLE_BURST_INTERRUPT true
CTL_ENABLE_BURST_TERMINATE true
LOCAL_ID_WIDTH 8
RDBUFFER_ADDR_WIDTH 8
WRBUFFER_ADDR_WIDTH 6
MAX_PENDING_WR_CMD 8
MAX_PENDING_RD_CMD 16
USE_MM_ADAPTOR true
USE_AXI_ADAPTOR false
HCX_COMPAT_MODE false
CTL_CMD_QUEUE_DEPTH 8
CTL_CSR_READ_ONLY 1
CFG_DATA_REORDERING_TYPE INTER_BANK
NUM_OF_PORTS 1
ENABLE_BONDING false
ENABLE_USER_ECC false
AVL_DATA_WIDTH_PORT 256,32,32,32,32,32
PRIORITY_PORT 1,1,1,1,1,1
WEIGHT_PORT 0,0,0,0,0,0
CPORT_TYPE_PORT Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional
CORE_PERIPHERY_DUAL_CLOCK false
USE_DR_CLK true
DLL_USE_DR_CLK true
USE_2X_FF false
DUAL_WRITE_CLOCK false
GENERIC_PLL true
USE_HARD_READ_FIFO false
READ_FIFO_HALF_RATE false
PLL_MASTER true
DLL_MASTER true
PHY_VERSION_NUMBER 131
ENABLE_NIOS_OCI false
ENABLE_EMIT_JTAG_MASTER true
ENABLE_NIOS_JTAG_UART false
ENABLE_NIOS_PRINTF_OUTPUT false
ENABLE_LARGE_RW_MGR_DI_BUFFER false
ENABLE_EMIT_BFM_MASTER false
FORCE_SEQUENCER_TCL_DEBUG_MODE false
ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false
ENABLE_MAX_SIZE_SEQ_MEM false
MAKE_INTERNAL_NIOS_VISIBLE false
DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false
ENABLE_CSR_SOFT_RESET_REQ true
DUPLICATE_PLL_FOR_PHY_CLK true
MAX_LATENCY_COUNT_WIDTH 5
READ_VALID_FIFO_SIZE 16
EXTRA_VFIFO_SHIFT 0
TB_MEM_CLK_FREQ 400.0
TB_RATE FULL
TB_MEM_IF_DQ_WIDTH 40
TB_MEM_IF_READ_DQS_WIDTH 5
TB_PLL_DLL_MASTER true
FAST_SIM_CALIBRATION false
REF_CLK_FREQ 100.0
REF_CLK_FREQ_STR 100.0 MHz
REF_CLK_NS 10.0
REF_CLK_PS 10000.0
PLL_DR_CLK_FREQ 800.0
PLL_DR_CLK_FREQ_STR 800.0 MHz
PLL_DR_CLK_FREQ_SIM_STR 1250 ps
PLL_DR_CLK_PHASE_PS 0
PLL_DR_CLK_PHASE_PS_STR 0 ps
PLL_DR_CLK_PHASE_DEG 0.0
PLL_DR_CLK_PHASE_PS_SIM 0
PLL_DR_CLK_PHASE_PS_SIM_STR 0 ps
PLL_DR_CLK_PHASE_DEG_SIM 0.0
PLL_DR_CLK_MULT 8000000
PLL_DR_CLK_DIV 1000000
PLL_MEM_CLK_FREQ 400.0
PLL_MEM_CLK_FREQ_STR 400.0 MHz
PLL_MEM_CLK_FREQ_SIM_STR 2500 ps
PLL_MEM_CLK_PHASE_PS 0
PLL_MEM_CLK_PHASE_PS_STR 0 ps
PLL_MEM_CLK_PHASE_DEG 0.0
PLL_MEM_CLK_PHASE_PS_SIM 0
PLL_MEM_CLK_PHASE_PS_SIM_STR 0 ps
PLL_MEM_CLK_PHASE_DEG_SIM 0.0
PLL_MEM_CLK_MULT 8000000
PLL_MEM_CLK_DIV 2000000
PLL_AFI_CLK_FREQ 400.0
PLL_AFI_CLK_FREQ_STR 400.0 MHz
PLL_AFI_CLK_FREQ_SIM_STR 2500 ps
PLL_AFI_CLK_PHASE_PS 0
PLL_AFI_CLK_PHASE_PS_STR 0 ps
PLL_AFI_CLK_PHASE_DEG 0.0
PLL_AFI_CLK_PHASE_PS_SIM 0
PLL_AFI_CLK_PHASE_PS_SIM_STR 0 ps
PLL_AFI_CLK_PHASE_DEG_SIM 0.0
PLL_AFI_CLK_MULT 8000000
PLL_AFI_CLK_DIV 2000000
PLL_WRITE_CLK_FREQ 400.0
PLL_WRITE_CLK_FREQ_STR 400.0 MHz
PLL_WRITE_CLK_FREQ_SIM_STR 2500 ps
PLL_WRITE_CLK_PHASE_PS 1875
PLL_WRITE_CLK_PHASE_PS_STR 1875 ps
PLL_WRITE_CLK_PHASE_DEG 270.0
PLL_WRITE_CLK_PHASE_PS_SIM 1875
PLL_WRITE_CLK_PHASE_PS_SIM_STR 1875 ps
PLL_WRITE_CLK_PHASE_DEG_SIM 270.0
PLL_WRITE_CLK_MULT 8000000
PLL_WRITE_CLK_DIV 2000000
PLL_ADDR_CMD_CLK_FREQ 400.0
PLL_ADDR_CMD_CLK_FREQ_STR 400.0 MHz
PLL_ADDR_CMD_CLK_FREQ_SIM_STR 2500 ps
PLL_ADDR_CMD_CLK_PHASE_PS 1875
PLL_ADDR_CMD_CLK_PHASE_PS_STR 1875 ps
PLL_ADDR_CMD_CLK_PHASE_DEG 270.0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM 1875
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR 1875 ps
PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0
PLL_ADDR_CMD_CLK_MULT 8000000
PLL_ADDR_CMD_CLK_DIV 2000000
PLL_AFI_HALF_CLK_FREQ 200.0
PLL_AFI_HALF_CLK_FREQ_STR 200.0 MHz
PLL_AFI_HALF_CLK_FREQ_SIM_STR 5000 ps
PLL_AFI_HALF_CLK_PHASE_PS 0
PLL_AFI_HALF_CLK_PHASE_PS_STR 0 ps
PLL_AFI_HALF_CLK_PHASE_DEG 0.0
PLL_AFI_HALF_CLK_PHASE_PS_SIM 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR 0 ps
PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0
PLL_AFI_HALF_CLK_MULT 8000000
PLL_AFI_HALF_CLK_DIV 4000000
PLL_NIOS_CLK_FREQ 66.666666
PLL_NIOS_CLK_FREQ_STR 66.666666 MHz
PLL_NIOS_CLK_FREQ_SIM_STR 15000 ps
PLL_NIOS_CLK_PHASE_PS 468
PLL_NIOS_CLK_PHASE_PS_STR 468 ps
PLL_NIOS_CLK_PHASE_DEG 11.0
PLL_NIOS_CLK_PHASE_PS_SIM 417
PLL_NIOS_CLK_PHASE_PS_SIM_STR 417 ps
PLL_NIOS_CLK_PHASE_DEG_SIM 10.0
PLL_NIOS_CLK_MULT 8000000
PLL_NIOS_CLK_DIV 12000000
PLL_CONFIG_CLK_FREQ 22.222222
PLL_CONFIG_CLK_FREQ_STR 22.222222 MHz
PLL_CONFIG_CLK_FREQ_SIM_STR 45000 ps
PLL_CONFIG_CLK_PHASE_PS 0
PLL_CONFIG_CLK_PHASE_PS_STR 0 ps
PLL_CONFIG_CLK_PHASE_DEG 0.0
PLL_CONFIG_CLK_PHASE_PS_SIM 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR 0 ps
PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0
PLL_CONFIG_CLK_MULT 8000000
PLL_CONFIG_CLK_DIV 36000000
PLL_P2C_READ_CLK_FREQ 0.0
PLL_P2C_READ_CLK_FREQ_STR
PLL_P2C_READ_CLK_FREQ_SIM_STR 0 ps
PLL_P2C_READ_CLK_PHASE_PS 0
PLL_P2C_READ_CLK_PHASE_PS_STR
PLL_P2C_READ_CLK_PHASE_DEG 0.0
PLL_P2C_READ_CLK_PHASE_PS_SIM 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR
PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0
PLL_P2C_READ_CLK_MULT 0
PLL_P2C_READ_CLK_DIV 0
PLL_C2P_WRITE_CLK_FREQ 0.0
PLL_C2P_WRITE_CLK_FREQ_STR
PLL_C2P_WRITE_CLK_FREQ_SIM_STR 0 ps
PLL_C2P_WRITE_CLK_PHASE_PS 0
PLL_C2P_WRITE_CLK_PHASE_PS_STR
PLL_C2P_WRITE_CLK_PHASE_DEG 0.0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR
PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0
PLL_C2P_WRITE_CLK_MULT 0
PLL_C2P_WRITE_CLK_DIV 0
PLL_HR_CLK_FREQ 0.0
PLL_HR_CLK_FREQ_STR
PLL_HR_CLK_FREQ_SIM_STR 0 ps
PLL_HR_CLK_PHASE_PS 0
PLL_HR_CLK_PHASE_PS_STR
PLL_HR_CLK_PHASE_DEG 0.0
PLL_HR_CLK_PHASE_PS_SIM 0
PLL_HR_CLK_PHASE_PS_SIM_STR
PLL_HR_CLK_PHASE_DEG_SIM 0.0
PLL_HR_CLK_MULT 0
PLL_HR_CLK_DIV 0
PLL_AFI_PHY_CLK_FREQ 400.0
PLL_AFI_PHY_CLK_FREQ_STR 400.0 MHz
PLL_AFI_PHY_CLK_FREQ_SIM_STR 2500 ps
PLL_AFI_PHY_CLK_PHASE_PS 0
PLL_AFI_PHY_CLK_PHASE_PS_STR 0 ps
PLL_AFI_PHY_CLK_PHASE_DEG 0.0
PLL_AFI_PHY_CLK_PHASE_PS_SIM 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR 0 ps
PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0
PLL_AFI_PHY_CLK_MULT 8000000
PLL_AFI_PHY_CLK_DIV 2000000
REF_CLK_FREQ_CACHE_VALID true
REF_CLK_FREQ_PARAM_VALID false
REF_CLK_FREQ_MIN_PARAM 0.0
REF_CLK_FREQ_MAX_PARAM 0.0
REF_CLK_FREQ_MIN_CACHE 10.0
REF_CLK_FREQ_MAX_CACHE 500.0
PLL_DR_CLK_FREQ_PARAM 0.0
PLL_DR_CLK_FREQ_SIM_STR_PARAM
PLL_DR_CLK_PHASE_PS_PARAM 0
PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM
PLL_DR_CLK_MULT_PARAM 0
PLL_DR_CLK_DIV_PARAM 0
PLL_DR_CLK_FREQ_CACHE 800.0
PLL_DR_CLK_FREQ_SIM_STR_CACHE 1250 ps
PLL_DR_CLK_PHASE_PS_CACHE 0
PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_DR_CLK_MULT_CACHE 8000000
PLL_DR_CLK_DIV_CACHE 1000000
PLL_MEM_CLK_FREQ_PARAM 0.0
PLL_MEM_CLK_FREQ_SIM_STR_PARAM
PLL_MEM_CLK_PHASE_PS_PARAM 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM
PLL_MEM_CLK_MULT_PARAM 0
PLL_MEM_CLK_DIV_PARAM 0
PLL_MEM_CLK_FREQ_CACHE 400.0
PLL_MEM_CLK_FREQ_SIM_STR_CACHE 2500 ps
PLL_MEM_CLK_PHASE_PS_CACHE 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_MEM_CLK_MULT_CACHE 8000000
PLL_MEM_CLK_DIV_CACHE 2000000
PLL_AFI_CLK_FREQ_PARAM 0.0
PLL_AFI_CLK_FREQ_SIM_STR_PARAM
PLL_AFI_CLK_PHASE_PS_PARAM 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM
PLL_AFI_CLK_MULT_PARAM 0
PLL_AFI_CLK_DIV_PARAM 0
PLL_AFI_CLK_FREQ_CACHE 400.0
PLL_AFI_CLK_FREQ_SIM_STR_CACHE 2500 ps
PLL_AFI_CLK_PHASE_PS_CACHE 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_AFI_CLK_MULT_CACHE 8000000
PLL_AFI_CLK_DIV_CACHE 2000000
PLL_WRITE_CLK_FREQ_PARAM 0.0
PLL_WRITE_CLK_FREQ_SIM_STR_PARAM
PLL_WRITE_CLK_PHASE_PS_PARAM 0
PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM
PLL_WRITE_CLK_MULT_PARAM 0
PLL_WRITE_CLK_DIV_PARAM 0
PLL_WRITE_CLK_FREQ_CACHE 400.0
PLL_WRITE_CLK_FREQ_SIM_STR_CACHE 2500 ps
PLL_WRITE_CLK_PHASE_PS_CACHE 1875
PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE 1875 ps
PLL_WRITE_CLK_MULT_CACHE 8000000
PLL_WRITE_CLK_DIV_CACHE 2000000
PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM
PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM
PLL_ADDR_CMD_CLK_MULT_PARAM 0
PLL_ADDR_CMD_CLK_DIV_PARAM 0
PLL_ADDR_CMD_CLK_FREQ_CACHE 400.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE 2500 ps
PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 1875
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE 1875 ps
PLL_ADDR_CMD_CLK_MULT_CACHE 8000000
PLL_ADDR_CMD_CLK_DIV_CACHE 2000000
PLL_AFI_HALF_CLK_FREQ_PARAM 0.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM
PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM
PLL_AFI_HALF_CLK_MULT_PARAM 0
PLL_AFI_HALF_CLK_DIV_PARAM 0
PLL_AFI_HALF_CLK_FREQ_CACHE 200.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE 5000 ps
PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_AFI_HALF_CLK_MULT_CACHE 8000000
PLL_AFI_HALF_CLK_DIV_CACHE 4000000
PLL_NIOS_CLK_FREQ_PARAM 0.0
PLL_NIOS_CLK_FREQ_SIM_STR_PARAM
PLL_NIOS_CLK_PHASE_PS_PARAM 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM
PLL_NIOS_CLK_MULT_PARAM 0
PLL_NIOS_CLK_DIV_PARAM 0
PLL_NIOS_CLK_FREQ_CACHE 66.666666
PLL_NIOS_CLK_FREQ_SIM_STR_CACHE 15000 ps
PLL_NIOS_CLK_PHASE_PS_CACHE 468
PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE 417 ps
PLL_NIOS_CLK_MULT_CACHE 8000000
PLL_NIOS_CLK_DIV_CACHE 12000000
PLL_CONFIG_CLK_FREQ_PARAM 0.0
PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM
PLL_CONFIG_CLK_PHASE_PS_PARAM 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM
PLL_CONFIG_CLK_MULT_PARAM 0
PLL_CONFIG_CLK_DIV_PARAM 0
PLL_CONFIG_CLK_FREQ_CACHE 22.222222
PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE 45000 ps
PLL_CONFIG_CLK_PHASE_PS_CACHE 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_CONFIG_CLK_MULT_CACHE 8000000
PLL_CONFIG_CLK_DIV_CACHE 36000000
PLL_P2C_READ_CLK_FREQ_PARAM 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM
PLL_P2C_READ_CLK_PHASE_PS_PARAM 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM
PLL_P2C_READ_CLK_MULT_PARAM 0
PLL_P2C_READ_CLK_DIV_PARAM 0
PLL_P2C_READ_CLK_FREQ_CACHE 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE
PLL_P2C_READ_CLK_PHASE_PS_CACHE 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE
PLL_P2C_READ_CLK_MULT_CACHE 0
PLL_P2C_READ_CLK_DIV_CACHE 0
PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM
PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM
PLL_C2P_WRITE_CLK_MULT_PARAM 0
PLL_C2P_WRITE_CLK_DIV_PARAM 0
PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE
PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE
PLL_C2P_WRITE_CLK_MULT_CACHE 0
PLL_C2P_WRITE_CLK_DIV_CACHE 0
PLL_HR_CLK_FREQ_PARAM 0.0
PLL_HR_CLK_FREQ_SIM_STR_PARAM
PLL_HR_CLK_PHASE_PS_PARAM 0
PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM
PLL_HR_CLK_MULT_PARAM 0
PLL_HR_CLK_DIV_PARAM 0
PLL_HR_CLK_FREQ_CACHE 0.0
PLL_HR_CLK_FREQ_SIM_STR_CACHE
PLL_HR_CLK_PHASE_PS_CACHE 0
PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE
PLL_HR_CLK_MULT_CACHE 0
PLL_HR_CLK_DIV_CACHE 0
PLL_AFI_PHY_CLK_FREQ_PARAM 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM
PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM
PLL_AFI_PHY_CLK_MULT_PARAM 0
PLL_AFI_PHY_CLK_DIV_PARAM 0
PLL_AFI_PHY_CLK_FREQ_CACHE 400.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE 2500 ps
PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_AFI_PHY_CLK_MULT_CACHE 8000000
PLL_AFI_PHY_CLK_DIV_CACHE 2000000
SPEED_GRADE_CACHE 7
IS_ES_DEVICE_CACHE false
MEM_CLK_FREQ_CACHE 400.0
REF_CLK_FREQ_CACHE 100.0
RATE_CACHE Full
HCX_COMPAT_MODE_CACHE false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV
COMMAND_PHASE_CACHE 0.0
MEM_CK_PHASE_CACHE 0.0
P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0
C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0
ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0
SEQUENCER_TYPE_CACHE NIOS
USE_MEM_CLK_FREQ_CACHE false
PLL_CLK_CACHE_VALID true
PLL_CLK_PARAM_VALID false
ENABLE_EXTRA_REPORTING false
NUM_EXTRA_REPORT_PATH 10
ENABLE_ISS_PROBES false
CALIB_REG_WIDTH 8
USE_SEQUENCER_BFM false
DEFAULT_FAST_SIM_MODEL true
PLL_SHARING_MODE None
NUM_PLL_SHARING_INTERFACES 1
EXPORT_AFI_HALF_CLK false
ABSTRACT_REAL_COMPARE_TEST false
INCLUDE_BOARD_DELAY_MODEL false
INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false
USE_FAKE_PHY_INTERNAL false
USE_FAKE_PHY false
FORCE_MAX_LATENCY_COUNT_WIDTH 0
USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false
ENABLE_NON_DESTRUCTIVE_CALIB false
ENABLE_DELAY_CHAIN_WRITE false
TRACKING_ERROR_TEST false
TRACKING_WATCH_TEST false
MARGIN_VARIATION_TEST false
EXTRA_SETTINGS
MEM_DEVICE MISSING_MODEL
FORCE_SYNTHESIS_LANGUAGE
NUM_SUBGROUP_PER_READ_DQS 1
QVLD_EXTRA_FLOP_STAGES 0
QVLD_WR_ADDRESS_OFFSET 5
MAX_WRITE_LATENCY_COUNT_WIDTH 4
NUM_WRITE_PATH_FLOP_STAGES 1
NUM_AC_FR_CYCLE_SHIFTS 0
FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0
NUM_WRITE_FR_CYCLE_SHIFTS 0
PERFORM_READ_AFTER_WRITE_CALIBRATION true
SEQ_BURST_COUNT_WIDTH 2
VCALIB_COUNT_WIDTH 2
PLL_PHASE_COUNTER_WIDTH 4
DQS_DELAY_CHAIN_PHASE_SETTING 2
DQS_PHASE_SHIFT 9000
DELAYED_CLOCK_PHASE_SETTING 2
IO_DQS_IN_RESERVE 4
IO_DQS_OUT_RESERVE 4
IO_DQ_OUT_RESERVE 0
IO_DM_OUT_RESERVE 0
IO_DQS_EN_DELAY_OFFSET 0
IO_DQS_EN_PHASE_MAX 7
IO_DQDQS_OUT_PHASE_MAX 0
IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false
MEM_CLK_NS 2.5
MEM_CLK_PS 2500.0
CALIB_LFIFO_OFFSET 7
CALIB_VFIFO_OFFSET 5
DELAY_PER_OPA_TAP 312
DELAY_PER_DCHAIN_TAP 25
DELAY_PER_DQS_EN_DCHAIN_TAP 25
DQS_EN_DELAY_MAX 31
DQS_IN_DELAY_MAX 31
IO_IN_DELAY_MAX 31
IO_OUT1_DELAY_MAX 31
IO_OUT2_DELAY_MAX 0
IO_STANDARD SSTL-15
VFIFO_AS_SHIFT_REG true
SEQUENCER_TYPE NIOS
NIOS_HEX_FILE_LOCATION ../
ADVERTIZE_SEQUENCER_SW_BUILD_FILES false
NEGATIVE_WRITE_CK_PHASE true
MEM_T_WL 5
MEM_T_RL 6
PHY_CLKBUF false
USE_LDC_AS_LOW_SKEW_CLOCK false
USE_LDC_FOR_ADDR_CMD false
ENABLE_LDC_MEM_CK_ADJUSTMENT false
MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0
LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true
LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0
FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false
NON_LDC_ADDR_CMD_MEM_CK_INVERT false
REGISTER_C2P false
EARLY_ADDR_CMD_CLK_TRANSFER true
PHY_ONLY false
SEQ_MODE 0
ADVANCED_CK_PHASES false
COMMAND_PHASE 0.0
MEM_CK_PHASE 0.0
P2C_READ_CLOCK_ADD_PHASE 0.0
C2P_WRITE_CLOCK_ADD_PHASE 0.0
ACV_PHY_CLK_ADD_FR_PHASE 0.0
MEM_VOLTAGE 1.5V DDR3
PLL_LOCATION Top_Bottom
SKIP_MEM_INIT true
READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS
DQ_INPUT_REG_USE_CLKN false
DQS_DQSN_MODE DIFFERENTIAL
AFI_DEBUG_INFO_WIDTH 32
CALIBRATION_MODE Skip
NIOS_ROM_DATA_WIDTH 32
NIOS_ROM_ADDRESS_WIDTH 13
READ_FIFO_SIZE 8
PHY_CSR_ENABLED false
PHY_CSR_CONNECTION INTERNAL_JTAG
USER_DEBUG_LEVEL 1
TIMING_BOARD_DERATE_METHOD AUTO
TIMING_BOARD_CK_CKN_SLEW_RATE 2.0
TIMING_BOARD_AC_SLEW_RATE 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0
TIMING_BOARD_DQ_SLEW_RATE 1.0
TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0
TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0
TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0
TIMING_BOARD_TIS 0.0
TIMING_BOARD_TIH 0.0
TIMING_BOARD_TDS 0.0
TIMING_BOARD_TDH 0.0
TIMING_BOARD_TIS_APPLIED 0.32
TIMING_BOARD_TIH_APPLIED 0.22
TIMING_BOARD_TDS_APPLIED 0.16
TIMING_BOARD_TDH_APPLIED 0.145
TIMING_BOARD_ISI_METHOD AUTO
TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H 0.0
TIMING_BOARD_DQ_EYE_REDUCTION 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0
TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0
TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0
PACKAGE_DESKEW false
AC_PACKAGE_DESKEW false
TIMING_BOARD_MAX_CK_DELAY 0.6
TIMING_BOARD_MAX_DQS_DELAY 0.6
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN -0.01
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED -0.01
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.01
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.01
TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05
TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0
TIMING_BOARD_SKEW_WITHIN_DQS 0.02
TIMING_BOARD_SKEW_BETWEEN_DQS 0.02
TIMING_BOARD_DQ_TO_DQS_SKEW 0.0
TIMING_BOARD_AC_SKEW 0.02
TIMING_BOARD_AC_TO_CK_SKEW 0.0
ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false
CORE_DEBUG_CONNECTION EXPORT
ADD_EXTERNAL_SEQ_DEBUG_NIOS false
ED_EXPORT_SEQ_DEBUG false
ADD_EFFICIENCY_MONITOR false
ENABLE_ABS_RAM_MEM_INIT false
ENABLE_ABS_RAM_INTERNAL false
ENABLE_ABSTRACT_RAM false
ABS_RAM_MEM_INIT_FILENAME meminit
DLL_DELAY_CTRL_WIDTH 7
DLL_OFFSET_CTRL_WIDTH 6
DELAY_BUFFER_MODE HIGH
DELAY_CHAIN_LENGTH 8
DLL_SHARING_MODE None
NUM_DLL_SHARING_INTERFACES 1
OCT_TERM_CONTROL_WIDTH 16
OCT_SHARING_MODE Master
NUM_OCT_SHARING_INTERFACES 1
AUTO_DEVICE 5CGTFD9E5F35C7
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

pll_0

altera_pll v13.1
fpga_sdram afi_clk   pll_0
  refclk
refclk clk_reset  
  reset
outclk0   fpga_sdram
  mp_wfifo_clk_0
outclk0  
  mp_rfifo_clk_0
outclk0  
  mp_cmd_clk_0
outclk0  
  mp_rfifo_clk_1
outclk0  
  mp_wfifo_clk_1
outclk0  
  csr_clk
outclk0  
  mp_rfifo_clk_2
outclk0  
  mp_wfifo_clk_2
outclk0  
  mp_rfifo_clk_3
outclk0  
  mp_wfifo_clk_3
outclk0   master_driver_msgdma_0
  clock
outclk0   mSGDMA_0_clk
  clk_in
outclk0   mm_traffic_generator_0
  avl_clock


Parameters

debug_print_output false
debug_use_rbc_taf_method false
device_family CYCLONEV
device 5CGTFD9E5F35C7
gui_device_speed_grade 7
gui_pll_mode Integer-N PLL
fractional_vco_multiplier false
gui_reference_clock_frequency 400.0
reference_clock_frequency 400.0 MHz
gui_channel_spacing 0.0
gui_operation_mode normal
gui_feedback_clock Global Clock
gui_fractional_cout 32
pll_fractional_cout 32
gui_dsm_out_sel 1st_order
pll_dsm_out_sel 1st_order
operation_mode normal
gui_use_locked false
gui_en_adv_params false
gui_number_of_clocks 1
number_of_clocks 1
number_of_cascade_counters 0
gui_multiply_factor 1
gui_frac_multiply_factor 1
gui_divide_factor_n 1
gui_cascade_counter0 false
gui_output_clock_frequency0 100.0
gui_divide_factor_c0 1
gui_actual_multiply_factor0 3
gui_actual_frac_multiply_factor0 1
gui_actual_divide_factor0 12
gui_actual_output_clock_frequency0 0 MHz
gui_ps_units0 ps
gui_phase_shift0 0
gui_phase_shift_deg0 0.0
gui_actual_phase_shift0 0
gui_duty_cycle0 50
gui_cascade_counter1 false
gui_output_clock_frequency1 100.0
gui_divide_factor_c1 1
gui_actual_multiply_factor1 1
gui_actual_frac_multiply_factor1 1
gui_actual_divide_factor1 1
gui_actual_output_clock_frequency1 0 MHz
gui_ps_units1 ps
gui_phase_shift1 0
gui_phase_shift_deg1 0.0
gui_actual_phase_shift1 0
gui_duty_cycle1 50
gui_cascade_counter2 false
gui_output_clock_frequency2 100.0
gui_divide_factor_c2 1
gui_actual_multiply_factor2 1
gui_actual_frac_multiply_factor2 1
gui_actual_divide_factor2 1
gui_actual_output_clock_frequency2 0 MHz
gui_ps_units2 ps
gui_phase_shift2 0
gui_phase_shift_deg2 0.0
gui_actual_phase_shift2 0
gui_duty_cycle2 50
gui_cascade_counter3 false
gui_output_clock_frequency3 100.0
gui_divide_factor_c3 1
gui_actual_multiply_factor3 1
gui_actual_frac_multiply_factor3 1
gui_actual_divide_factor3 1
gui_actual_output_clock_frequency3 0 MHz
gui_ps_units3 ps
gui_phase_shift3 0
gui_phase_shift_deg3 0.0
gui_actual_phase_shift3 0
gui_duty_cycle3 50
gui_cascade_counter4 false
gui_output_clock_frequency4 100.0
gui_divide_factor_c4 1
gui_actual_multiply_factor4 1
gui_actual_frac_multiply_factor4 1
gui_actual_divide_factor4 1
gui_actual_output_clock_frequency4 0 MHz
gui_ps_units4 ps
gui_phase_shift4 0
gui_phase_shift_deg4 0.0
gui_actual_phase_shift4 0
gui_duty_cycle4 50
gui_cascade_counter5 false
gui_output_clock_frequency5 100.0
gui_divide_factor_c5 1
gui_actual_multiply_factor5 1
gui_actual_frac_multiply_factor5 1
gui_actual_divide_factor5 1
gui_actual_output_clock_frequency5 0 MHz
gui_ps_units5 ps
gui_phase_shift5 0
gui_phase_shift_deg5 0.0
gui_actual_phase_shift5 0
gui_duty_cycle5 50
gui_cascade_counter6 false
gui_output_clock_frequency6 100.0
gui_divide_factor_c6 1
gui_actual_multiply_factor6 1
gui_actual_frac_multiply_factor6 1
gui_actual_divide_factor6 1
gui_actual_output_clock_frequency6 0 MHz
gui_ps_units6 ps
gui_phase_shift6 0
gui_phase_shift_deg6 0.0
gui_actual_phase_shift6 0
gui_duty_cycle6 50
gui_cascade_counter7 false
gui_output_clock_frequency7 100.0
gui_divide_factor_c7 1
gui_actual_multiply_factor7 1
gui_actual_frac_multiply_factor7 1
gui_actual_divide_factor7 1
gui_actual_output_clock_frequency7 0 MHz
gui_ps_units7 ps
gui_phase_shift7 0
gui_phase_shift_deg7 0.0
gui_actual_phase_shift7 0
gui_duty_cycle7 50
gui_cascade_counter8 false
gui_output_clock_frequency8 100.0
gui_divide_factor_c8 1
gui_actual_multiply_factor8 1
gui_actual_frac_multiply_factor8 1
gui_actual_divide_factor8 1
gui_actual_output_clock_frequency8 0 MHz
gui_ps_units8 ps
gui_phase_shift8 0
gui_phase_shift_deg8 0.0
gui_actual_phase_shift8 0
gui_duty_cycle8 50
gui_cascade_counter9 false
gui_output_clock_frequency9 100.0
gui_divide_factor_c9 1
gui_actual_multiply_factor9 1
gui_actual_frac_multiply_factor9 1
gui_actual_divide_factor9 1
gui_actual_output_clock_frequency9 0 MHz
gui_ps_units9 ps
gui_phase_shift9 0
gui_phase_shift_deg9 0.0
gui_actual_phase_shift9 0
gui_duty_cycle9 50
gui_cascade_counter10 false
gui_output_clock_frequency10 100.0
gui_divide_factor_c10 1
gui_actual_multiply_factor10 1
gui_actual_frac_multiply_factor10 1
gui_actual_divide_factor10 1
gui_actual_output_clock_frequency10 0 MHz
gui_ps_units10 ps
gui_phase_shift10 0
gui_phase_shift_deg10 0.0
gui_actual_phase_shift10 0
gui_duty_cycle10 50
gui_cascade_counter11 false
gui_output_clock_frequency11 100.0
gui_divide_factor_c11 1
gui_actual_multiply_factor11 1
gui_actual_frac_multiply_factor11 1
gui_actual_divide_factor11 1
gui_actual_output_clock_frequency11 0 MHz
gui_ps_units11 ps
gui_phase_shift11 0
gui_phase_shift_deg11 0.0
gui_actual_phase_shift11 0
gui_duty_cycle11 50
gui_cascade_counter12 false
gui_output_clock_frequency12 100.0
gui_divide_factor_c12 1
gui_actual_multiply_factor12 1
gui_actual_frac_multiply_factor12 1
gui_actual_divide_factor12 1
gui_actual_output_clock_frequency12 0 MHz
gui_ps_units12 ps
gui_phase_shift12 0
gui_phase_shift_deg12 0.0
gui_actual_phase_shift12 0
gui_duty_cycle12 50
gui_cascade_counter13 false
gui_output_clock_frequency13 100.0
gui_divide_factor_c13 1
gui_actual_multiply_factor13 1
gui_actual_frac_multiply_factor13 1
gui_actual_divide_factor13 1
gui_actual_output_clock_frequency13 0 MHz
gui_ps_units13 ps
gui_phase_shift13 0
gui_phase_shift_deg13 0.0
gui_actual_phase_shift13 0
gui_duty_cycle13 50
gui_cascade_counter14 false
gui_output_clock_frequency14 100.0
gui_divide_factor_c14 1
gui_actual_multiply_factor14 1
gui_actual_frac_multiply_factor14 1
gui_actual_divide_factor14 1
gui_actual_output_clock_frequency14 0 MHz
gui_ps_units14 ps
gui_phase_shift14 0
gui_phase_shift_deg14 0.0
gui_actual_phase_shift14 0
gui_duty_cycle14 50
gui_cascade_counter15 false
gui_output_clock_frequency15 100.0
gui_divide_factor_c15 1
gui_actual_multiply_factor15 1
gui_actual_frac_multiply_factor15 1
gui_actual_divide_factor15 1
gui_actual_output_clock_frequency15 0 MHz
gui_ps_units15 ps
gui_phase_shift15 0
gui_phase_shift_deg15 0.0
gui_actual_phase_shift15 0
gui_duty_cycle15 50
gui_cascade_counter16 false
gui_output_clock_frequency16 100.0
gui_divide_factor_c16 1
gui_actual_multiply_factor16 1
gui_actual_frac_multiply_factor16 1
gui_actual_divide_factor16 1
gui_actual_output_clock_frequency16 0 MHz
gui_ps_units16 ps
gui_phase_shift16 0
gui_phase_shift_deg16 0.0
gui_actual_phase_shift16 0
gui_duty_cycle16 50
gui_cascade_counter17 false
gui_output_clock_frequency17 100.0
gui_divide_factor_c17 1
gui_actual_multiply_factor17 1
gui_actual_frac_multiply_factor17 1
gui_actual_divide_factor17 1
gui_actual_output_clock_frequency17 0 MHz
gui_ps_units17 ps
gui_phase_shift17 0
gui_phase_shift_deg17 0.0
gui_actual_phase_shift17 0
gui_duty_cycle17 50
output_clock_frequency0 100.000000 MHz
phase_shift0 0 ps
duty_cycle0 50
output_clock_frequency1 0 MHz
phase_shift1 0 ps
duty_cycle1 50
output_clock_frequency2 0 MHz
phase_shift2 0 ps
duty_cycle2 50
output_clock_frequency3 0 MHz
phase_shift3 0 ps
duty_cycle3 50
output_clock_frequency4 0 MHz
phase_shift4 0 ps
duty_cycle4 50
output_clock_frequency5 0 MHz
phase_shift5 0 ps
duty_cycle5 50
output_clock_frequency6 0 MHz
phase_shift6 0 ps
duty_cycle6 50
output_clock_frequency7 0 MHz
phase_shift7 0 ps
duty_cycle7 50
output_clock_frequency8 0 MHz
phase_shift8 0 ps
duty_cycle8 50
output_clock_frequency9 0 MHz
phase_shift9 0 ps
duty_cycle9 50
output_clock_frequency10 0 MHz
phase_shift10 0 ps
duty_cycle10 50
output_clock_frequency11 0 MHz
phase_shift11 0 ps
duty_cycle11 50
output_clock_frequency12 0 MHz
phase_shift12 0 ps
duty_cycle12 50
output_clock_frequency13 0 MHz
phase_shift13 0 ps
duty_cycle13 50
output_clock_frequency14 0 MHz
phase_shift14 0 ps
duty_cycle14 50
output_clock_frequency15 0 MHz
phase_shift15 0 ps
duty_cycle15 50
output_clock_frequency16 0 MHz
phase_shift16 0 ps
duty_cycle16 50
output_clock_frequency17 0 MHz
phase_shift17 0 ps
duty_cycle17 50
gui_pll_auto_reset Off
gui_pll_bandwidth_preset Auto
gui_en_reconf false
gui_en_dps_ports false
gui_en_phout_ports false
gui_phout_division 1
gui_en_lvds_ports false
pll_vcoph_div 1
pll_type General
pll_subtype General
m_cnt_hi_div 2
m_cnt_lo_div 1
n_cnt_hi_div 2
n_cnt_lo_div 2
m_cnt_bypass_en false
n_cnt_bypass_en false
m_cnt_odd_div_duty_en true
n_cnt_odd_div_duty_en false
c_cnt_hi_div0 2
c_cnt_lo_div0 1
c_cnt_prst0 1
c_cnt_ph_mux_prst0 0
c_cnt_in_src0 ph_mux_clk
c_cnt_bypass_en0 false
c_cnt_odd_div_duty_en0 true
c_cnt_hi_div1 1
c_cnt_lo_div1 1
c_cnt_prst1 1
c_cnt_ph_mux_prst1 0
c_cnt_in_src1 ph_mux_clk
c_cnt_bypass_en1 true
c_cnt_odd_div_duty_en1 false
c_cnt_hi_div2 1
c_cnt_lo_div2 1
c_cnt_prst2 1
c_cnt_ph_mux_prst2 0
c_cnt_in_src2 ph_mux_clk
c_cnt_bypass_en2 true
c_cnt_odd_div_duty_en2 false
c_cnt_hi_div3 1
c_cnt_lo_div3 1
c_cnt_prst3 1
c_cnt_ph_mux_prst3 0
c_cnt_in_src3 ph_mux_clk
c_cnt_bypass_en3 true
c_cnt_odd_div_duty_en3 false
c_cnt_hi_div4 1
c_cnt_lo_div4 1
c_cnt_prst4 1
c_cnt_ph_mux_prst4 0
c_cnt_in_src4 ph_mux_clk
c_cnt_bypass_en4 true
c_cnt_odd_div_duty_en4 false
c_cnt_hi_div5 1
c_cnt_lo_div5 1
c_cnt_prst5 1
c_cnt_ph_mux_prst5 0
c_cnt_in_src5 ph_mux_clk
c_cnt_bypass_en5 true
c_cnt_odd_div_duty_en5 false
c_cnt_hi_div6 1
c_cnt_lo_div6 1
c_cnt_prst6 1
c_cnt_ph_mux_prst6 0
c_cnt_in_src6 ph_mux_clk
c_cnt_bypass_en6 true
c_cnt_odd_div_duty_en6 false
c_cnt_hi_div7 1
c_cnt_lo_div7 1
c_cnt_prst7 1
c_cnt_ph_mux_prst7 0
c_cnt_in_src7 ph_mux_clk
c_cnt_bypass_en7 true
c_cnt_odd_div_duty_en7 false
c_cnt_hi_div8 1
c_cnt_lo_div8 1
c_cnt_prst8 1
c_cnt_ph_mux_prst8 0
c_cnt_in_src8 ph_mux_clk
c_cnt_bypass_en8 true
c_cnt_odd_div_duty_en8 false
c_cnt_hi_div9 1
c_cnt_lo_div9 1
c_cnt_prst9 1
c_cnt_ph_mux_prst9 0
c_cnt_in_src9 ph_mux_clk
c_cnt_bypass_en9 true
c_cnt_odd_div_duty_en9 false
c_cnt_hi_div10 1
c_cnt_lo_div10 1
c_cnt_prst10 1
c_cnt_ph_mux_prst10 0
c_cnt_in_src10 ph_mux_clk
c_cnt_bypass_en10 true
c_cnt_odd_div_duty_en10 false
c_cnt_hi_div11 1
c_cnt_lo_div11 1
c_cnt_prst11 1
c_cnt_ph_mux_prst11 0
c_cnt_in_src11 ph_mux_clk
c_cnt_bypass_en11 true
c_cnt_odd_div_duty_en11 false
c_cnt_hi_div12 1
c_cnt_lo_div12 1
c_cnt_prst12 1
c_cnt_ph_mux_prst12 0
c_cnt_in_src12 ph_mux_clk
c_cnt_bypass_en12 true
c_cnt_odd_div_duty_en12 false
c_cnt_hi_div13 1
c_cnt_lo_div13 1
c_cnt_prst13 1
c_cnt_ph_mux_prst13 0
c_cnt_in_src13 ph_mux_clk
c_cnt_bypass_en13 true
c_cnt_odd_div_duty_en13 false
c_cnt_hi_div14 1
c_cnt_lo_div14 1
c_cnt_prst14 1
c_cnt_ph_mux_prst14 0
c_cnt_in_src14 ph_mux_clk
c_cnt_bypass_en14 true
c_cnt_odd_div_duty_en14 false
c_cnt_hi_div15 1
c_cnt_lo_div15 1
c_cnt_prst15 1
c_cnt_ph_mux_prst15 0
c_cnt_in_src15 ph_mux_clk
c_cnt_bypass_en15 true
c_cnt_odd_div_duty_en15 false
c_cnt_hi_div16 1
c_cnt_lo_div16 1
c_cnt_prst16 1
c_cnt_ph_mux_prst16 0
c_cnt_in_src16 ph_mux_clk
c_cnt_bypass_en16 true
c_cnt_odd_div_duty_en16 false
c_cnt_hi_div17 1
c_cnt_lo_div17 1
c_cnt_prst17 1
c_cnt_ph_mux_prst17 0
c_cnt_in_src17 ph_mux_clk
c_cnt_bypass_en17 true
c_cnt_odd_div_duty_en17 false
pll_vco_div 2
pll_cp_current 20
pll_bwctrl 2000
pll_output_clk_frequency 300.0 MHz
pll_fractional_division 1
mimic_fbclk_type gclk
pll_fbclk_mux_1 glb
pll_fbclk_mux_2 fb_1
pll_m_cnt_in_src ph_mux_clk
pll_slf_rst false
gui_parameter_list M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset
gui_parameter_values 2,1,2,2,false,false,true,false,2,1,1,0,ph_mux_clk,false,true,2,20,2000,300.0 MHz,1,gclk,glb,fb_1,ph_mux_clk,false
gui_mif_generate false
gui_enable_mif_dps false
gui_dps_cntr C0
gui_dps_num 1
gui_dps_dir Positive
gui_refclk_switch false
gui_refclk1_frequency 100.0
gui_switchover_mode Automatic Switchover
gui_switchover_delay 0
gui_active_clk false
gui_clk_bad false
refclk1_frequency 100.0 MHz
pll_clk_loss_sw_en false
pll_manu_clk_sw_en false
pll_auto_clk_sw_en false
pll_clkin_1_src clk_0
pll_clk_sw_dly 0
gui_enable_cascade_out false
gui_cascade_outclk_index 0
gui_enable_cascade_in false
pll_clkin_0_src clk_0
gui_pll_cascading_mode Create an adjpllin signal to connect with an upstream PLL
AUTO_REFCLK_CLOCK_RATE 400000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

master_driver_msgdma_0

master_driver_msgdma v1.0
ext_clk_50 clk_reset   master_driver_msgdma_0
  reset
pll_0 outclk0  
  clock
mm_bridge_0 m0  
  csr
avalon_master   mSGDMA_0_mm_bridge_slv
  s0
reset_source   mSGDMA_0_clk
  clk_in_reset
interrupt_receiver   mSGDMA_0_dispatcher_write
  csr_irq
interrupt_receiver   mSGDMA_0_dispatcher_read
  csr_irq


Parameters

PRBS_PATTERN_GENERATOR_BASE 2097216
PRBS_PATTERN_CHECKER_BASE 2097152
MEMORY_BASE_ADDRESS 0
MEMORY_SPAN 536870912
BLOCK_SIZE 536870912
DISPATCHER_WRITE_CSR 2097248
DISPATCHER_WRITE_DESCRIPTOR 2097312
DISPATCHER_READ_CSR 2097280
DISPATCHER_READ_DESCRIPTOR 2097328
TIMER_BASE 2625536
FREQUENCY_COUNTER_BASE 2686976
ENABLE_PER_INFO 1
LOCAL_DATA_WORDS 32
AUTO_CLOCK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

refclk

clock_source v13.1


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0

mSGDMA_hmc v1.0


Parameters

AUTO_GENERATION_ID 1397699910
AUTO_UNIQUE_ID q_sys_hmc_mSGDMA_0
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_CLK_CLOCK_RATE 100000000
AUTO_CLK_CLOCK_DOMAIN 5
AUTO_CLK_RESET_DOMAIN 5
AUTO_CLK_0_CLOCK_RATE 50000000
AUTO_CLK_0_CLOCK_DOMAIN 1
AUTO_CLK_0_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_prbs_pattern_generator

prbs_pattern_generator v1.1
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_prbs_pattern_generator
  csr
mSGDMA_0_clk clk_reset  
  reset
clk  
  clock
st_pattern_output   mSGDMA_0_timing_adapter
  in


Parameters

DATA_WIDTH 256
PRBS_WIDTH 32
AUTO_CLOCK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_prbs_pattern_checker

prbs_pattern_checker v1.1
mSGDMA_0_dma_read_master Data_Source   mSGDMA_0_prbs_pattern_checker
  st_pattern_input
mSGDMA_0_mm_bridge_slv m0  
  csr
mSGDMA_0_clk clk_reset  
  reset
clk  
  clock


Parameters

DATA_WIDTH 256
PRBS_WIDTH 32
AUTO_CLOCK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_dma_write_master

dma_write_master v1.0
mSGDMA_0_timing_adapter out   mSGDMA_0_dma_write_master
  Data_Sink
mSGDMA_0_dispatcher_write Write_Command_Source  
  Command_Sink
mSGDMA_0_clk clk_reset  
  Clock_reset
clk  
  Clock
Response_Source   mSGDMA_0_dispatcher_write
  Write_Response_Sink
Data_Write_Master   fpga_sdram
  avl_0


Parameters

DATA_WIDTH 256
LENGTH_WIDTH 31
FIFO_DEPTH 128
STRIDE_ENABLE 0
GUI_STRIDE_WIDTH 1
BURST_ENABLE 1
GUI_MAX_BURST_COUNT 32
GUI_PROGRAMMABLE_BURST_ENABLE 0
GUI_BURST_WRAPPING_SUPPORT 0
TRANSFER_TYPE Full Word Accesses Only
PACKET_ENABLE 0
ERROR_ENABLE 0
ERROR_WIDTH 8
BYTE_ENABLE_WIDTH 32
BYTE_ENABLE_WIDTH_LOG2 5
ADDRESS_WIDTH 32
FIFO_DEPTH_LOG2 7
SYMBOL_WIDTH 8
NUMBER_OF_SYMBOLS 32
NUMBER_OF_SYMBOLS_LOG2 5
MAX_BURST_COUNT_WIDTH 6
UNALIGNED_ACCESSES_ENABLE 0
ONLY_FULL_ACCESS_ENABLE 1
BURST_WRAPPING_SUPPORT 0
PROGRAMMABLE_BURST_ENABLE 0
MAX_BURST_COUNT 32
FIFO_SPEED_OPTIMIZATION 1
STRIDE_WIDTH 1
ACTUAL_BYTES_TRANSFERRED_WIDTH 32
AUTO_CLOCK_CLOCK_RATE 100000000
AUTO_DEVICE_FAMILY CYCLONEV
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_dispatcher_write

modular_sgdma_dispatcher v1.0
mSGDMA_0_dma_write_master Response_Source   mSGDMA_0_dispatcher_write
  Write_Response_Sink
mSGDMA_0_mm_bridge_slv m0  
  CSR
m0  
  Descriptor_Slave
mSGDMA_0_clk clk_reset  
  clock_reset
clk  
  clock
master_driver_msgdma_0 interrupt_receiver  
  csr_irq
Write_Command_Source   mSGDMA_0_dma_write_master
  Command_Sink


Parameters

MODE 2
GUI_RESPONSE_PORT 2
RESPONSE_PORT 2
DESCRIPTOR_FIFO_DEPTH 8
ENHANCED_FEATURES 0
DESCRIPTOR_WIDTH 128
DESCRIPTOR_BYTEENABLE_WIDTH 16
CSR_ADDRESS_WIDTH 3
AUTO_CLOCK_CLOCK_RATE 100000000
AUTO_DEVICE_FAMILY CYCLONEV
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

DESCRIPTOR_FIFO_DEPTH 8
RESPONSE_FIFO_DEPTH 16

mSGDMA_0_dma_read_master

dma_read_master v1.0
mSGDMA_0_dispatcher_read Read_Command_Source   mSGDMA_0_dma_read_master
  Command_Sink
mSGDMA_0_clk clk_reset  
  Clock_reset
clk  
  Clock
Data_Source   mSGDMA_0_prbs_pattern_checker
  st_pattern_input
Response_Source   mSGDMA_0_dispatcher_read
  Read_Response_Sink
Data_Read_Master   fpga_sdram
  avl_0


Parameters

DATA_WIDTH 256
LENGTH_WIDTH 31
FIFO_DEPTH 256
STRIDE_ENABLE 0
GUI_STRIDE_WIDTH 1
BURST_ENABLE 1
GUI_MAX_BURST_COUNT 32
GUI_PROGRAMMABLE_BURST_ENABLE 0
GUI_BURST_WRAPPING_SUPPORT 0
TRANSFER_TYPE Full Word Accesses Only
PACKET_ENABLE 0
ERROR_ENABLE 0
ERROR_WIDTH 8
CHANNEL_ENABLE 0
CHANNEL_WIDTH 8
BYTE_ENABLE_WIDTH 32
BYTE_ENABLE_WIDTH_LOG2 5
ADDRESS_WIDTH 32
FIFO_DEPTH_LOG2 8
SYMBOL_WIDTH 8
NUMBER_OF_SYMBOLS 32
NUMBER_OF_SYMBOLS_LOG2 5
MAX_BURST_COUNT_WIDTH 6
UNALIGNED_ACCESSES_ENABLE 0
ONLY_FULL_ACCESS_ENABLE 1
BURST_WRAPPING_SUPPORT 0
PROGRAMMABLE_BURST_ENABLE 0
MAX_BURST_COUNT 32
FIFO_SPEED_OPTIMIZATION 1
STRIDE_WIDTH 1
AUTO_CLOCK_CLOCK_RATE 100000000
AUTO_DEVICE_FAMILY CYCLONEV
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_dispatcher_read

modular_sgdma_dispatcher v1.0
mSGDMA_0_dma_read_master Response_Source   mSGDMA_0_dispatcher_read
  Read_Response_Sink
mSGDMA_0_mm_bridge_slv m0  
  CSR
m0  
  Descriptor_Slave
mSGDMA_0_clk clk_reset  
  clock_reset
clk  
  clock
master_driver_msgdma_0 interrupt_receiver  
  csr_irq
Read_Command_Source   mSGDMA_0_dma_read_master
  Command_Sink


Parameters

MODE 1
GUI_RESPONSE_PORT 0
RESPONSE_PORT 2
DESCRIPTOR_FIFO_DEPTH 8
ENHANCED_FEATURES 0
DESCRIPTOR_WIDTH 128
DESCRIPTOR_BYTEENABLE_WIDTH 16
CSR_ADDRESS_WIDTH 3
AUTO_CLOCK_CLOCK_RATE 100000000
AUTO_DEVICE_FAMILY CYCLONEV
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

DESCRIPTOR_FIFO_DEPTH 8
RESPONSE_FIFO_DEPTH 16

mSGDMA_0_timing_adapter

timing_adapter v13.1
mSGDMA_0_prbs_pattern_generator st_pattern_output   mSGDMA_0_timing_adapter
  in
mSGDMA_0_clk clk_reset  
  reset
clk  
  clk
out   mSGDMA_0_dma_write_master
  Data_Sink


Parameters

generationLanguage VERILOG
inBitsPerSymbol 8
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 1
inSymbolsPerBeat 32
inUseEmpty false
inUseEmptyPort AUTO
inUsePackets false
inUseReady true
inUseValid true
moduleName
outReadyLatency 0
outUseReady true
outUseValid true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_mm_bridge_slv

altera_avalon_mm_bridge v13.1
mSGDMA_0_clk clk   mSGDMA_0_mm_bridge_slv
  clk
clk_reset  
  reset
master_driver_msgdma_0 avalon_master  
  s0
mm_bridge_0 m0  
  s0
m0   mSGDMA_0_prbs_pattern_generator
  csr
m0   mSGDMA_0_dispatcher_write
  CSR
m0  
  Descriptor_Slave
m0   mSGDMA_0_prbs_pattern_checker
  csr
m0   mSGDMA_0_dispatcher_read
  CSR
m0  
  Descriptor_Slave
m0   mSGDMA_0_status_mon_0
  slv
m0   mSGDMA_0_timer_0
  s1
m0   mSGDMA_0_freq_counter_0
  csr


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 20
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 4
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
AUTO_CLK_CLOCK_RATE 100000000
AUTO_DEVICE_FAMILY CYCLONEV
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_clk

clock_source v13.1
master_driver_msgdma_0 reset_source   mSGDMA_0_clk
  clk_in_reset
pll_0 outclk0  
  clk_in
clk_reset   mSGDMA_0_dispatcher_read
  clock_reset
clk  
  clock
clk_reset   mSGDMA_0_dma_read_master
  Clock_reset
clk  
  Clock
clk_reset   mSGDMA_0_prbs_pattern_checker
  reset
clk  
  clock
clk_reset   mSGDMA_0_dispatcher_write
  clock_reset
clk  
  clock
clk_reset   mSGDMA_0_dma_write_master
  Clock_reset
clk  
  Clock
clk_reset   mSGDMA_0_timing_adapter
  reset
clk  
  clk
clk_reset   mSGDMA_0_prbs_pattern_generator
  reset
clk  
  clock
clk   mSGDMA_0_mm_bridge_slv
  clk
clk_reset  
  reset
clk   mSGDMA_0_status_mon_0
  clock
clk_reset  
  reset_n
clk_reset   mSGDMA_0_timer_0
  reset
clk   mSGDMA_0_freq_counter_0
  sample_clock


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 100000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_status_mon_0

status_mon v1.0
mSGDMA_0_clk clk   mSGDMA_0_status_mon_0
  clock
clk_reset  
  reset_n
mSGDMA_0_mm_bridge_slv m0  
  slv
status   fpga_sdram
  status


Parameters

AUTO_CLOCK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_timer_0

altera_avalon_timer v13.1
mSGDMA_0_clk_0 clk   mSGDMA_0_timer_0
  clk
mSGDMA_0_clk clk_reset  
  reset
mSGDMA_0_mm_bridge_slv m0  
  s1


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 50000000
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0
loadValue 49999
mult 0
ticksPerSec 1000
slave_address_width 3
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000.0
TIMEOUT_PULSE_OUTPUT 0

mSGDMA_0_clk_0

clock_source v13.1
ext_clk_50 clk   mSGDMA_0_clk_0
  clk_in
clk_reset  
  clk_in_reset
clk   mSGDMA_0_timer_0
  clk
clk   mSGDMA_0_freq_counter_0
  clock
clk_reset  
  reset


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 50000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_freq_counter_0

freq_counter v1.0
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_freq_counter_0
  csr
mSGDMA_0_clk_0 clk  
  clock
clk_reset  
  reset
mSGDMA_0_clk clk  
  sample_clock


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 20000
DIV 1
AUTO_CLOCK_CLOCK_RATE 50000000
AUTO_SAMPLE_CLOCK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mm_bridge_0

altera_avalon_mm_bridge v13.1
ext_clk_50 clk   mm_bridge_0
  clk
clk_reset  
  reset
m0   master_driver_msgdma_0
  csr
m0   mSGDMA_0_mm_bridge_slv
  s0


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 22
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 4
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
AUTO_CLK_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY CYCLONEV
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

mm_traffic_generator_0

altera_avalon_mm_traffic_generator v13.1
pll_0 outclk0   mm_traffic_generator_0
  avl_clock
reset clk_reset  
  avl_reset
avl   fpga_sdram
  avl_0


Parameters

SYS_INFO_DEVICE_FAMILY CYCLONEV
PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV
DEVICE_FAMILY Cyclone V
PRE_V_SERIES_FAMILY false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM
DEVICE_FAMILY_PARAM
SPEED_GRADE 2
IS_ES_DEVICE false
DISABLE_CHILD_MESSAGING false
HARD_PHY false
HARD_EMIF false
HHP_HPS false
HHP_HPS_VERIFICATION false
HHP_HPS_SIMULATION false
HPS_PROTOCOL DEFAULT
CUT_NEW_FAMILY_TIMING true
TG_AVL_DATA_WIDTH 256
TG_AVL_ADDR_WIDTH 29
TG_AVL_WORD_ADDR_WIDTH 24
TG_AVL_SIZE_WIDTH 7
TG_AVL_SYMBOL_WIDTH 8
TG_AVL_BE_WIDTH 32
TG_AVL_NUM_SYMBOLS 32
ENABLE_EMIT_BFM_MASTER false
DRIVER_SIGNATURE 1431634051
TG_AVL_DATA_WIDTH_IN 256
TG_POWER_OF_TWO_BUS false
TG_SOPC_COMPAT_RESET false
TG_AVL_ADDR_WIDTH_IN 24
TG_GEN_BYTE_ADDR true
TG_AVL_MAX_SIZE 64
TG_NUM_DRIVER_LOOP 10000
TG_TWO_AVL_INTERFACES false
TG_BYTE_ENABLE true
TG_PNF_ENABLE false
ENABLE_CTRL_AVALON_INTERFACE true
TG_BURST_BEGIN false
TG_ENABLE_UNIX_ID false
TG_USE_UNIX_ID 0
TG_USE_LITE_DRIVER false
TG_ENABLE_DRIVER_CSR_MASTER false
TG_RANDOM_BYTE_ENABLE false
TG_ENABLE_READ_COMPARE true
TG_POWER_OF_TWO_BURSTS_ONLY false
TG_BURST_ON_BURST_BOUNDARY false
TG_DO_NOT_CROSS_4KB_BOUNDARY false
TG_TIMEOUT_COUNTER_WIDTH 32
TG_MAX_READ_LATENCY 20
TG_SINGLE_RW_SEQ_ADDR_COUNT 32
TG_SINGLE_RW_RAND_ADDR_COUNT 32
TG_SINGLE_RW_RAND_SEQ_ADDR_COUNT 32
TG_BLOCK_RW_SEQ_ADDR_COUNT 8
TG_BLOCK_RW_RAND_ADDR_COUNT 8
TG_BLOCK_RW_RAND_SEQ_ADDR_COUNT 8
TG_BLOCK_RW_BLOCK_SIZE 8
TG_TEMPLATE_STAGE_COUNT 4
TG_SEQ_ADDR_GEN_MIN_BURSTCOUNT 1
TG_SEQ_ADDR_GEN_MAX_BURSTCOUNT 64
TG_RAND_ADDR_GEN_MIN_BURSTCOUNT 1
TG_RAND_ADDR_GEN_MAX_BURSTCOUNT 64
TG_RAND_SEQ_ADDR_GEN_MIN_BURSTCOUNT 1
TG_RAND_SEQ_ADDR_GEN_MAX_BURSTCOUNT 64
TG_RAND_SEQ_ADDR_GEN_RAND_ADDR_PERCENT 50
AUTO_DEVICE 5CGTFD9E5F35C7
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

reset

clock_source v13.1
ext_clk_50 clk   reset
  clk_in
clk_reset   mm_traffic_generator_0
  avl_reset


Parameters

clockFrequency 50000000
clockFrequencyKnown false
inputClockFrequency 50000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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