q_sys_cmos

2023.09.14.14:40:15 Datasheet
Overview
  clkin  q_sys_cmos

All Components
   data_pattern_checker_0 altera_avalon_data_pattern_checker 22.1
   data_pattern_generator_0 altera_avalon_data_pattern_generator 22.1
   freq_counter_0 freq_counter 1.0
   master_driver_com_0 master_driver_com 1.0
   mm_bridge_0 altera_avalon_mm_bridge 22.1
   timer_0 altera_avalon_timer 22.1
Memory Map
master_driver_com_0
 avalon_master
  data_pattern_checker_0
csr_slave  0x00000020
  data_pattern_generator_0
csr_slave  0x00000000
  freq_counter_0
csr  0x00000200
  master_driver_com_0
csr 
  timer_0
s1  0x00000100

clkin

clock_source v22.1


Parameters

clockFrequency 100000000
clockFrequencyKnown false
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

data_pattern_checker_0

altera_avalon_data_pattern_checker v22.1
master_driver_com_0 avalon_master   data_pattern_checker_0
  csr_slave
mm_bridge_0 m0  
  csr_slave
clkin clk  
  csr_clk
clk_reset  
  reset
rx_clk out_clk  
  pattern_in_clk


Parameters

ST_DATA_W 32
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 0
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

data_pattern_generator_0

altera_avalon_data_pattern_generator v22.1
master_driver_com_0 avalon_master   data_pattern_generator_0
  csr_slave
mm_bridge_0 m0  
  csr_slave
clkin clk  
  csr_clk
clk_reset  
  reset
tx_clk out_clk  
  pattern_out_clk


Parameters

ST_DATA_W 32
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 0
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

freq_counter_0

freq_counter v1.0
master_driver_com_0 avalon_master   freq_counter_0
  csr
mm_bridge_0 m0  
  csr
clkin clk  
  clock
clk_reset  
  reset
rx_clk out_clk  
  sample_clock


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 20000
DIV 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

master_driver_com_0

master_driver_com v1.0
mm_bridge_0 m0   master_driver_com_0
  csr
clkin clk  
  clock
clk_reset  
  reset
avalon_master   freq_counter_0
  csr
avalon_master   data_pattern_checker_0
  csr_slave
avalon_master   data_pattern_generator_0
  csr_slave
avalon_master   timer_0
  s1


Parameters

CHECKER_BASE 32
GENERATOR_BASE 0
TIMER_BASE 256
FREQ_BASE 512
DESERIALIZATION_FACTOR 8
NUM_OF_CH 16
ENABLE_PER_INFO 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mm_bridge_0

altera_avalon_mm_bridge v22.1
clkin clk   mm_bridge_0
  clk
clk_reset  
  reset
m0   master_driver_com_0
  csr
m0   freq_counter_0
  csr
m0   data_pattern_checker_0
  csr_slave
m0   data_pattern_generator_0
  csr_slave
m0   timer_0
  s1


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 10
SYSINFO_ADDR_WIDTH 10
USE_AUTO_ADDRESS_WIDTH 0
AUTO_ADDRESS_WIDTH 10
HDL_ADDR_WIDTH 10
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 4
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
USE_RESPONSE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

rx_clk

altera_clock_bridge v22.1
clkin clk   rx_clk
  in_clk
out_clk   data_pattern_checker_0
  pattern_in_clk
out_clk   freq_counter_0
  sample_clock


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

timer_0

altera_avalon_timer v22.1
master_driver_com_0 avalon_master   timer_0
  s1
mm_bridge_0 m0  
  s1
clkin clk  
  clk
clk_reset  
  reset


Parameters

alwaysRun false
counterSize 64
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 0
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0.001
loadValue 0
mult 0.0
ticksPerSec 0.0
slave_address_width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 64
FIXED_PERIOD 0
FREQ 0
LOAD_VALUE 0
MULT 0.0
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 0.0
TIMEOUT_PULSE_OUTPUT 0
TIMER_DEVICE_TYPE 1

tx_clk

altera_clock_bridge v22.1
clkin clk   tx_clk
  in_clk
out_clk   data_pattern_generator_0
  pattern_out_clk


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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