mSGDMA_smc

2014.04.17.09:56:22 Datasheet
Overview
  clk  mSGDMA_smc
  clk_0 

All Components
   prbs_pattern_generator prbs_pattern_generator 1.1
   prbs_pattern_checker prbs_pattern_checker 1.1
   dispatcher_write modular_sgdma_dispatcher 1.0
   dispatcher_read modular_sgdma_dispatcher 1.0
   mm_bridge_slv altera_avalon_mm_bridge 13.1
   status_mon_0 status_mon 1.0
   timer_0 altera_avalon_timer 13.1
   freq_counter_0 freq_counter 1.0
Memory Map
dma_write_master dma_read_master
 Data_Write_Master  Data_Read_Master
  prbs_pattern_generator
csr 
  prbs_pattern_checker
csr 
  dispatcher_write
CSR 
Descriptor_Slave 
  dispatcher_read
CSR 
Descriptor_Slave 
  status_mon_0
slv 
  timer_0
s1 
  freq_counter_0
csr 

prbs_pattern_generator

prbs_pattern_generator v1.1
mm_bridge_slv m0   prbs_pattern_generator
  csr
clk clk_reset  
  reset
clk  
  clock
st_pattern_output   timing_adapter
  in


Parameters

DATA_WIDTH 256
PRBS_WIDTH 32
AUTO_CLOCK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

prbs_pattern_checker

prbs_pattern_checker v1.1
dma_read_master Data_Source   prbs_pattern_checker
  st_pattern_input
mm_bridge_slv m0  
  csr
clk clk_reset  
  reset
clk  
  clock


Parameters

DATA_WIDTH 256
PRBS_WIDTH 32
AUTO_CLOCK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

dma_write_master

dma_write_master v1.0
timing_adapter out   dma_write_master
  Data_Sink
dispatcher_write Write_Command_Source  
  Command_Sink
clk clk_reset  
  Clock_reset
clk  
  Clock
Response_Source   dispatcher_write
  Write_Response_Sink


Parameters

DATA_WIDTH 256
LENGTH_WIDTH 31
FIFO_DEPTH 256
STRIDE_ENABLE 0
GUI_STRIDE_WIDTH 1
BURST_ENABLE 1
GUI_MAX_BURST_COUNT 32
GUI_PROGRAMMABLE_BURST_ENABLE 0
GUI_BURST_WRAPPING_SUPPORT 0
TRANSFER_TYPE Full Word Accesses Only
PACKET_ENABLE 0
ERROR_ENABLE 0
ERROR_WIDTH 8
BYTE_ENABLE_WIDTH 32
BYTE_ENABLE_WIDTH_LOG2 5
ADDRESS_WIDTH 32
FIFO_DEPTH_LOG2 8
SYMBOL_WIDTH 8
NUMBER_OF_SYMBOLS 32
NUMBER_OF_SYMBOLS_LOG2 5
MAX_BURST_COUNT_WIDTH 6
UNALIGNED_ACCESSES_ENABLE 0
ONLY_FULL_ACCESS_ENABLE 1
BURST_WRAPPING_SUPPORT 0
PROGRAMMABLE_BURST_ENABLE 0
MAX_BURST_COUNT 32
FIFO_SPEED_OPTIMIZATION 1
STRIDE_WIDTH 1
ACTUAL_BYTES_TRANSFERRED_WIDTH 32
AUTO_CLOCK_CLOCK_RATE 100000000
AUTO_DEVICE_FAMILY CYCLONEV
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

dispatcher_write

modular_sgdma_dispatcher v1.0
dma_write_master Response_Source   dispatcher_write
  Write_Response_Sink
mm_bridge_slv m0  
  CSR
m0  
  Descriptor_Slave
clk clk_reset  
  clock_reset
clk  
  clock
Write_Command_Source   dma_write_master
  Command_Sink


Parameters

MODE 2
GUI_RESPONSE_PORT 2
RESPONSE_PORT 2
DESCRIPTOR_FIFO_DEPTH 8
ENHANCED_FEATURES 0
DESCRIPTOR_WIDTH 128
DESCRIPTOR_BYTEENABLE_WIDTH 16
CSR_ADDRESS_WIDTH 3
AUTO_CLOCK_CLOCK_RATE 100000000
AUTO_DEVICE_FAMILY CYCLONEV
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

DESCRIPTOR_FIFO_DEPTH 8
RESPONSE_FIFO_DEPTH 16

dma_read_master

dma_read_master v1.0
dispatcher_read Read_Command_Source   dma_read_master
  Command_Sink
clk clk_reset  
  Clock_reset
clk  
  Clock
Data_Source   prbs_pattern_checker
  st_pattern_input
Response_Source   dispatcher_read
  Read_Response_Sink


Parameters

DATA_WIDTH 256
LENGTH_WIDTH 31
FIFO_DEPTH 256
STRIDE_ENABLE 0
GUI_STRIDE_WIDTH 1
BURST_ENABLE 1
GUI_MAX_BURST_COUNT 32
GUI_PROGRAMMABLE_BURST_ENABLE 0
GUI_BURST_WRAPPING_SUPPORT 0
TRANSFER_TYPE Full Word Accesses Only
PACKET_ENABLE 0
ERROR_ENABLE 0
ERROR_WIDTH 8
CHANNEL_ENABLE 0
CHANNEL_WIDTH 8
BYTE_ENABLE_WIDTH 32
BYTE_ENABLE_WIDTH_LOG2 5
ADDRESS_WIDTH 32
FIFO_DEPTH_LOG2 8
SYMBOL_WIDTH 8
NUMBER_OF_SYMBOLS 32
NUMBER_OF_SYMBOLS_LOG2 5
MAX_BURST_COUNT_WIDTH 6
UNALIGNED_ACCESSES_ENABLE 0
ONLY_FULL_ACCESS_ENABLE 1
BURST_WRAPPING_SUPPORT 0
PROGRAMMABLE_BURST_ENABLE 0
MAX_BURST_COUNT 32
FIFO_SPEED_OPTIMIZATION 1
STRIDE_WIDTH 1
AUTO_CLOCK_CLOCK_RATE 100000000
AUTO_DEVICE_FAMILY CYCLONEV
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

dispatcher_read

modular_sgdma_dispatcher v1.0
dma_read_master Response_Source   dispatcher_read
  Read_Response_Sink
mm_bridge_slv m0  
  CSR
m0  
  Descriptor_Slave
clk clk_reset  
  clock_reset
clk  
  clock
Read_Command_Source   dma_read_master
  Command_Sink


Parameters

MODE 1
GUI_RESPONSE_PORT 0
RESPONSE_PORT 2
DESCRIPTOR_FIFO_DEPTH 8
ENHANCED_FEATURES 0
DESCRIPTOR_WIDTH 128
DESCRIPTOR_BYTEENABLE_WIDTH 16
CSR_ADDRESS_WIDTH 3
AUTO_CLOCK_CLOCK_RATE 100000000
AUTO_DEVICE_FAMILY CYCLONEV
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

DESCRIPTOR_FIFO_DEPTH 8
RESPONSE_FIFO_DEPTH 16

timing_adapter

timing_adapter v13.1
prbs_pattern_generator st_pattern_output   timing_adapter
  in
clk clk_reset  
  reset
clk  
  clk
out   dma_write_master
  Data_Sink


Parameters

generationLanguage VERILOG
inBitsPerSymbol 8
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 1
inSymbolsPerBeat 32
inUseEmpty false
inUseEmptyPort AUTO
inUsePackets false
inUseReady true
inUseValid true
moduleName
outReadyLatency 0
outUseReady true
outUseValid true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mm_bridge_slv

altera_avalon_mm_bridge v13.1
clk clk   mm_bridge_slv
  clk
clk_reset  
  reset
m0   prbs_pattern_generator
  csr
m0   dispatcher_write
  CSR
m0  
  Descriptor_Slave
m0   prbs_pattern_checker
  csr
m0   dispatcher_read
  CSR
m0  
  Descriptor_Slave
m0   status_mon_0
  slv
m0   timer_0
  s1
m0   freq_counter_0
  csr


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 20
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 4
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
AUTO_CLK_CLOCK_RATE 100000000
AUTO_DEVICE_FAMILY CYCLONEV
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

clk

clock_source v13.1


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

status_mon_0

status_mon v1.0
clk clk   status_mon_0
  clock
clk_reset  
  reset_n
mm_bridge_slv m0  
  slv


Parameters

AUTO_CLOCK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

timer_0

altera_avalon_timer v13.1
clk_0 clk   timer_0
  clk
clk clk_reset  
  reset
mm_bridge_slv m0  
  s1


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 50000000
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0
loadValue 49999
mult 0
ticksPerSec 1000
slave_address_width 3
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000.0
TIMEOUT_PULSE_OUTPUT 0

clk_0

clock_source v13.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

freq_counter_0

freq_counter v1.0
clk_0 clk_reset   freq_counter_0
  reset
clk  
  clock
mm_bridge_slv m0  
  csr
clk clk  
  sample_clock


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 20000
DIV 0
AUTO_CLOCK_CLOCK_RATE 50000000
AUTO_SAMPLE_CLOCK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
generation took 0.00 seconds rendering took 0.02 seconds