2023.09.14.15:02:11 |
Datasheet |
Overview
clk_100 |
q_sys |
|
clk_50 |
|
cmos_0_clkin |
|
lvds_0_clk_50 |
|
lvds_0_clk_rx |
|
lvds_0_clk_tx |
|
xcvr_0_clk_100 |
|
xcvr_0_clk_50 |
|
xcvr_0_tester_0_clk_50 |
|
xcvr_0_tester_1_clk_50 |
|
xcvr_0_tester_2_clk_50 |
|
xcvr_0_tester_3_clk_50 |
|
Memory Map
clk_100
clock_source v22.1
Parameters
clockFrequency |
100000000 |
clockFrequencyKnown |
true |
inputClockFrequency |
0 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
clk_50
clock_source v22.1
Parameters
clockFrequency |
50000000 |
clockFrequencyKnown |
true |
inputClockFrequency |
0 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
cmos_0
q_sys_cmos v1.0
Parameters
AUTO_GENERATION_ID |
1694674931 |
AUTO_UNIQUE_ID |
q_sys_cmos_0 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CLKIN_CLOCK_RATE |
50000000 |
AUTO_CLKIN_CLOCK_DOMAIN |
3 |
AUTO_CLKIN_RESET_DOMAIN |
3 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
cmos_0_clkin
clock_source v22.1
Parameters
clockFrequency |
100000000 |
clockFrequencyKnown |
false |
inputClockFrequency |
50000000 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
cmos_0_data_pattern_checker_0
altera_avalon_data_pattern_checker v22.1
Parameters
ST_DATA_W |
32 |
NUM_CYCLES_FOR_LOCK |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
cmos_0_data_pattern_generator_0
altera_avalon_data_pattern_generator v22.1
Parameters
ST_DATA_W |
32 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
cmos_0_freq_counter_0
freq_counter v1.0
Parameters
SYSTEM_CLK_FREQ_PICO_SEC |
20000 |
DIV |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
cmos_0_master_driver_com_0
master_driver_com v1.0
Parameters
CHECKER_BASE |
32 |
GENERATOR_BASE |
0 |
TIMER_BASE |
256 |
FREQ_BASE |
512 |
DESERIALIZATION_FACTOR |
8 |
NUM_OF_CH |
16 |
ENABLE_PER_INFO |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
cmos_0_mm_bridge_0
altera_avalon_mm_bridge v22.1
Parameters
DATA_WIDTH |
32 |
SYMBOL_WIDTH |
8 |
ADDRESS_WIDTH |
10 |
SYSINFO_ADDR_WIDTH |
10 |
USE_AUTO_ADDRESS_WIDTH |
0 |
AUTO_ADDRESS_WIDTH |
10 |
HDL_ADDR_WIDTH |
10 |
ADDRESS_UNITS |
SYMBOLS |
BURSTCOUNT_WIDTH |
1 |
MAX_BURST_SIZE |
1 |
MAX_PENDING_RESPONSES |
4 |
LINEWRAPBURSTS |
0 |
PIPELINE_COMMAND |
1 |
PIPELINE_RESPONSE |
1 |
USE_RESPONSE |
0 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
cmos_0_rx_clk
altera_clock_bridge v22.1
Parameters
DERIVED_CLOCK_RATE |
50000000 |
EXPLICIT_CLOCK_RATE |
0 |
NUM_CLOCK_OUTPUTS |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
cmos_0_timer_0
altera_avalon_timer v22.1
Parameters
alwaysRun |
false |
counterSize |
64 |
fixedPeriod |
false |
period |
1 |
periodUnits |
MSEC |
resetOutput |
false |
snapshot |
true |
timeoutPulseOutput |
false |
systemFrequency |
50000000 |
watchdogPulse |
2 |
timerPreset |
FULL_FEATURED |
periodUnitsString |
ms |
valueInSecond |
0.001 |
loadValue |
49999 |
mult |
0.001 |
ticksPerSec |
1000.0 |
slave_address_width |
4 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments
ALWAYS_RUN |
0 |
COUNTER_SIZE |
64 |
FIXED_PERIOD |
0 |
FREQ |
50000000 |
LOAD_VALUE |
49999 |
MULT |
0.001 |
PERIOD |
1 |
PERIOD_UNITS |
ms |
RESET_OUTPUT |
0 |
SNAPSHOT |
1 |
TICKS_PER_SEC |
1000 |
TIMEOUT_PULSE_OUTPUT |
0 |
TIMER_DEVICE_TYPE |
1 |
|
cmos_0_tx_clk
altera_clock_bridge v22.1
Parameters
DERIVED_CLOCK_RATE |
50000000 |
EXPLICIT_CLOCK_RATE |
0 |
NUM_CLOCK_OUTPUTS |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0
q_sys_lvds v1.0
Parameters
AUTO_GENERATION_ID |
1694674931 |
AUTO_UNIQUE_ID |
q_sys_lvds_0 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CLK50_CLOCK_RATE |
50000000 |
AUTO_CLK50_CLOCK_DOMAIN |
3 |
AUTO_CLK50_RESET_DOMAIN |
3 |
AUTO_RX_CLOCK_RATE |
0 |
AUTO_RX_CLOCK_DOMAIN |
5 |
AUTO_RX_RESET_DOMAIN |
5 |
AUTO_TX_CLOCK_RATE |
0 |
AUTO_TX_CLOCK_DOMAIN |
6 |
AUTO_TX_RESET_DOMAIN |
6 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_clk_50
clock_source v22.1
Parameters
clockFrequency |
100000000 |
clockFrequencyKnown |
true |
inputClockFrequency |
50000000 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_clk_rx
clock_source v22.1
Parameters
clockFrequency |
50000000 |
clockFrequencyKnown |
false |
inputClockFrequency |
0 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_clk_tx
clock_source v22.1
Parameters
clockFrequency |
50000000 |
clockFrequencyKnown |
false |
inputClockFrequency |
0 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_data_pattern_checker_0
altera_avalon_data_pattern_checker v22.1
Parameters
ST_DATA_W |
32 |
NUM_CYCLES_FOR_LOCK |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_data_pattern_checker_1
altera_avalon_data_pattern_checker v22.1
Parameters
ST_DATA_W |
40 |
NUM_CYCLES_FOR_LOCK |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_data_pattern_checker_2
altera_avalon_data_pattern_checker v22.1
Parameters
ST_DATA_W |
64 |
NUM_CYCLES_FOR_LOCK |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_data_pattern_generator_0
altera_avalon_data_pattern_generator v22.1
Parameters
ST_DATA_W |
32 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_data_pattern_generator_1
altera_avalon_data_pattern_generator v22.1
Parameters
ST_DATA_W |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_data_pattern_generator_2
altera_avalon_data_pattern_generator v22.1
Parameters
ST_DATA_W |
64 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_freq_counter_0
freq_counter v1.0
Parameters
SYSTEM_CLK_FREQ_PICO_SEC |
20000 |
DIV |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_freq_counter_1
freq_counter v1.0
Parameters
SYSTEM_CLK_FREQ_PICO_SEC |
20000 |
DIV |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_freq_counter_2
freq_counter v1.0
Parameters
SYSTEM_CLK_FREQ_PICO_SEC |
20000 |
DIV |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_master_driver_com_0
master_driver_com v1.0
Parameters
CHECKER_BASE |
4128 |
GENERATOR_BASE |
4096 |
TIMER_BASE |
4352 |
FREQ_BASE |
4608 |
DESERIALIZATION_FACTOR |
8 |
NUM_OF_CH |
4 |
ENABLE_PER_INFO |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_master_driver_com_1
master_driver_com v1.0
Parameters
CHECKER_BASE |
8224 |
GENERATOR_BASE |
8192 |
TIMER_BASE |
8448 |
FREQ_BASE |
8704 |
DESERIALIZATION_FACTOR |
8 |
NUM_OF_CH |
5 |
ENABLE_PER_INFO |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_master_driver_com_2
master_driver_com v1.0
Parameters
CHECKER_BASE |
12320 |
GENERATOR_BASE |
12288 |
TIMER_BASE |
12544 |
FREQ_BASE |
12800 |
DESERIALIZATION_FACTOR |
8 |
NUM_OF_CH |
8 |
ENABLE_PER_INFO |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_mm_bridge_0
altera_avalon_mm_bridge v22.1
Parameters
DATA_WIDTH |
32 |
SYMBOL_WIDTH |
8 |
ADDRESS_WIDTH |
14 |
SYSINFO_ADDR_WIDTH |
14 |
USE_AUTO_ADDRESS_WIDTH |
0 |
AUTO_ADDRESS_WIDTH |
14 |
HDL_ADDR_WIDTH |
14 |
ADDRESS_UNITS |
SYMBOLS |
BURSTCOUNT_WIDTH |
1 |
MAX_BURST_SIZE |
1 |
MAX_PENDING_RESPONSES |
4 |
LINEWRAPBURSTS |
0 |
PIPELINE_COMMAND |
1 |
PIPELINE_RESPONSE |
1 |
USE_RESPONSE |
0 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
lvds_0_timer_0
altera_avalon_timer v22.1
Parameters
alwaysRun |
false |
counterSize |
64 |
fixedPeriod |
false |
period |
1 |
periodUnits |
MSEC |
resetOutput |
false |
snapshot |
true |
timeoutPulseOutput |
false |
systemFrequency |
50000000 |
watchdogPulse |
2 |
timerPreset |
FULL_FEATURED |
periodUnitsString |
ms |
valueInSecond |
0.001 |
loadValue |
49999 |
mult |
0.001 |
ticksPerSec |
1000.0 |
slave_address_width |
4 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments
ALWAYS_RUN |
0 |
COUNTER_SIZE |
64 |
FIXED_PERIOD |
0 |
FREQ |
50000000 |
LOAD_VALUE |
49999 |
MULT |
0.001 |
PERIOD |
1 |
PERIOD_UNITS |
ms |
RESET_OUTPUT |
0 |
SNAPSHOT |
1 |
TICKS_PER_SEC |
1000 |
TIMEOUT_PULSE_OUTPUT |
0 |
TIMER_DEVICE_TYPE |
1 |
|
lvds_0_timer_1
altera_avalon_timer v22.1
Parameters
alwaysRun |
false |
counterSize |
64 |
fixedPeriod |
false |
period |
1 |
periodUnits |
MSEC |
resetOutput |
false |
snapshot |
true |
timeoutPulseOutput |
false |
systemFrequency |
50000000 |
watchdogPulse |
2 |
timerPreset |
FULL_FEATURED |
periodUnitsString |
ms |
valueInSecond |
0.001 |
loadValue |
49999 |
mult |
0.001 |
ticksPerSec |
1000.0 |
slave_address_width |
4 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments
ALWAYS_RUN |
0 |
COUNTER_SIZE |
64 |
FIXED_PERIOD |
0 |
FREQ |
50000000 |
LOAD_VALUE |
49999 |
MULT |
0.001 |
PERIOD |
1 |
PERIOD_UNITS |
ms |
RESET_OUTPUT |
0 |
SNAPSHOT |
1 |
TICKS_PER_SEC |
1000 |
TIMEOUT_PULSE_OUTPUT |
0 |
TIMER_DEVICE_TYPE |
1 |
|
lvds_0_timer_2
altera_avalon_timer v22.1
Parameters
alwaysRun |
false |
counterSize |
64 |
fixedPeriod |
false |
period |
1 |
periodUnits |
MSEC |
resetOutput |
false |
snapshot |
true |
timeoutPulseOutput |
false |
systemFrequency |
50000000 |
watchdogPulse |
2 |
timerPreset |
FULL_FEATURED |
periodUnitsString |
ms |
valueInSecond |
0.001 |
loadValue |
49999 |
mult |
0.001 |
ticksPerSec |
1000.0 |
slave_address_width |
4 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments
ALWAYS_RUN |
0 |
COUNTER_SIZE |
64 |
FIXED_PERIOD |
0 |
FREQ |
50000000 |
LOAD_VALUE |
49999 |
MULT |
0.001 |
PERIOD |
1 |
PERIOD_UNITS |
ms |
RESET_OUTPUT |
0 |
SNAPSHOT |
1 |
TICKS_PER_SEC |
1000 |
TIMEOUT_PULSE_OUTPUT |
0 |
TIMER_DEVICE_TYPE |
1 |
|
master_0
altera_jtag_avalon_master v22.1
Parameters
USE_PLI |
0 |
PLI_PORT |
50000 |
COMPONENT_CLOCK |
0 |
FAST_VER |
0 |
FIFO_DEPTHS |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
product_info_0
product_info v1.0
master_0
|
master |
product_info_0 |
avalon_slave_0 |
|
clk_50
|
clk |
clock |
clk_reset |
reset |
Parameters
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0
q_sys_xcvr v1.0
Parameters
AUTO_GENERATION_ID |
1694674931 |
AUTO_UNIQUE_ID |
q_sys_xcvr_0 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CLK_100_CLOCK_RATE |
100000000 |
AUTO_CLK_100_CLOCK_DOMAIN |
1 |
AUTO_CLK_100_RESET_DOMAIN |
1 |
AUTO_CLK_50_CLOCK_RATE |
50000000 |
AUTO_CLK_50_CLOCK_DOMAIN |
3 |
AUTO_CLK_50_RESET_DOMAIN |
3 |
AUTO_XCVR_CUSTOM_PHY_0_PLL_REF_CLK_CLOCK_RATE |
0 |
AUTO_XCVR_CUSTOM_PHY_0_PLL_REF_CLK_CLOCK_DOMAIN |
7 |
AUTO_XCVR_CUSTOM_PHY_0_PLL_REF_CLK_RESET_DOMAIN |
7 |
AUTO_XCVR_CUSTOM_PHY_1_PLL_REF_CLK_CLOCK_RATE |
0 |
AUTO_XCVR_CUSTOM_PHY_1_PLL_REF_CLK_CLOCK_DOMAIN |
8 |
AUTO_XCVR_CUSTOM_PHY_1_PLL_REF_CLK_RESET_DOMAIN |
8 |
AUTO_XCVR_CUSTOM_PHY_2_PLL_REF_CLK_CLOCK_RATE |
0 |
AUTO_XCVR_CUSTOM_PHY_2_PLL_REF_CLK_CLOCK_DOMAIN |
9 |
AUTO_XCVR_CUSTOM_PHY_2_PLL_REF_CLK_RESET_DOMAIN |
9 |
AUTO_XCVR_CUSTOM_PHY_3_PLL_REF_CLK_CLOCK_RATE |
0 |
AUTO_XCVR_CUSTOM_PHY_3_PLL_REF_CLK_CLOCK_DOMAIN |
10 |
AUTO_XCVR_CUSTOM_PHY_3_PLL_REF_CLK_RESET_DOMAIN |
10 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_alt_xcvr_reconfig_0
alt_xcvr_reconfig v19.1
Parameters
device_family |
CYCLONEV |
number_of_reconfig_interfaces |
8 |
gui_split_sizes |
2,2,2 |
enable_offset |
1 |
enable_lc |
0 |
enable_dcd |
1 |
enable_dcd_power_up |
1 |
enable_analog |
1 |
enable_eyemon |
0 |
ber_en |
0 |
enable_ber |
0 |
enable_dfe |
0 |
enable_adce |
0 |
enable_mif |
0 |
gui_enable_pll |
0 |
enable_pll |
0 |
gui_cal_status_port |
false |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_clk_100
clock_source v22.1
Parameters
clockFrequency |
100000000 |
clockFrequencyKnown |
true |
inputClockFrequency |
100000000 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_clk_50
clock_source v22.1
Parameters
clockFrequency |
50000000 |
clockFrequencyKnown |
true |
inputClockFrequency |
50000000 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_mm_bridge_0
altera_avalon_mm_bridge v22.1
Parameters
DATA_WIDTH |
32 |
SYMBOL_WIDTH |
8 |
ADDRESS_WIDTH |
15 |
SYSINFO_ADDR_WIDTH |
15 |
USE_AUTO_ADDRESS_WIDTH |
0 |
AUTO_ADDRESS_WIDTH |
15 |
HDL_ADDR_WIDTH |
15 |
ADDRESS_UNITS |
SYMBOLS |
BURSTCOUNT_WIDTH |
1 |
MAX_BURST_SIZE |
1 |
MAX_PENDING_RESPONSES |
4 |
LINEWRAPBURSTS |
0 |
PIPELINE_COMMAND |
1 |
PIPELINE_RESPONSE |
1 |
USE_RESPONSE |
0 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_0
xcvr_tester v1.0
Parameters
AUTO_GENERATION_ID |
1694674931 |
AUTO_UNIQUE_ID |
q_sys_xcvr_0_tester_0 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CLK_50_CLOCK_RATE |
50000000 |
AUTO_CLK_50_CLOCK_DOMAIN |
5 |
AUTO_CLK_50_RESET_DOMAIN |
5 |
AUTO_RX_CLK_IN_CLK_CLOCK_RATE |
0 |
AUTO_RX_CLK_IN_CLK_CLOCK_DOMAIN |
11 |
AUTO_RX_CLK_IN_CLK_RESET_DOMAIN |
11 |
AUTO_TX_CLK_IN_CLK_CLOCK_RATE |
0 |
AUTO_TX_CLK_IN_CLK_CLOCK_DOMAIN |
12 |
AUTO_TX_CLK_IN_CLK_RESET_DOMAIN |
12 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_0_clk_50
clock_source v22.1
Parameters
clockFrequency |
100000000 |
clockFrequencyKnown |
true |
inputClockFrequency |
50000000 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_0_data_pattern_generator_0
altera_avalon_data_pattern_generator v22.1
Parameters
ST_DATA_W |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_0_data_pattern_checker_0
altera_avalon_data_pattern_checker v22.1
Parameters
ST_DATA_W |
40 |
NUM_CYCLES_FOR_LOCK |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_0_timing_adapter_tx0
timing_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
NO |
inUseEmpty |
false |
inSymbolsPerBeat |
4 |
inUseReady |
true |
outUseReady |
false |
inReadyLatency |
0 |
outReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
inUseValid |
true |
outUseValid |
false |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_0_timing_adapter_rx0
timing_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
NO |
inUseEmpty |
false |
inSymbolsPerBeat |
4 |
inUseReady |
false |
outUseReady |
true |
inReadyLatency |
0 |
outReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
inUseValid |
false |
outUseValid |
true |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_0_rx_clk
altera_clock_bridge v22.1
Parameters
DERIVED_CLOCK_RATE |
0 |
EXPLICIT_CLOCK_RATE |
0 |
NUM_CLOCK_OUTPUTS |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_0_tx_clk
altera_clock_bridge v22.1
Parameters
DERIVED_CLOCK_RATE |
0 |
EXPLICIT_CLOCK_RATE |
0 |
NUM_CLOCK_OUTPUTS |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_0_data_format_adapter_0
data_format_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
AUTO |
inUseEmpty |
false |
outUseEmptyPort |
AUTO |
outUseEmpty |
false |
inSymbolsPerBeat |
4 |
outSymbolsPerBeat |
4 |
inReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_0_data_format_adapter_1
data_format_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
AUTO |
inUseEmpty |
false |
outUseEmptyPort |
AUTO |
outUseEmpty |
false |
inSymbolsPerBeat |
4 |
outSymbolsPerBeat |
4 |
inReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_0_timer_0
altera_avalon_timer v22.1
Parameters
alwaysRun |
false |
counterSize |
64 |
fixedPeriod |
false |
period |
1 |
periodUnits |
MSEC |
resetOutput |
false |
snapshot |
true |
timeoutPulseOutput |
false |
systemFrequency |
50000000 |
watchdogPulse |
2 |
timerPreset |
FULL_FEATURED |
periodUnitsString |
ms |
valueInSecond |
0.001 |
loadValue |
49999 |
mult |
0.001 |
ticksPerSec |
1000.0 |
slave_address_width |
4 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments
ALWAYS_RUN |
0 |
COUNTER_SIZE |
64 |
FIXED_PERIOD |
0 |
FREQ |
50000000 |
LOAD_VALUE |
49999 |
MULT |
0.001 |
PERIOD |
1 |
PERIOD_UNITS |
ms |
RESET_OUTPUT |
0 |
SNAPSHOT |
1 |
TICKS_PER_SEC |
1000 |
TIMEOUT_PULSE_OUTPUT |
0 |
TIMER_DEVICE_TYPE |
1 |
|
xcvr_0_tester_0_master_driver_com_0
master_driver_com v1.0
Parameters
CHECKER_BASE |
32 |
GENERATOR_BASE |
0 |
TIMER_BASE |
256 |
FREQ_BASE |
512 |
DESERIALIZATION_FACTOR |
40 |
NUM_OF_CH |
1 |
ENABLE_PER_INFO |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_0_mm_bridge_0
altera_avalon_mm_bridge v22.1
Parameters
DATA_WIDTH |
32 |
SYMBOL_WIDTH |
8 |
ADDRESS_WIDTH |
10 |
SYSINFO_ADDR_WIDTH |
10 |
USE_AUTO_ADDRESS_WIDTH |
0 |
AUTO_ADDRESS_WIDTH |
10 |
HDL_ADDR_WIDTH |
10 |
ADDRESS_UNITS |
SYMBOLS |
BURSTCOUNT_WIDTH |
1 |
MAX_BURST_SIZE |
1 |
MAX_PENDING_RESPONSES |
4 |
LINEWRAPBURSTS |
0 |
PIPELINE_COMMAND |
1 |
PIPELINE_RESPONSE |
1 |
USE_RESPONSE |
0 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_0_freq_counter_0
freq_counter v1.0
Parameters
SYSTEM_CLK_FREQ_PICO_SEC |
20000 |
DIV |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_1
xcvr_tester v1.0
Parameters
AUTO_GENERATION_ID |
1694674931 |
AUTO_UNIQUE_ID |
q_sys_xcvr_0_tester_1 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CLK_50_CLOCK_RATE |
50000000 |
AUTO_CLK_50_CLOCK_DOMAIN |
5 |
AUTO_CLK_50_RESET_DOMAIN |
5 |
AUTO_RX_CLK_IN_CLK_CLOCK_RATE |
0 |
AUTO_RX_CLK_IN_CLK_CLOCK_DOMAIN |
13 |
AUTO_RX_CLK_IN_CLK_RESET_DOMAIN |
13 |
AUTO_TX_CLK_IN_CLK_CLOCK_RATE |
0 |
AUTO_TX_CLK_IN_CLK_CLOCK_DOMAIN |
14 |
AUTO_TX_CLK_IN_CLK_RESET_DOMAIN |
14 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_1_clk_50
clock_source v22.1
Parameters
clockFrequency |
100000000 |
clockFrequencyKnown |
true |
inputClockFrequency |
50000000 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_1_data_pattern_generator_0
altera_avalon_data_pattern_generator v22.1
Parameters
ST_DATA_W |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_1_data_pattern_checker_0
altera_avalon_data_pattern_checker v22.1
Parameters
ST_DATA_W |
40 |
NUM_CYCLES_FOR_LOCK |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_1_timing_adapter_tx0
timing_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
NO |
inUseEmpty |
false |
inSymbolsPerBeat |
4 |
inUseReady |
true |
outUseReady |
false |
inReadyLatency |
0 |
outReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
inUseValid |
true |
outUseValid |
false |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_1_timing_adapter_rx0
timing_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
NO |
inUseEmpty |
false |
inSymbolsPerBeat |
4 |
inUseReady |
false |
outUseReady |
true |
inReadyLatency |
0 |
outReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
inUseValid |
false |
outUseValid |
true |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_1_rx_clk
altera_clock_bridge v22.1
Parameters
DERIVED_CLOCK_RATE |
0 |
EXPLICIT_CLOCK_RATE |
0 |
NUM_CLOCK_OUTPUTS |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_1_tx_clk
altera_clock_bridge v22.1
Parameters
DERIVED_CLOCK_RATE |
0 |
EXPLICIT_CLOCK_RATE |
0 |
NUM_CLOCK_OUTPUTS |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_1_data_format_adapter_0
data_format_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
AUTO |
inUseEmpty |
false |
outUseEmptyPort |
AUTO |
outUseEmpty |
false |
inSymbolsPerBeat |
4 |
outSymbolsPerBeat |
4 |
inReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_1_data_format_adapter_1
data_format_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
AUTO |
inUseEmpty |
false |
outUseEmptyPort |
AUTO |
outUseEmpty |
false |
inSymbolsPerBeat |
4 |
outSymbolsPerBeat |
4 |
inReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_1_timer_0
altera_avalon_timer v22.1
Parameters
alwaysRun |
false |
counterSize |
64 |
fixedPeriod |
false |
period |
1 |
periodUnits |
MSEC |
resetOutput |
false |
snapshot |
true |
timeoutPulseOutput |
false |
systemFrequency |
50000000 |
watchdogPulse |
2 |
timerPreset |
FULL_FEATURED |
periodUnitsString |
ms |
valueInSecond |
0.001 |
loadValue |
49999 |
mult |
0.001 |
ticksPerSec |
1000.0 |
slave_address_width |
4 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments
ALWAYS_RUN |
0 |
COUNTER_SIZE |
64 |
FIXED_PERIOD |
0 |
FREQ |
50000000 |
LOAD_VALUE |
49999 |
MULT |
0.001 |
PERIOD |
1 |
PERIOD_UNITS |
ms |
RESET_OUTPUT |
0 |
SNAPSHOT |
1 |
TICKS_PER_SEC |
1000 |
TIMEOUT_PULSE_OUTPUT |
0 |
TIMER_DEVICE_TYPE |
1 |
|
xcvr_0_tester_1_master_driver_com_0
master_driver_com v1.0
Parameters
CHECKER_BASE |
32 |
GENERATOR_BASE |
0 |
TIMER_BASE |
256 |
FREQ_BASE |
512 |
DESERIALIZATION_FACTOR |
40 |
NUM_OF_CH |
1 |
ENABLE_PER_INFO |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_1_mm_bridge_0
altera_avalon_mm_bridge v22.1
Parameters
DATA_WIDTH |
32 |
SYMBOL_WIDTH |
8 |
ADDRESS_WIDTH |
10 |
SYSINFO_ADDR_WIDTH |
10 |
USE_AUTO_ADDRESS_WIDTH |
0 |
AUTO_ADDRESS_WIDTH |
10 |
HDL_ADDR_WIDTH |
10 |
ADDRESS_UNITS |
SYMBOLS |
BURSTCOUNT_WIDTH |
1 |
MAX_BURST_SIZE |
1 |
MAX_PENDING_RESPONSES |
4 |
LINEWRAPBURSTS |
0 |
PIPELINE_COMMAND |
1 |
PIPELINE_RESPONSE |
1 |
USE_RESPONSE |
0 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_1_freq_counter_0
freq_counter v1.0
Parameters
SYSTEM_CLK_FREQ_PICO_SEC |
20000 |
DIV |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_2
xcvr_tester v1.0
Parameters
AUTO_GENERATION_ID |
1694674931 |
AUTO_UNIQUE_ID |
q_sys_xcvr_0_tester_2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CLK_50_CLOCK_RATE |
50000000 |
AUTO_CLK_50_CLOCK_DOMAIN |
5 |
AUTO_CLK_50_RESET_DOMAIN |
5 |
AUTO_RX_CLK_IN_CLK_CLOCK_RATE |
0 |
AUTO_RX_CLK_IN_CLK_CLOCK_DOMAIN |
15 |
AUTO_RX_CLK_IN_CLK_RESET_DOMAIN |
15 |
AUTO_TX_CLK_IN_CLK_CLOCK_RATE |
0 |
AUTO_TX_CLK_IN_CLK_CLOCK_DOMAIN |
16 |
AUTO_TX_CLK_IN_CLK_RESET_DOMAIN |
16 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_2_clk_50
clock_source v22.1
Parameters
clockFrequency |
100000000 |
clockFrequencyKnown |
true |
inputClockFrequency |
50000000 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_2_data_pattern_generator_0
altera_avalon_data_pattern_generator v22.1
Parameters
ST_DATA_W |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_2_data_pattern_checker_0
altera_avalon_data_pattern_checker v22.1
Parameters
ST_DATA_W |
40 |
NUM_CYCLES_FOR_LOCK |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_2_timing_adapter_tx0
timing_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
NO |
inUseEmpty |
false |
inSymbolsPerBeat |
4 |
inUseReady |
true |
outUseReady |
false |
inReadyLatency |
0 |
outReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
inUseValid |
true |
outUseValid |
false |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_2_timing_adapter_rx0
timing_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
NO |
inUseEmpty |
false |
inSymbolsPerBeat |
4 |
inUseReady |
false |
outUseReady |
true |
inReadyLatency |
0 |
outReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
inUseValid |
false |
outUseValid |
true |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_2_rx_clk
altera_clock_bridge v22.1
Parameters
DERIVED_CLOCK_RATE |
0 |
EXPLICIT_CLOCK_RATE |
0 |
NUM_CLOCK_OUTPUTS |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_2_tx_clk
altera_clock_bridge v22.1
Parameters
DERIVED_CLOCK_RATE |
0 |
EXPLICIT_CLOCK_RATE |
0 |
NUM_CLOCK_OUTPUTS |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_2_data_format_adapter_0
data_format_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
AUTO |
inUseEmpty |
false |
outUseEmptyPort |
AUTO |
outUseEmpty |
false |
inSymbolsPerBeat |
4 |
outSymbolsPerBeat |
4 |
inReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_2_data_format_adapter_1
data_format_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
AUTO |
inUseEmpty |
false |
outUseEmptyPort |
AUTO |
outUseEmpty |
false |
inSymbolsPerBeat |
4 |
outSymbolsPerBeat |
4 |
inReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_2_timer_0
altera_avalon_timer v22.1
Parameters
alwaysRun |
false |
counterSize |
64 |
fixedPeriod |
false |
period |
1 |
periodUnits |
MSEC |
resetOutput |
false |
snapshot |
true |
timeoutPulseOutput |
false |
systemFrequency |
50000000 |
watchdogPulse |
2 |
timerPreset |
FULL_FEATURED |
periodUnitsString |
ms |
valueInSecond |
0.001 |
loadValue |
49999 |
mult |
0.001 |
ticksPerSec |
1000.0 |
slave_address_width |
4 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments
ALWAYS_RUN |
0 |
COUNTER_SIZE |
64 |
FIXED_PERIOD |
0 |
FREQ |
50000000 |
LOAD_VALUE |
49999 |
MULT |
0.001 |
PERIOD |
1 |
PERIOD_UNITS |
ms |
RESET_OUTPUT |
0 |
SNAPSHOT |
1 |
TICKS_PER_SEC |
1000 |
TIMEOUT_PULSE_OUTPUT |
0 |
TIMER_DEVICE_TYPE |
1 |
|
xcvr_0_tester_2_master_driver_com_0
master_driver_com v1.0
Parameters
CHECKER_BASE |
32 |
GENERATOR_BASE |
0 |
TIMER_BASE |
256 |
FREQ_BASE |
512 |
DESERIALIZATION_FACTOR |
40 |
NUM_OF_CH |
1 |
ENABLE_PER_INFO |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_2_mm_bridge_0
altera_avalon_mm_bridge v22.1
Parameters
DATA_WIDTH |
32 |
SYMBOL_WIDTH |
8 |
ADDRESS_WIDTH |
10 |
SYSINFO_ADDR_WIDTH |
10 |
USE_AUTO_ADDRESS_WIDTH |
0 |
AUTO_ADDRESS_WIDTH |
10 |
HDL_ADDR_WIDTH |
10 |
ADDRESS_UNITS |
SYMBOLS |
BURSTCOUNT_WIDTH |
1 |
MAX_BURST_SIZE |
1 |
MAX_PENDING_RESPONSES |
4 |
LINEWRAPBURSTS |
0 |
PIPELINE_COMMAND |
1 |
PIPELINE_RESPONSE |
1 |
USE_RESPONSE |
0 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_2_freq_counter_0
freq_counter v1.0
Parameters
SYSTEM_CLK_FREQ_PICO_SEC |
20000 |
DIV |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_3
xcvr_tester v1.0
Parameters
AUTO_GENERATION_ID |
1694674931 |
AUTO_UNIQUE_ID |
q_sys_xcvr_0_tester_3 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CLK_50_CLOCK_RATE |
50000000 |
AUTO_CLK_50_CLOCK_DOMAIN |
5 |
AUTO_CLK_50_RESET_DOMAIN |
5 |
AUTO_RX_CLK_IN_CLK_CLOCK_RATE |
0 |
AUTO_RX_CLK_IN_CLK_CLOCK_DOMAIN |
17 |
AUTO_RX_CLK_IN_CLK_RESET_DOMAIN |
17 |
AUTO_TX_CLK_IN_CLK_CLOCK_RATE |
0 |
AUTO_TX_CLK_IN_CLK_CLOCK_DOMAIN |
18 |
AUTO_TX_CLK_IN_CLK_RESET_DOMAIN |
18 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_3_clk_50
clock_source v22.1
Parameters
clockFrequency |
100000000 |
clockFrequencyKnown |
true |
inputClockFrequency |
50000000 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_3_data_pattern_generator_0
altera_avalon_data_pattern_generator v22.1
Parameters
ST_DATA_W |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_3_data_pattern_checker_0
altera_avalon_data_pattern_checker v22.1
Parameters
ST_DATA_W |
40 |
NUM_CYCLES_FOR_LOCK |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
50000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_3_timing_adapter_tx0
timing_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
NO |
inUseEmpty |
false |
inSymbolsPerBeat |
4 |
inUseReady |
true |
outUseReady |
false |
inReadyLatency |
0 |
outReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
inUseValid |
true |
outUseValid |
false |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_3_timing_adapter_rx0
timing_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
NO |
inUseEmpty |
false |
inSymbolsPerBeat |
4 |
inUseReady |
false |
outUseReady |
true |
inReadyLatency |
0 |
outReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
inUseValid |
false |
outUseValid |
true |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_3_rx_clk
altera_clock_bridge v22.1
Parameters
DERIVED_CLOCK_RATE |
0 |
EXPLICIT_CLOCK_RATE |
0 |
NUM_CLOCK_OUTPUTS |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_3_tx_clk
altera_clock_bridge v22.1
Parameters
DERIVED_CLOCK_RATE |
0 |
EXPLICIT_CLOCK_RATE |
0 |
NUM_CLOCK_OUTPUTS |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_3_data_format_adapter_0
data_format_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
AUTO |
inUseEmpty |
false |
outUseEmptyPort |
AUTO |
outUseEmpty |
false |
inSymbolsPerBeat |
4 |
outSymbolsPerBeat |
4 |
inReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_3_data_format_adapter_1
data_format_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
AUTO |
inUseEmpty |
false |
outUseEmptyPort |
AUTO |
outUseEmpty |
false |
inSymbolsPerBeat |
4 |
outSymbolsPerBeat |
4 |
inReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_3_timer_0
altera_avalon_timer v22.1
Parameters
alwaysRun |
false |
counterSize |
64 |
fixedPeriod |
false |
period |
1 |
periodUnits |
MSEC |
resetOutput |
false |
snapshot |
true |
timeoutPulseOutput |
false |
systemFrequency |
50000000 |
watchdogPulse |
2 |
timerPreset |
FULL_FEATURED |
periodUnitsString |
ms |
valueInSecond |
0.001 |
loadValue |
49999 |
mult |
0.001 |
ticksPerSec |
1000.0 |
slave_address_width |
4 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments
ALWAYS_RUN |
0 |
COUNTER_SIZE |
64 |
FIXED_PERIOD |
0 |
FREQ |
50000000 |
LOAD_VALUE |
49999 |
MULT |
0.001 |
PERIOD |
1 |
PERIOD_UNITS |
ms |
RESET_OUTPUT |
0 |
SNAPSHOT |
1 |
TICKS_PER_SEC |
1000 |
TIMEOUT_PULSE_OUTPUT |
0 |
TIMER_DEVICE_TYPE |
1 |
|
xcvr_0_tester_3_master_driver_com_0
master_driver_com v1.0
Parameters
CHECKER_BASE |
32 |
GENERATOR_BASE |
0 |
TIMER_BASE |
256 |
FREQ_BASE |
512 |
DESERIALIZATION_FACTOR |
40 |
NUM_OF_CH |
1 |
ENABLE_PER_INFO |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_3_mm_bridge_0
altera_avalon_mm_bridge v22.1
Parameters
DATA_WIDTH |
32 |
SYMBOL_WIDTH |
8 |
ADDRESS_WIDTH |
10 |
SYSINFO_ADDR_WIDTH |
10 |
USE_AUTO_ADDRESS_WIDTH |
0 |
AUTO_ADDRESS_WIDTH |
10 |
HDL_ADDR_WIDTH |
10 |
ADDRESS_UNITS |
SYMBOLS |
BURSTCOUNT_WIDTH |
1 |
MAX_BURST_SIZE |
1 |
MAX_PENDING_RESPONSES |
4 |
LINEWRAPBURSTS |
0 |
PIPELINE_COMMAND |
1 |
PIPELINE_RESPONSE |
1 |
USE_RESPONSE |
0 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_tester_3_freq_counter_0
freq_counter v1.0
Parameters
SYSTEM_CLK_FREQ_PICO_SEC |
20000 |
DIV |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_0
altera_xcvr_custom_phy v19.1
Parameters
device_family |
CYCLONEV |
gui_parameter_rules |
Custom |
protocol_hint |
basic |
operation_mode |
Duplex |
lanes |
1 |
gui_bonding_enable |
false |
bonded_group_size |
1 |
gui_bonded_mode |
xN |
bonded_mode |
xN |
gui_pma_bonding_mode |
x1 |
pma_bonding_mode |
x1 |
gui_deser_factor |
40 |
gui_pcs_pma_width |
PARAM_DEFAULT |
pcs_pma_width |
20 |
ser_base_factor |
10 |
ser_words |
4 |
gui_pll_type |
CMU |
data_rate |
5000 Mbps |
gui_base_data_rate |
6250 Mbps |
base_data_rate |
5000 Mbps |
gui_pll_refclk_freq |
100.0 MHz |
en_synce_support |
0 |
gui_tx_bitslip_enable |
false |
tx_bitslip_enable |
false |
gui_rx_use_coreclk |
false |
rx_use_coreclk |
false |
gui_tx_use_coreclk |
false |
tx_use_coreclk |
false |
gui_rx_use_recovered_clk |
false |
gui_use_status |
false |
gui_use_8b10b |
false |
use_8b10b |
false |
gui_use_8b10b_manual_control |
false |
use_8b10b_manual_control |
false |
gui_use_8b10b_status |
false |
std_tx_pcfifo_mode |
low_latency |
std_rx_pcfifo_mode |
low_latency |
word_aligner_mode |
manual |
word_aligner_state_machine_datacnt |
1 |
word_aligner_state_machine_errcnt |
1 |
word_aligner_state_machine_patterncnt |
10 |
gui_use_wa_status |
false |
word_aligner_pattern_length |
20 |
word_align_pattern |
11111001111111110000 |
gui_enable_run_length |
false |
run_length_violation_checking |
40 |
use_rate_match_fifo |
0 |
rate_match_pattern1 |
11010000111010000011 |
rate_match_pattern2 |
00101111000101111100 |
gui_use_rmfifo_status |
false |
byte_order_mode |
none |
gui_use_byte_order_block |
false |
gui_byte_order_pld_ctrl_enable |
false |
byte_order_pattern |
111111011 |
byte_order_pad_pattern |
000000000 |
use_double_data_mode |
DEPRECATED |
coreclk_0ppm_enable |
false |
pll_refclk_cnt |
1 |
pll_refclk_freq |
100.0 MHz |
pll_refclk_select |
0 |
cdr_refclk_select |
0 |
plls |
1 |
pll_type |
CMU |
pll_select |
0 |
pll_reconfig |
0 |
pll_external_enable |
0 |
gxb_analog_power |
AUTO |
pll_lock_speed |
AUTO |
tx_analog_power |
AUTO |
tx_slew_rate |
OFF |
tx_termination |
OCT_100_OHMS |
tx_use_external_termination |
false |
tx_preemp_pretap |
0 |
gui_tx_preemp_pretap_inv |
false |
tx_preemp_pretap_inv |
false |
tx_preemp_tap_1 |
0 |
tx_preemp_tap_2 |
0 |
gui_tx_preemp_tap_2_inv |
false |
tx_preemp_tap_2_inv |
false |
tx_vod_selection |
2 |
tx_common_mode |
0.65V |
rx_pll_lock_speed |
AUTO |
rx_common_mode |
0.82V |
rx_termination |
OCT_100_OHMS |
rx_use_external_termination |
false |
rx_eq_dc_gain |
1 |
rx_eq_ctrl |
16 |
gui_pll_reconfig_enable_pll_reconfig |
false |
gui_pll_reconfig_pll_count |
1 |
gui_pll_reconfig_refclk_count |
1 |
gui_pll_reconfig_main_pll_index |
0 |
gui_pll_reconfig_cdr_pll_refclk_sel |
0 |
gui_pll_reconfig_pll0_pll_type |
CMU |
gui_pll_reconfig_pll0_data_rate |
0 Mbps |
gui_pll_reconfig_pll0_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll0_refclk_freq |
0 MHz |
gui_pll_reconfig_pll0_refclk_sel |
0 |
gui_pll_reconfig_pll0_clk_network |
x1 |
gui_pll_reconfig_pll1_pll_type |
CMU |
gui_pll_reconfig_pll1_data_rate |
0 Mbps |
gui_pll_reconfig_pll1_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll1_refclk_freq |
0 MHz |
gui_pll_reconfig_pll1_refclk_sel |
0 |
gui_pll_reconfig_pll1_clk_network |
x1 |
gui_pll_reconfig_pll2_pll_type |
CMU |
gui_pll_reconfig_pll2_data_rate |
0 Mbps |
gui_pll_reconfig_pll2_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll2_refclk_freq |
0 MHz |
gui_pll_reconfig_pll2_refclk_sel |
0 |
gui_pll_reconfig_pll2_clk_network |
x1 |
gui_pll_reconfig_pll3_pll_type |
CMU |
gui_pll_reconfig_pll3_data_rate |
0 Mbps |
gui_pll_reconfig_pll3_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll3_refclk_freq |
0 MHz |
gui_pll_reconfig_pll3_refclk_sel |
0 |
gui_pll_reconfig_pll3_clk_network |
x1 |
mgmt_clk_in_mhz |
250 |
gui_mgmt_clk_in_hz |
250000000 |
gui_split_interfaces |
1 |
gui_embedded_reset |
1 |
embedded_reset |
1 |
channel_interface |
0 |
manual_reset |
DEPRECATED |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_1
altera_xcvr_custom_phy v19.1
Parameters
device_family |
CYCLONEV |
gui_parameter_rules |
Custom |
protocol_hint |
basic |
operation_mode |
Duplex |
lanes |
1 |
gui_bonding_enable |
false |
bonded_group_size |
1 |
gui_bonded_mode |
xN |
bonded_mode |
xN |
gui_pma_bonding_mode |
x1 |
pma_bonding_mode |
x1 |
gui_deser_factor |
40 |
gui_pcs_pma_width |
PARAM_DEFAULT |
pcs_pma_width |
20 |
ser_base_factor |
10 |
ser_words |
4 |
gui_pll_type |
CMU |
data_rate |
5000 Mbps |
gui_base_data_rate |
6250 Mbps |
base_data_rate |
5000 Mbps |
gui_pll_refclk_freq |
100.0 MHz |
en_synce_support |
0 |
gui_tx_bitslip_enable |
false |
tx_bitslip_enable |
false |
gui_rx_use_coreclk |
false |
rx_use_coreclk |
false |
gui_tx_use_coreclk |
false |
tx_use_coreclk |
false |
gui_rx_use_recovered_clk |
false |
gui_use_status |
false |
gui_use_8b10b |
false |
use_8b10b |
false |
gui_use_8b10b_manual_control |
false |
use_8b10b_manual_control |
false |
gui_use_8b10b_status |
false |
std_tx_pcfifo_mode |
low_latency |
std_rx_pcfifo_mode |
low_latency |
word_aligner_mode |
manual |
word_aligner_state_machine_datacnt |
1 |
word_aligner_state_machine_errcnt |
1 |
word_aligner_state_machine_patterncnt |
10 |
gui_use_wa_status |
false |
word_aligner_pattern_length |
20 |
word_align_pattern |
11111001111111110000 |
gui_enable_run_length |
false |
run_length_violation_checking |
40 |
use_rate_match_fifo |
0 |
rate_match_pattern1 |
11010000111010000011 |
rate_match_pattern2 |
00101111000101111100 |
gui_use_rmfifo_status |
false |
byte_order_mode |
none |
gui_use_byte_order_block |
false |
gui_byte_order_pld_ctrl_enable |
false |
byte_order_pattern |
111111011 |
byte_order_pad_pattern |
000000000 |
use_double_data_mode |
DEPRECATED |
coreclk_0ppm_enable |
false |
pll_refclk_cnt |
1 |
pll_refclk_freq |
100.0 MHz |
pll_refclk_select |
0 |
cdr_refclk_select |
0 |
plls |
1 |
pll_type |
CMU |
pll_select |
0 |
pll_reconfig |
0 |
pll_external_enable |
0 |
gxb_analog_power |
AUTO |
pll_lock_speed |
AUTO |
tx_analog_power |
AUTO |
tx_slew_rate |
OFF |
tx_termination |
OCT_100_OHMS |
tx_use_external_termination |
false |
tx_preemp_pretap |
0 |
gui_tx_preemp_pretap_inv |
false |
tx_preemp_pretap_inv |
false |
tx_preemp_tap_1 |
0 |
tx_preemp_tap_2 |
0 |
gui_tx_preemp_tap_2_inv |
false |
tx_preemp_tap_2_inv |
false |
tx_vod_selection |
2 |
tx_common_mode |
0.65V |
rx_pll_lock_speed |
AUTO |
rx_common_mode |
0.82V |
rx_termination |
OCT_100_OHMS |
rx_use_external_termination |
false |
rx_eq_dc_gain |
1 |
rx_eq_ctrl |
16 |
gui_pll_reconfig_enable_pll_reconfig |
false |
gui_pll_reconfig_pll_count |
1 |
gui_pll_reconfig_refclk_count |
1 |
gui_pll_reconfig_main_pll_index |
0 |
gui_pll_reconfig_cdr_pll_refclk_sel |
0 |
gui_pll_reconfig_pll0_pll_type |
CMU |
gui_pll_reconfig_pll0_data_rate |
0 Mbps |
gui_pll_reconfig_pll0_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll0_refclk_freq |
0 MHz |
gui_pll_reconfig_pll0_refclk_sel |
0 |
gui_pll_reconfig_pll0_clk_network |
x1 |
gui_pll_reconfig_pll1_pll_type |
CMU |
gui_pll_reconfig_pll1_data_rate |
0 Mbps |
gui_pll_reconfig_pll1_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll1_refclk_freq |
0 MHz |
gui_pll_reconfig_pll1_refclk_sel |
0 |
gui_pll_reconfig_pll1_clk_network |
x1 |
gui_pll_reconfig_pll2_pll_type |
CMU |
gui_pll_reconfig_pll2_data_rate |
0 Mbps |
gui_pll_reconfig_pll2_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll2_refclk_freq |
0 MHz |
gui_pll_reconfig_pll2_refclk_sel |
0 |
gui_pll_reconfig_pll2_clk_network |
x1 |
gui_pll_reconfig_pll3_pll_type |
CMU |
gui_pll_reconfig_pll3_data_rate |
0 Mbps |
gui_pll_reconfig_pll3_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll3_refclk_freq |
0 MHz |
gui_pll_reconfig_pll3_refclk_sel |
0 |
gui_pll_reconfig_pll3_clk_network |
x1 |
mgmt_clk_in_mhz |
250 |
gui_mgmt_clk_in_hz |
250000000 |
gui_split_interfaces |
1 |
gui_embedded_reset |
1 |
embedded_reset |
1 |
channel_interface |
0 |
manual_reset |
DEPRECATED |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_2
altera_xcvr_custom_phy v19.1
Parameters
device_family |
CYCLONEV |
gui_parameter_rules |
Custom |
protocol_hint |
basic |
operation_mode |
Duplex |
lanes |
1 |
gui_bonding_enable |
false |
bonded_group_size |
1 |
gui_bonded_mode |
xN |
bonded_mode |
xN |
gui_pma_bonding_mode |
x1 |
pma_bonding_mode |
x1 |
gui_deser_factor |
40 |
gui_pcs_pma_width |
PARAM_DEFAULT |
pcs_pma_width |
20 |
ser_base_factor |
10 |
ser_words |
4 |
gui_pll_type |
CMU |
data_rate |
5000 Mbps |
gui_base_data_rate |
6250 Mbps |
base_data_rate |
5000 Mbps |
gui_pll_refclk_freq |
100.0 MHz |
en_synce_support |
0 |
gui_tx_bitslip_enable |
false |
tx_bitslip_enable |
false |
gui_rx_use_coreclk |
false |
rx_use_coreclk |
false |
gui_tx_use_coreclk |
false |
tx_use_coreclk |
false |
gui_rx_use_recovered_clk |
false |
gui_use_status |
false |
gui_use_8b10b |
false |
use_8b10b |
false |
gui_use_8b10b_manual_control |
false |
use_8b10b_manual_control |
false |
gui_use_8b10b_status |
false |
std_tx_pcfifo_mode |
low_latency |
std_rx_pcfifo_mode |
low_latency |
word_aligner_mode |
manual |
word_aligner_state_machine_datacnt |
1 |
word_aligner_state_machine_errcnt |
1 |
word_aligner_state_machine_patterncnt |
10 |
gui_use_wa_status |
false |
word_aligner_pattern_length |
20 |
word_align_pattern |
11111001111111110000 |
gui_enable_run_length |
false |
run_length_violation_checking |
40 |
use_rate_match_fifo |
0 |
rate_match_pattern1 |
11010000111010000011 |
rate_match_pattern2 |
00101111000101111100 |
gui_use_rmfifo_status |
false |
byte_order_mode |
none |
gui_use_byte_order_block |
false |
gui_byte_order_pld_ctrl_enable |
false |
byte_order_pattern |
111111011 |
byte_order_pad_pattern |
000000000 |
use_double_data_mode |
DEPRECATED |
coreclk_0ppm_enable |
false |
pll_refclk_cnt |
1 |
pll_refclk_freq |
100.0 MHz |
pll_refclk_select |
0 |
cdr_refclk_select |
0 |
plls |
1 |
pll_type |
CMU |
pll_select |
0 |
pll_reconfig |
0 |
pll_external_enable |
0 |
gxb_analog_power |
AUTO |
pll_lock_speed |
AUTO |
tx_analog_power |
AUTO |
tx_slew_rate |
OFF |
tx_termination |
OCT_100_OHMS |
tx_use_external_termination |
false |
tx_preemp_pretap |
0 |
gui_tx_preemp_pretap_inv |
false |
tx_preemp_pretap_inv |
false |
tx_preemp_tap_1 |
0 |
tx_preemp_tap_2 |
0 |
gui_tx_preemp_tap_2_inv |
false |
tx_preemp_tap_2_inv |
false |
tx_vod_selection |
2 |
tx_common_mode |
0.65V |
rx_pll_lock_speed |
AUTO |
rx_common_mode |
0.82V |
rx_termination |
OCT_100_OHMS |
rx_use_external_termination |
false |
rx_eq_dc_gain |
1 |
rx_eq_ctrl |
16 |
gui_pll_reconfig_enable_pll_reconfig |
false |
gui_pll_reconfig_pll_count |
1 |
gui_pll_reconfig_refclk_count |
1 |
gui_pll_reconfig_main_pll_index |
0 |
gui_pll_reconfig_cdr_pll_refclk_sel |
0 |
gui_pll_reconfig_pll0_pll_type |
CMU |
gui_pll_reconfig_pll0_data_rate |
0 Mbps |
gui_pll_reconfig_pll0_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll0_refclk_freq |
0 MHz |
gui_pll_reconfig_pll0_refclk_sel |
0 |
gui_pll_reconfig_pll0_clk_network |
x1 |
gui_pll_reconfig_pll1_pll_type |
CMU |
gui_pll_reconfig_pll1_data_rate |
0 Mbps |
gui_pll_reconfig_pll1_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll1_refclk_freq |
0 MHz |
gui_pll_reconfig_pll1_refclk_sel |
0 |
gui_pll_reconfig_pll1_clk_network |
x1 |
gui_pll_reconfig_pll2_pll_type |
CMU |
gui_pll_reconfig_pll2_data_rate |
0 Mbps |
gui_pll_reconfig_pll2_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll2_refclk_freq |
0 MHz |
gui_pll_reconfig_pll2_refclk_sel |
0 |
gui_pll_reconfig_pll2_clk_network |
x1 |
gui_pll_reconfig_pll3_pll_type |
CMU |
gui_pll_reconfig_pll3_data_rate |
0 Mbps |
gui_pll_reconfig_pll3_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll3_refclk_freq |
0 MHz |
gui_pll_reconfig_pll3_refclk_sel |
0 |
gui_pll_reconfig_pll3_clk_network |
x1 |
mgmt_clk_in_mhz |
250 |
gui_mgmt_clk_in_hz |
250000000 |
gui_split_interfaces |
1 |
gui_embedded_reset |
1 |
embedded_reset |
1 |
channel_interface |
0 |
manual_reset |
DEPRECATED |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_3
altera_xcvr_custom_phy v19.1
Parameters
device_family |
CYCLONEV |
gui_parameter_rules |
Custom |
protocol_hint |
basic |
operation_mode |
Duplex |
lanes |
1 |
gui_bonding_enable |
false |
bonded_group_size |
1 |
gui_bonded_mode |
xN |
bonded_mode |
xN |
gui_pma_bonding_mode |
x1 |
pma_bonding_mode |
x1 |
gui_deser_factor |
40 |
gui_pcs_pma_width |
PARAM_DEFAULT |
pcs_pma_width |
20 |
ser_base_factor |
10 |
ser_words |
4 |
gui_pll_type |
CMU |
data_rate |
5000 Mbps |
gui_base_data_rate |
6250 Mbps |
base_data_rate |
5000 Mbps |
gui_pll_refclk_freq |
100.0 MHz |
en_synce_support |
0 |
gui_tx_bitslip_enable |
false |
tx_bitslip_enable |
false |
gui_rx_use_coreclk |
false |
rx_use_coreclk |
false |
gui_tx_use_coreclk |
false |
tx_use_coreclk |
false |
gui_rx_use_recovered_clk |
false |
gui_use_status |
false |
gui_use_8b10b |
false |
use_8b10b |
false |
gui_use_8b10b_manual_control |
false |
use_8b10b_manual_control |
false |
gui_use_8b10b_status |
false |
std_tx_pcfifo_mode |
low_latency |
std_rx_pcfifo_mode |
low_latency |
word_aligner_mode |
manual |
word_aligner_state_machine_datacnt |
1 |
word_aligner_state_machine_errcnt |
1 |
word_aligner_state_machine_patterncnt |
10 |
gui_use_wa_status |
false |
word_aligner_pattern_length |
20 |
word_align_pattern |
11111001111111110000 |
gui_enable_run_length |
false |
run_length_violation_checking |
40 |
use_rate_match_fifo |
0 |
rate_match_pattern1 |
11010000111010000011 |
rate_match_pattern2 |
00101111000101111100 |
gui_use_rmfifo_status |
false |
byte_order_mode |
none |
gui_use_byte_order_block |
false |
gui_byte_order_pld_ctrl_enable |
false |
byte_order_pattern |
111111011 |
byte_order_pad_pattern |
000000000 |
use_double_data_mode |
DEPRECATED |
coreclk_0ppm_enable |
false |
pll_refclk_cnt |
1 |
pll_refclk_freq |
100.0 MHz |
pll_refclk_select |
0 |
cdr_refclk_select |
0 |
plls |
1 |
pll_type |
CMU |
pll_select |
0 |
pll_reconfig |
0 |
pll_external_enable |
0 |
gxb_analog_power |
AUTO |
pll_lock_speed |
AUTO |
tx_analog_power |
AUTO |
tx_slew_rate |
OFF |
tx_termination |
OCT_100_OHMS |
tx_use_external_termination |
false |
tx_preemp_pretap |
0 |
gui_tx_preemp_pretap_inv |
false |
tx_preemp_pretap_inv |
false |
tx_preemp_tap_1 |
0 |
tx_preemp_tap_2 |
0 |
gui_tx_preemp_tap_2_inv |
false |
tx_preemp_tap_2_inv |
false |
tx_vod_selection |
2 |
tx_common_mode |
0.65V |
rx_pll_lock_speed |
AUTO |
rx_common_mode |
0.82V |
rx_termination |
OCT_100_OHMS |
rx_use_external_termination |
false |
rx_eq_dc_gain |
1 |
rx_eq_ctrl |
16 |
gui_pll_reconfig_enable_pll_reconfig |
false |
gui_pll_reconfig_pll_count |
1 |
gui_pll_reconfig_refclk_count |
1 |
gui_pll_reconfig_main_pll_index |
0 |
gui_pll_reconfig_cdr_pll_refclk_sel |
0 |
gui_pll_reconfig_pll0_pll_type |
CMU |
gui_pll_reconfig_pll0_data_rate |
0 Mbps |
gui_pll_reconfig_pll0_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll0_refclk_freq |
0 MHz |
gui_pll_reconfig_pll0_refclk_sel |
0 |
gui_pll_reconfig_pll0_clk_network |
x1 |
gui_pll_reconfig_pll1_pll_type |
CMU |
gui_pll_reconfig_pll1_data_rate |
0 Mbps |
gui_pll_reconfig_pll1_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll1_refclk_freq |
0 MHz |
gui_pll_reconfig_pll1_refclk_sel |
0 |
gui_pll_reconfig_pll1_clk_network |
x1 |
gui_pll_reconfig_pll2_pll_type |
CMU |
gui_pll_reconfig_pll2_data_rate |
0 Mbps |
gui_pll_reconfig_pll2_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll2_refclk_freq |
0 MHz |
gui_pll_reconfig_pll2_refclk_sel |
0 |
gui_pll_reconfig_pll2_clk_network |
x1 |
gui_pll_reconfig_pll3_pll_type |
CMU |
gui_pll_reconfig_pll3_data_rate |
0 Mbps |
gui_pll_reconfig_pll3_data_rate_der |
5000 Mbps |
gui_pll_reconfig_pll3_refclk_freq |
0 MHz |
gui_pll_reconfig_pll3_refclk_sel |
0 |
gui_pll_reconfig_pll3_clk_network |
x1 |
mgmt_clk_in_mhz |
250 |
gui_mgmt_clk_in_hz |
250000000 |
gui_split_interfaces |
1 |
gui_embedded_reset |
1 |
embedded_reset |
1 |
channel_interface |
0 |
manual_reset |
DEPRECATED |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
generation took 0.00 seconds |
rendering took 0.15 seconds |