q_sys

2015.11.09.17:10:36 Datasheet
Overview
  clk_100  q_sys
  cmos_0_clkin 
  xcvr_0_clk_100 
  xcvr_0_tester_0_clk_50 
  xcvr_0_tester_1_clk_50 
  xcvr_0_tester_2_clk_50 
  xcvr_0_tester_3_clk_50 
  xcvr_0_clk_50 
  clk_50 

All Components
   cmos_0 q_sys_cmos 1.0
   cmos_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 15.1
   cmos_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 15.1
   cmos_0_mm_bridge_0 altera_avalon_mm_bridge 15.1
   cmos_0_master_driver_com_0 master_driver_com 1.0
   cmos_0_timer_0 altera_avalon_timer 15.1
   cmos_0_freq_counter_0 freq_counter 1.0
   xcvr_0 q_sys_xcvr 1.0
   xcvr_0_xcvr_custom_phy_0 altera_xcvr_custom_phy 15.1
   xcvr_0_alt_xcvr_reconfig_0 alt_xcvr_reconfig 15.1
   xcvr_0_tester_0 xcvr_tester 1.0
   xcvr_0_tester_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 15.1
   xcvr_0_tester_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 15.1
   xcvr_0_tester_0_timer_0 altera_avalon_timer 15.1
   xcvr_0_tester_0_master_driver_com_0 master_driver_com 1.0
   xcvr_0_tester_0_mm_bridge_0 altera_avalon_mm_bridge 15.1
   xcvr_0_tester_0_freq_counter_0 freq_counter 1.0
   xcvr_0_tester_1 xcvr_tester 1.0
   xcvr_0_tester_1_data_pattern_generator_0 altera_avalon_data_pattern_generator 15.1
   xcvr_0_tester_1_data_pattern_checker_0 altera_avalon_data_pattern_checker 15.1
   xcvr_0_tester_1_timer_0 altera_avalon_timer 15.1
   xcvr_0_tester_1_master_driver_com_0 master_driver_com 1.0
   xcvr_0_tester_1_mm_bridge_0 altera_avalon_mm_bridge 15.1
   xcvr_0_tester_1_freq_counter_0 freq_counter 1.0
   xcvr_0_tester_2 xcvr_tester 1.0
   xcvr_0_tester_2_data_pattern_generator_0 altera_avalon_data_pattern_generator 15.1
   xcvr_0_tester_2_data_pattern_checker_0 altera_avalon_data_pattern_checker 15.1
   xcvr_0_tester_2_timer_0 altera_avalon_timer 15.1
   xcvr_0_tester_2_master_driver_com_0 master_driver_com 1.0
   xcvr_0_tester_2_mm_bridge_0 altera_avalon_mm_bridge 15.1
   xcvr_0_tester_2_freq_counter_0 freq_counter 1.0
   xcvr_0_tester_3 xcvr_tester 1.0
   xcvr_0_tester_3_data_pattern_generator_0 altera_avalon_data_pattern_generator 15.1
   xcvr_0_tester_3_data_pattern_checker_0 altera_avalon_data_pattern_checker 15.1
   xcvr_0_tester_3_timer_0 altera_avalon_timer 15.1
   xcvr_0_tester_3_master_driver_com_0 master_driver_com 1.0
   xcvr_0_tester_3_mm_bridge_0 altera_avalon_mm_bridge 15.1
   xcvr_0_tester_3_freq_counter_0 freq_counter 1.0
   xcvr_0_mm_bridge_0 altera_avalon_mm_bridge 15.1
   product_info_0 product_info 1.0
Memory Map
master_0 cmos_0_master_driver_com_0 xcvr_0_tester_0_master_driver_com_0 xcvr_0_tester_1_master_driver_com_0 xcvr_0_tester_2_master_driver_com_0 xcvr_0_tester_3_master_driver_com_0
 master  avalon_master  avalon_master  avalon_master  avalon_master  avalon_master
  cmos_0
mm_bridge_0_s0 
  cmos_0_data_pattern_generator_0
csr_slave  0x00300000 0x00000000
  cmos_0_data_pattern_checker_0
csr_slave  0x00300020 0x00000020
  cmos_0_master_driver_com_0
csr  0x00300300
  cmos_0_timer_0
s1  0x00300100 0x00000100
  cmos_0_freq_counter_0
csr  0x00300200 0x00000200
  xcvr_0
mm_bridge_0_s0 
  xcvr_0_xcvr_custom_phy_0
phy_mgmt  0x00100000
  xcvr_0_alt_xcvr_reconfig_0
reconfig_mgmt  0x00100800
  xcvr_0_tester_0
mm_bridge_0_s0 
  xcvr_0_tester_0_data_pattern_generator_0
csr_slave  0x00101000 0x00000000
  xcvr_0_tester_0_data_pattern_checker_0
csr_slave  0x00101020 0x00000020
  xcvr_0_tester_0_timer_0
s1  0x00101100 0x00000100
  xcvr_0_tester_0_master_driver_com_0
csr  0x00101300
  xcvr_0_tester_0_freq_counter_0
csr  0x00101200 0x00000200
  xcvr_0_tester_1
mm_bridge_0_s0 
  xcvr_0_tester_1_data_pattern_generator_0
csr_slave  0x00102000 0x00000000
  xcvr_0_tester_1_data_pattern_checker_0
csr_slave  0x00102020 0x00000020
  xcvr_0_tester_1_timer_0
s1  0x00102100 0x00000100
  xcvr_0_tester_1_master_driver_com_0
csr  0x00102300
  xcvr_0_tester_1_freq_counter_0
csr  0x00102200 0x00000200
  xcvr_0_tester_2
mm_bridge_0_s0 
  xcvr_0_tester_2_data_pattern_generator_0
csr_slave  0x00103000 0x00000000
  xcvr_0_tester_2_data_pattern_checker_0
csr_slave  0x00103020 0x00000020
  xcvr_0_tester_2_timer_0
s1  0x00103100 0x00000100
  xcvr_0_tester_2_master_driver_com_0
csr  0x00103300
  xcvr_0_tester_2_freq_counter_0
csr  0x00103200 0x00000200
  xcvr_0_tester_3
mm_bridge_0_s0 
  xcvr_0_tester_3_data_pattern_generator_0
csr_slave  0x00104000 0x00000000
  xcvr_0_tester_3_data_pattern_checker_0
csr_slave  0x00104020 0x00000020
  xcvr_0_tester_3_timer_0
s1  0x00104100 0x00000100
  xcvr_0_tester_3_master_driver_com_0
csr  0x00104300
  xcvr_0_tester_3_freq_counter_0
csr  0x00104200 0x00000200
  product_info_0
avalon_slave_0  0x00000000

clk_100

clock_source v15.1


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

master_0

altera_jtag_avalon_master v15.1
clk_50 clk   master_0
  clk
clk_reset  
  clk_reset
master   cmos_0_mm_bridge_0
  s0
master   xcvr_0_mm_bridge_0
  s0
master   product_info_0
  avalon_slave_0


Parameters

USE_PLI 0
PLI_PORT 50000
COMPONENT_CLOCK 0
FAST_VER 0
FIFO_DEPTHS 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

cmos_0

q_sys_cmos v1.0


Parameters

AUTO_GENERATION_ID 1447060235
AUTO_UNIQUE_ID q_sys_cmos_0
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CLKIN_CLOCK_RATE 50000000
AUTO_CLKIN_CLOCK_DOMAIN 3
AUTO_CLKIN_RESET_DOMAIN 3
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

cmos_0_clkin

clock_source v15.1
clk_50 clk   cmos_0_clkin
  clk_in
clk_reset  
  clk_in_reset
clk   cmos_0_mm_bridge_0
  clk
clk_reset  
  reset
clk   cmos_0_tx_clk
  in_clk
clk   cmos_0_rx_clk
  in_clk
clk   cmos_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
clk   cmos_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk_reset   cmos_0_master_driver_com_0
  reset
clk  
  clock
clk   cmos_0_timer_0
  clk
clk_reset  
  reset
clk_reset   cmos_0_freq_counter_0
  reset
clk  
  clock


Parameters

clockFrequency 100000000
clockFrequencyKnown false
inputClockFrequency 50000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cmos_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v15.1
cmos_0_tx_clk out_clk   cmos_0_data_pattern_generator_0
  pattern_out_clk
cmos_0_mm_bridge_0 m0  
  csr_slave
cmos_0_clkin clk  
  csr_clk
clk_reset  
  reset
cmos_0_master_driver_com_0 avalon_master  
  csr_slave


Parameters

ST_DATA_W 50
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 50000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

cmos_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v15.1
cmos_0_rx_clk out_clk   cmos_0_data_pattern_checker_0
  pattern_in_clk
cmos_0_mm_bridge_0 m0  
  csr_slave
cmos_0_clkin clk  
  csr_clk
clk_reset  
  reset
cmos_0_master_driver_com_0 avalon_master  
  csr_slave


Parameters

ST_DATA_W 50
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 50000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

cmos_0_rx_clk

altera_clock_bridge v15.1
cmos_0_clkin clk   cmos_0_rx_clk
  in_clk
out_clk   cmos_0_data_pattern_checker_0
  pattern_in_clk
out_clk   cmos_0_freq_counter_0
  sample_clock


Parameters

DERIVED_CLOCK_RATE 50000000
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cmos_0_tx_clk

altera_clock_bridge v15.1
cmos_0_clkin clk   cmos_0_tx_clk
  in_clk
out_clk   cmos_0_data_pattern_generator_0
  pattern_out_clk


Parameters

DERIVED_CLOCK_RATE 50000000
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cmos_0_mm_bridge_0

altera_avalon_mm_bridge v15.1
cmos_0_clkin clk   cmos_0_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   cmos_0_data_pattern_checker_0
  csr_slave
m0   cmos_0_data_pattern_generator_0
  csr_slave
m0   cmos_0_master_driver_com_0
  csr
m0   cmos_0_timer_0
  s1
m0   cmos_0_freq_counter_0
  csr


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 10
SYSINFO_ADDR_WIDTH 10
USE_AUTO_ADDRESS_WIDTH 0
AUTO_ADDRESS_WIDTH 10
HDL_ADDR_WIDTH 10
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 4
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
USE_RESPONSE 0
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_CLK_CLOCK_RATE 50000000
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

cmos_0_master_driver_com_0

master_driver_com v1.0
cmos_0_clkin clk_reset   cmos_0_master_driver_com_0
  reset
clk  
  clock
cmos_0_mm_bridge_0 m0  
  csr
avalon_master   cmos_0_data_pattern_checker_0
  csr_slave
avalon_master   cmos_0_data_pattern_generator_0
  csr_slave
avalon_master   cmos_0_timer_0
  s1
avalon_master   cmos_0_freq_counter_0
  csr


Parameters

CHECKER_BASE 32
GENERATOR_BASE 0
TIMER_BASE 256
FREQ_BASE 512
DESERIALIZATION_FACTOR 8
NUM_OF_CH 16
ENABLE_PER_INFO 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cmos_0_timer_0

altera_avalon_timer v15.1
cmos_0_clkin clk   cmos_0_timer_0
  clk
clk_reset  
  reset
cmos_0_mm_bridge_0 m0  
  s1
cmos_0_master_driver_com_0 avalon_master  
  s1


Parameters

alwaysRun false
counterSize 64
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 50000000
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0.001
loadValue 49999
mult 0.001
ticksPerSec 1000.0
slave_address_width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 64
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0

cmos_0_freq_counter_0

freq_counter v1.0
cmos_0_clkin clk_reset   cmos_0_freq_counter_0
  reset
clk  
  clock
cmos_0_master_driver_com_0 avalon_master  
  csr
cmos_0_mm_bridge_0 m0  
  csr
cmos_0_rx_clk out_clk  
  sample_clock


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 20000
DIV 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0

q_sys_xcvr v1.0


Parameters

AUTO_GENERATION_ID 1447060235
AUTO_UNIQUE_ID q_sys_xcvr_0
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CLK_100_CLOCK_RATE 100000000
AUTO_CLK_100_CLOCK_DOMAIN 1
AUTO_CLK_100_RESET_DOMAIN 1
AUTO_XCVR_CUSTOM_PHY_0_PLL_REF_CLK_CLOCK_RATE 0
AUTO_XCVR_CUSTOM_PHY_0_PLL_REF_CLK_CLOCK_DOMAIN 5
AUTO_XCVR_CUSTOM_PHY_0_PLL_REF_CLK_RESET_DOMAIN 5
AUTO_CLK_50_CLOCK_RATE 50000000
AUTO_CLK_50_CLOCK_DOMAIN 3
AUTO_CLK_50_RESET_DOMAIN 3
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_clk_100

clock_source v15.1
clk_100 clk   xcvr_0_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk_reset   xcvr_0_xcvr_custom_phy_0
  phy_mgmt_clk_reset
clk  
  phy_mgmt_clk
clk   xcvr_0_alt_xcvr_reconfig_0
  mgmt_clk_clk
clk_reset  
  mgmt_rst_reset


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 100000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_xcvr_custom_phy_0

altera_xcvr_custom_phy v15.1
xcvr_0_clk_100 clk_reset   xcvr_0_xcvr_custom_phy_0
  phy_mgmt_clk_reset
clk  
  phy_mgmt_clk
xcvr_0_tester_0_timing_adapter_tx0 out  
  tx_parallel_data0
xcvr_0_tester_1_timing_adapter_tx0 out  
  tx_parallel_data1
xcvr_0_tester_2_timing_adapter_tx0 out  
  tx_parallel_data2
xcvr_0_tester_3_timing_adapter_tx0 out  
  tx_parallel_data3
xcvr_0_mm_bridge_0 m0  
  phy_mgmt
reconfig_to_xcvr   xcvr_0_alt_xcvr_reconfig_0
  reconfig_to_xcvr
reconfig_from_xcvr  
  reconfig_from_xcvr
rx_clkout0   xcvr_0_tester_0_rx_clk
  in_clk
tx_clkout0   xcvr_0_tester_0_tx_clk
  in_clk
rx_parallel_data0   xcvr_0_tester_0_timing_adapter_rx0
  in
rx_clkout1   xcvr_0_tester_1_rx_clk
  in_clk
tx_clkout1   xcvr_0_tester_1_tx_clk
  in_clk
rx_clkout2   xcvr_0_tester_2_rx_clk
  in_clk
tx_clkout2   xcvr_0_tester_2_tx_clk
  in_clk
rx_clkout3   xcvr_0_tester_3_rx_clk
  in_clk
tx_clkout3   xcvr_0_tester_3_tx_clk
  in_clk
rx_parallel_data1   xcvr_0_tester_1_timing_adapter_rx0
  in
rx_parallel_data2   xcvr_0_tester_2_timing_adapter_rx0
  in
rx_parallel_data3   xcvr_0_tester_3_timing_adapter_rx0
  in


Parameters

device_family CYCLONEV
gui_parameter_rules Custom
protocol_hint basic
operation_mode Duplex
lanes 4
gui_bonding_enable false
bonded_group_size 1
gui_bonded_mode xN
bonded_mode xN
gui_pma_bonding_mode xN
pma_bonding_mode xN
gui_deser_factor 40
gui_pcs_pma_width PARAM_DEFAULT
pcs_pma_width 20
ser_base_factor 10
ser_words 4
gui_pll_type CMU
data_rate 5000 Mbps
gui_base_data_rate 6250 Mbps
base_data_rate 5000 Mbps
gui_pll_refclk_freq 100.0 MHz
en_synce_support 0
gui_tx_bitslip_enable false
tx_bitslip_enable false
gui_rx_use_coreclk false
rx_use_coreclk false
gui_tx_use_coreclk false
tx_use_coreclk false
gui_rx_use_recovered_clk false
gui_use_status false
gui_use_8b10b false
use_8b10b false
gui_use_8b10b_manual_control false
use_8b10b_manual_control false
gui_use_8b10b_status false
std_tx_pcfifo_mode low_latency
std_rx_pcfifo_mode low_latency
word_aligner_mode manual
word_aligner_state_machine_datacnt 1
word_aligner_state_machine_errcnt 1
word_aligner_state_machine_patterncnt 10
gui_use_wa_status false
word_aligner_pattern_length 20
word_align_pattern 11111001111111110000
gui_enable_run_length false
run_length_violation_checking 40
use_rate_match_fifo 0
rate_match_pattern1 11010000111010000011
rate_match_pattern2 00101111000101111100
gui_use_rmfifo_status false
byte_order_mode none
gui_use_byte_order_block false
gui_byte_order_pld_ctrl_enable false
byte_order_pattern 111111011
byte_order_pad_pattern 000000000
use_double_data_mode DEPRECATED
coreclk_0ppm_enable false
pll_refclk_cnt 1
pll_refclk_freq 100.0 MHz
pll_refclk_select 0
cdr_refclk_select 0
plls 1
pll_type CMU
pll_select 0
pll_reconfig 0
pll_external_enable 0
gxb_analog_power AUTO
pll_lock_speed AUTO
tx_analog_power AUTO
tx_slew_rate OFF
tx_termination OCT_100_OHMS
tx_use_external_termination false
tx_preemp_pretap 0
gui_tx_preemp_pretap_inv false
tx_preemp_pretap_inv false
tx_preemp_tap_1 0
tx_preemp_tap_2 0
gui_tx_preemp_tap_2_inv false
tx_preemp_tap_2_inv false
tx_vod_selection 2
tx_common_mode 0.65V
rx_pll_lock_speed AUTO
rx_common_mode 0.82V
rx_termination OCT_100_OHMS
rx_use_external_termination false
rx_eq_dc_gain 1
rx_eq_ctrl 16
gui_pll_reconfig_enable_pll_reconfig false
gui_pll_reconfig_pll_count 1
gui_pll_reconfig_refclk_count 1
gui_pll_reconfig_main_pll_index 0
gui_pll_reconfig_cdr_pll_refclk_sel 0
gui_pll_reconfig_pll0_pll_type CMU
gui_pll_reconfig_pll0_data_rate 0 Mbps
gui_pll_reconfig_pll0_data_rate_der 5000 Mbps
gui_pll_reconfig_pll0_refclk_freq 0 MHz
gui_pll_reconfig_pll0_refclk_sel 0
gui_pll_reconfig_pll0_clk_network x1
gui_pll_reconfig_pll1_pll_type CMU
gui_pll_reconfig_pll1_data_rate 0 Mbps
gui_pll_reconfig_pll1_data_rate_der 5000 Mbps
gui_pll_reconfig_pll1_refclk_freq 0 MHz
gui_pll_reconfig_pll1_refclk_sel 0
gui_pll_reconfig_pll1_clk_network x1
gui_pll_reconfig_pll2_pll_type CMU
gui_pll_reconfig_pll2_data_rate 0 Mbps
gui_pll_reconfig_pll2_data_rate_der 5000 Mbps
gui_pll_reconfig_pll2_refclk_freq 0 MHz
gui_pll_reconfig_pll2_refclk_sel 0
gui_pll_reconfig_pll2_clk_network x1
gui_pll_reconfig_pll3_pll_type CMU
gui_pll_reconfig_pll3_data_rate 0 Mbps
gui_pll_reconfig_pll3_data_rate_der 5000 Mbps
gui_pll_reconfig_pll3_refclk_freq 0 MHz
gui_pll_reconfig_pll3_refclk_sel 0
gui_pll_reconfig_pll3_clk_network x1
mgmt_clk_in_mhz 250
gui_mgmt_clk_in_hz 250000000
gui_split_interfaces 1
gui_embedded_reset 1
embedded_reset 1
channel_interface 0
manual_reset DEPRECATED
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_alt_xcvr_reconfig_0

alt_xcvr_reconfig v15.1
xcvr_0_xcvr_custom_phy_0 reconfig_to_xcvr   xcvr_0_alt_xcvr_reconfig_0
  reconfig_to_xcvr
reconfig_from_xcvr  
  reconfig_from_xcvr
xcvr_0_clk_100 clk  
  mgmt_clk_clk
clk_reset  
  mgmt_rst_reset
xcvr_0_mm_bridge_0 m0  
  reconfig_mgmt


Parameters

device_family CYCLONEV
number_of_reconfig_interfaces 8
gui_split_sizes
enable_offset 1
enable_lc 0
enable_dcd 1
enable_dcd_power_up 1
enable_analog 1
enable_eyemon 0
ber_en 0
enable_ber 0
enable_dfe 0
enable_adce 0
enable_mif 0
gui_enable_pll 0
enable_pll 0
gui_cal_status_port false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_0

xcvr_tester v1.0


Parameters

AUTO_GENERATION_ID 1447060235
AUTO_UNIQUE_ID q_sys_xcvr_0_tester_0
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CLK_50_CLOCK_RATE 50000000
AUTO_CLK_50_CLOCK_DOMAIN 6
AUTO_CLK_50_RESET_DOMAIN 6
AUTO_RX_CLK_IN_CLK_CLOCK_RATE 0
AUTO_RX_CLK_IN_CLK_CLOCK_DOMAIN 8
AUTO_RX_CLK_IN_CLK_RESET_DOMAIN 8
AUTO_TX_CLK_IN_CLK_CLOCK_RATE 0
AUTO_TX_CLK_IN_CLK_CLOCK_DOMAIN 12
AUTO_TX_CLK_IN_CLK_RESET_DOMAIN 12
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_0_clk_50

clock_source v15.1
xcvr_0_clk_50 clk   xcvr_0_tester_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk_reset   xcvr_0_tester_0_timing_adapter_tx0
  reset
clk_reset   xcvr_0_tester_0_timing_adapter_rx0
  reset
clk   xcvr_0_tester_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
clk   xcvr_0_tester_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk_reset   xcvr_0_tester_0_data_format_adapter_0
  reset
clk_reset   xcvr_0_tester_0_data_format_adapter_1
  reset
clk   xcvr_0_tester_0_timer_0
  clk
clk_reset  
  reset
clk_reset   xcvr_0_tester_0_master_driver_com_0
  reset
clk  
  clock
clk   xcvr_0_tester_0_mm_bridge_0
  clk
clk_reset  
  reset
clk_reset   xcvr_0_tester_0_freq_counter_0
  reset
clk  
  clock


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 50000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v15.1
xcvr_0_tester_0_clk_50 clk   xcvr_0_tester_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
xcvr_0_tester_0_tx_clk out_clk  
  pattern_out_clk
xcvr_0_tester_0_mm_bridge_0 m0  
  csr_slave
xcvr_0_tester_0_master_driver_com_0 avalon_master  
  csr_slave
pattern_out   xcvr_0_tester_0_data_format_adapter_0
  in


Parameters

ST_DATA_W 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 50000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v15.1
xcvr_0_tester_0_clk_50 clk   xcvr_0_tester_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
xcvr_0_tester_0_rx_clk out_clk  
  pattern_in_clk
xcvr_0_tester_0_data_format_adapter_1 out  
  pattern_in
xcvr_0_tester_0_mm_bridge_0 m0  
  csr_slave
xcvr_0_tester_0_master_driver_com_0 avalon_master  
  csr_slave


Parameters

ST_DATA_W 40
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 50000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_0_timing_adapter_tx0

timing_adapter v15.1
xcvr_0_tester_0_clk_50 clk_reset   xcvr_0_tester_0_timing_adapter_tx0
  reset
xcvr_0_tester_0_tx_clk out_clk  
  clk
xcvr_0_tester_0_data_format_adapter_0 out  
  in
out   xcvr_0_xcvr_custom_phy_0
  tx_parallel_data0


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort NO
inUseEmpty false
inSymbolsPerBeat 4
inUseReady true
outUseReady false
inReadyLatency 0
outReadyLatency 0
inErrorWidth 0
inErrorDescriptor
inUseValid true
outUseValid false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_0_timing_adapter_rx0

timing_adapter v15.1
xcvr_0_tester_0_clk_50 clk_reset   xcvr_0_tester_0_timing_adapter_rx0
  reset
xcvr_0_tester_0_rx_clk out_clk  
  clk
xcvr_0_xcvr_custom_phy_0 rx_parallel_data0  
  in
out   xcvr_0_tester_0_data_format_adapter_1
  in


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort NO
inUseEmpty false
inSymbolsPerBeat 4
inUseReady false
outUseReady true
inReadyLatency 0
outReadyLatency 0
inErrorWidth 0
inErrorDescriptor
inUseValid false
outUseValid true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_0_rx_clk

altera_clock_bridge v15.1
xcvr_0_xcvr_custom_phy_0 rx_clkout0   xcvr_0_tester_0_rx_clk
  in_clk
out_clk   xcvr_0_tester_0_timing_adapter_rx0
  clk
out_clk   xcvr_0_tester_0_data_pattern_checker_0
  pattern_in_clk
out_clk   xcvr_0_tester_0_data_format_adapter_1
  clk
out_clk   xcvr_0_tester_0_freq_counter_0
  sample_clock


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_0_tx_clk

altera_clock_bridge v15.1
xcvr_0_xcvr_custom_phy_0 tx_clkout0   xcvr_0_tester_0_tx_clk
  in_clk
out_clk   xcvr_0_tester_0_timing_adapter_tx0
  clk
out_clk   xcvr_0_tester_0_data_pattern_generator_0
  pattern_out_clk
out_clk   xcvr_0_tester_0_data_format_adapter_0
  clk


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_0_data_format_adapter_0

data_format_adapter v15.1
xcvr_0_tester_0_tx_clk out_clk   xcvr_0_tester_0_data_format_adapter_0
  clk
xcvr_0_tester_0_clk_50 clk_reset  
  reset
xcvr_0_tester_0_data_pattern_generator_0 pattern_out  
  in
out   xcvr_0_tester_0_timing_adapter_tx0
  in


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort AUTO
inUseEmpty false
outUseEmptyPort AUTO
outUseEmpty false
inSymbolsPerBeat 4
outSymbolsPerBeat 4
inReadyLatency 0
inErrorWidth 0
inErrorDescriptor
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_0_data_format_adapter_1

data_format_adapter v15.1
xcvr_0_tester_0_rx_clk out_clk   xcvr_0_tester_0_data_format_adapter_1
  clk
xcvr_0_tester_0_clk_50 clk_reset  
  reset
xcvr_0_tester_0_timing_adapter_rx0 out  
  in
out   xcvr_0_tester_0_data_pattern_checker_0
  pattern_in


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort AUTO
inUseEmpty false
outUseEmptyPort AUTO
outUseEmpty false
inSymbolsPerBeat 4
outSymbolsPerBeat 4
inReadyLatency 0
inErrorWidth 0
inErrorDescriptor
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_0_timer_0

altera_avalon_timer v15.1
xcvr_0_tester_0_clk_50 clk   xcvr_0_tester_0_timer_0
  clk
clk_reset  
  reset
xcvr_0_tester_0_mm_bridge_0 m0  
  s1
xcvr_0_tester_0_master_driver_com_0 avalon_master  
  s1


Parameters

alwaysRun false
counterSize 64
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 50000000
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0.001
loadValue 49999
mult 0.001
ticksPerSec 1000.0
slave_address_width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 64
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0

xcvr_0_tester_0_master_driver_com_0

master_driver_com v1.0
xcvr_0_tester_0_clk_50 clk_reset   xcvr_0_tester_0_master_driver_com_0
  reset
clk  
  clock
xcvr_0_tester_0_mm_bridge_0 m0  
  csr
avalon_master   xcvr_0_tester_0_timer_0
  s1
avalon_master   xcvr_0_tester_0_data_pattern_checker_0
  csr_slave
avalon_master   xcvr_0_tester_0_data_pattern_generator_0
  csr_slave
avalon_master   xcvr_0_tester_0_freq_counter_0
  csr


Parameters

CHECKER_BASE 32
GENERATOR_BASE 0
TIMER_BASE 256
FREQ_BASE 512
DESERIALIZATION_FACTOR 40
NUM_OF_CH 1
ENABLE_PER_INFO 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_0_mm_bridge_0

altera_avalon_mm_bridge v15.1
xcvr_0_tester_0_clk_50 clk   xcvr_0_tester_0_mm_bridge_0
  clk
clk_reset  
  reset
xcvr_0_mm_bridge_0 m0  
  s0
m0   xcvr_0_tester_0_master_driver_com_0
  csr
m0   xcvr_0_tester_0_timer_0
  s1
m0   xcvr_0_tester_0_data_pattern_checker_0
  csr_slave
m0   xcvr_0_tester_0_data_pattern_generator_0
  csr_slave
m0   xcvr_0_tester_0_freq_counter_0
  csr


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 10
SYSINFO_ADDR_WIDTH 10
USE_AUTO_ADDRESS_WIDTH 0
AUTO_ADDRESS_WIDTH 10
HDL_ADDR_WIDTH 10
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 4
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
USE_RESPONSE 0
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_CLK_CLOCK_RATE 50000000
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_0_freq_counter_0

freq_counter v1.0
xcvr_0_tester_0_clk_50 clk_reset   xcvr_0_tester_0_freq_counter_0
  reset
clk  
  clock
xcvr_0_tester_0_mm_bridge_0 m0  
  csr
xcvr_0_tester_0_master_driver_com_0 avalon_master  
  csr
xcvr_0_tester_0_rx_clk out_clk  
  sample_clock


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 20000
DIV 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_1

xcvr_tester v1.0


Parameters

AUTO_GENERATION_ID 1447060235
AUTO_UNIQUE_ID q_sys_xcvr_0_tester_1
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CLK_50_CLOCK_RATE 50000000
AUTO_CLK_50_CLOCK_DOMAIN 6
AUTO_CLK_50_RESET_DOMAIN 6
AUTO_RX_CLK_IN_CLK_CLOCK_RATE 0
AUTO_RX_CLK_IN_CLK_CLOCK_DOMAIN 9
AUTO_RX_CLK_IN_CLK_RESET_DOMAIN 9
AUTO_TX_CLK_IN_CLK_CLOCK_RATE 0
AUTO_TX_CLK_IN_CLK_CLOCK_DOMAIN 13
AUTO_TX_CLK_IN_CLK_RESET_DOMAIN 13
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_1_clk_50

clock_source v15.1
xcvr_0_clk_50 clk   xcvr_0_tester_1_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk_reset   xcvr_0_tester_1_timing_adapter_tx0
  reset
clk_reset   xcvr_0_tester_1_timing_adapter_rx0
  reset
clk   xcvr_0_tester_1_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
clk   xcvr_0_tester_1_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk_reset   xcvr_0_tester_1_data_format_adapter_0
  reset
clk_reset   xcvr_0_tester_1_data_format_adapter_1
  reset
clk   xcvr_0_tester_1_timer_0
  clk
clk_reset  
  reset
clk_reset   xcvr_0_tester_1_master_driver_com_0
  reset
clk  
  clock
clk   xcvr_0_tester_1_mm_bridge_0
  clk
clk_reset  
  reset
clk_reset   xcvr_0_tester_1_freq_counter_0
  reset
clk  
  clock


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 50000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_1_data_pattern_generator_0

altera_avalon_data_pattern_generator v15.1
xcvr_0_tester_1_clk_50 clk   xcvr_0_tester_1_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
xcvr_0_tester_1_tx_clk out_clk  
  pattern_out_clk
xcvr_0_tester_1_mm_bridge_0 m0  
  csr_slave
xcvr_0_tester_1_master_driver_com_0 avalon_master  
  csr_slave
pattern_out   xcvr_0_tester_1_data_format_adapter_0
  in


Parameters

ST_DATA_W 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 50000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_1_data_pattern_checker_0

altera_avalon_data_pattern_checker v15.1
xcvr_0_tester_1_clk_50 clk   xcvr_0_tester_1_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
xcvr_0_tester_1_rx_clk out_clk  
  pattern_in_clk
xcvr_0_tester_1_data_format_adapter_1 out  
  pattern_in
xcvr_0_tester_1_mm_bridge_0 m0  
  csr_slave
xcvr_0_tester_1_master_driver_com_0 avalon_master  
  csr_slave


Parameters

ST_DATA_W 40
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 50000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_1_timing_adapter_tx0

timing_adapter v15.1
xcvr_0_tester_1_clk_50 clk_reset   xcvr_0_tester_1_timing_adapter_tx0
  reset
xcvr_0_tester_1_tx_clk out_clk  
  clk
xcvr_0_tester_1_data_format_adapter_0 out  
  in
out   xcvr_0_xcvr_custom_phy_0
  tx_parallel_data1


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort NO
inUseEmpty false
inSymbolsPerBeat 4
inUseReady true
outUseReady false
inReadyLatency 0
outReadyLatency 0
inErrorWidth 0
inErrorDescriptor
inUseValid true
outUseValid false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_1_timing_adapter_rx0

timing_adapter v15.1
xcvr_0_tester_1_clk_50 clk_reset   xcvr_0_tester_1_timing_adapter_rx0
  reset
xcvr_0_tester_1_rx_clk out_clk  
  clk
xcvr_0_xcvr_custom_phy_0 rx_parallel_data1  
  in
out   xcvr_0_tester_1_data_format_adapter_1
  in


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort NO
inUseEmpty false
inSymbolsPerBeat 4
inUseReady false
outUseReady true
inReadyLatency 0
outReadyLatency 0
inErrorWidth 0
inErrorDescriptor
inUseValid false
outUseValid true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_1_rx_clk

altera_clock_bridge v15.1
xcvr_0_xcvr_custom_phy_0 rx_clkout1   xcvr_0_tester_1_rx_clk
  in_clk
out_clk   xcvr_0_tester_1_timing_adapter_rx0
  clk
out_clk   xcvr_0_tester_1_data_pattern_checker_0
  pattern_in_clk
out_clk   xcvr_0_tester_1_data_format_adapter_1
  clk
out_clk   xcvr_0_tester_1_freq_counter_0
  sample_clock


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_1_tx_clk

altera_clock_bridge v15.1
xcvr_0_xcvr_custom_phy_0 tx_clkout1   xcvr_0_tester_1_tx_clk
  in_clk
out_clk   xcvr_0_tester_1_timing_adapter_tx0
  clk
out_clk   xcvr_0_tester_1_data_pattern_generator_0
  pattern_out_clk
out_clk   xcvr_0_tester_1_data_format_adapter_0
  clk


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_1_data_format_adapter_0

data_format_adapter v15.1
xcvr_0_tester_1_tx_clk out_clk   xcvr_0_tester_1_data_format_adapter_0
  clk
xcvr_0_tester_1_clk_50 clk_reset  
  reset
xcvr_0_tester_1_data_pattern_generator_0 pattern_out  
  in
out   xcvr_0_tester_1_timing_adapter_tx0
  in


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort AUTO
inUseEmpty false
outUseEmptyPort AUTO
outUseEmpty false
inSymbolsPerBeat 4
outSymbolsPerBeat 4
inReadyLatency 0
inErrorWidth 0
inErrorDescriptor
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_1_data_format_adapter_1

data_format_adapter v15.1
xcvr_0_tester_1_rx_clk out_clk   xcvr_0_tester_1_data_format_adapter_1
  clk
xcvr_0_tester_1_clk_50 clk_reset  
  reset
xcvr_0_tester_1_timing_adapter_rx0 out  
  in
out   xcvr_0_tester_1_data_pattern_checker_0
  pattern_in


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort AUTO
inUseEmpty false
outUseEmptyPort AUTO
outUseEmpty false
inSymbolsPerBeat 4
outSymbolsPerBeat 4
inReadyLatency 0
inErrorWidth 0
inErrorDescriptor
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_1_timer_0

altera_avalon_timer v15.1
xcvr_0_tester_1_clk_50 clk   xcvr_0_tester_1_timer_0
  clk
clk_reset  
  reset
xcvr_0_tester_1_mm_bridge_0 m0  
  s1
xcvr_0_tester_1_master_driver_com_0 avalon_master  
  s1


Parameters

alwaysRun false
counterSize 64
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 50000000
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0.001
loadValue 49999
mult 0.001
ticksPerSec 1000.0
slave_address_width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 64
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0

xcvr_0_tester_1_master_driver_com_0

master_driver_com v1.0
xcvr_0_tester_1_clk_50 clk_reset   xcvr_0_tester_1_master_driver_com_0
  reset
clk  
  clock
xcvr_0_tester_1_mm_bridge_0 m0  
  csr
avalon_master   xcvr_0_tester_1_timer_0
  s1
avalon_master   xcvr_0_tester_1_data_pattern_checker_0
  csr_slave
avalon_master   xcvr_0_tester_1_data_pattern_generator_0
  csr_slave
avalon_master   xcvr_0_tester_1_freq_counter_0
  csr


Parameters

CHECKER_BASE 32
GENERATOR_BASE 0
TIMER_BASE 256
FREQ_BASE 512
DESERIALIZATION_FACTOR 40
NUM_OF_CH 1
ENABLE_PER_INFO 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_1_mm_bridge_0

altera_avalon_mm_bridge v15.1
xcvr_0_tester_1_clk_50 clk   xcvr_0_tester_1_mm_bridge_0
  clk
clk_reset  
  reset
xcvr_0_mm_bridge_0 m0  
  s0
m0   xcvr_0_tester_1_master_driver_com_0
  csr
m0   xcvr_0_tester_1_timer_0
  s1
m0   xcvr_0_tester_1_data_pattern_checker_0
  csr_slave
m0   xcvr_0_tester_1_data_pattern_generator_0
  csr_slave
m0   xcvr_0_tester_1_freq_counter_0
  csr


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 10
SYSINFO_ADDR_WIDTH 10
USE_AUTO_ADDRESS_WIDTH 0
AUTO_ADDRESS_WIDTH 10
HDL_ADDR_WIDTH 10
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 4
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
USE_RESPONSE 0
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_CLK_CLOCK_RATE 50000000
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_1_freq_counter_0

freq_counter v1.0
xcvr_0_tester_1_clk_50 clk_reset   xcvr_0_tester_1_freq_counter_0
  reset
clk  
  clock
xcvr_0_tester_1_mm_bridge_0 m0  
  csr
xcvr_0_tester_1_master_driver_com_0 avalon_master  
  csr
xcvr_0_tester_1_rx_clk out_clk  
  sample_clock


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 20000
DIV 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_2

xcvr_tester v1.0


Parameters

AUTO_GENERATION_ID 1447060235
AUTO_UNIQUE_ID q_sys_xcvr_0_tester_2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CLK_50_CLOCK_RATE 50000000
AUTO_CLK_50_CLOCK_DOMAIN 6
AUTO_CLK_50_RESET_DOMAIN 6
AUTO_RX_CLK_IN_CLK_CLOCK_RATE 0
AUTO_RX_CLK_IN_CLK_CLOCK_DOMAIN 10
AUTO_RX_CLK_IN_CLK_RESET_DOMAIN 10
AUTO_TX_CLK_IN_CLK_CLOCK_RATE 0
AUTO_TX_CLK_IN_CLK_CLOCK_DOMAIN 14
AUTO_TX_CLK_IN_CLK_RESET_DOMAIN 14
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_2_clk_50

clock_source v15.1
xcvr_0_clk_50 clk   xcvr_0_tester_2_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk_reset   xcvr_0_tester_2_timing_adapter_tx0
  reset
clk_reset   xcvr_0_tester_2_timing_adapter_rx0
  reset
clk   xcvr_0_tester_2_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
clk   xcvr_0_tester_2_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk_reset   xcvr_0_tester_2_data_format_adapter_0
  reset
clk_reset   xcvr_0_tester_2_data_format_adapter_1
  reset
clk   xcvr_0_tester_2_timer_0
  clk
clk_reset  
  reset
clk_reset   xcvr_0_tester_2_master_driver_com_0
  reset
clk  
  clock
clk   xcvr_0_tester_2_mm_bridge_0
  clk
clk_reset  
  reset
clk_reset   xcvr_0_tester_2_freq_counter_0
  reset
clk  
  clock


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 50000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_2_data_pattern_generator_0

altera_avalon_data_pattern_generator v15.1
xcvr_0_tester_2_clk_50 clk   xcvr_0_tester_2_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
xcvr_0_tester_2_tx_clk out_clk  
  pattern_out_clk
xcvr_0_tester_2_mm_bridge_0 m0  
  csr_slave
xcvr_0_tester_2_master_driver_com_0 avalon_master  
  csr_slave
pattern_out   xcvr_0_tester_2_data_format_adapter_0
  in


Parameters

ST_DATA_W 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 50000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_2_data_pattern_checker_0

altera_avalon_data_pattern_checker v15.1
xcvr_0_tester_2_clk_50 clk   xcvr_0_tester_2_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
xcvr_0_tester_2_rx_clk out_clk  
  pattern_in_clk
xcvr_0_tester_2_data_format_adapter_1 out  
  pattern_in
xcvr_0_tester_2_mm_bridge_0 m0  
  csr_slave
xcvr_0_tester_2_master_driver_com_0 avalon_master  
  csr_slave


Parameters

ST_DATA_W 40
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 50000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_2_timing_adapter_tx0

timing_adapter v15.1
xcvr_0_tester_2_clk_50 clk_reset   xcvr_0_tester_2_timing_adapter_tx0
  reset
xcvr_0_tester_2_tx_clk out_clk  
  clk
xcvr_0_tester_2_data_format_adapter_0 out  
  in
out   xcvr_0_xcvr_custom_phy_0
  tx_parallel_data2


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort NO
inUseEmpty false
inSymbolsPerBeat 4
inUseReady true
outUseReady false
inReadyLatency 0
outReadyLatency 0
inErrorWidth 0
inErrorDescriptor
inUseValid true
outUseValid false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_2_timing_adapter_rx0

timing_adapter v15.1
xcvr_0_tester_2_clk_50 clk_reset   xcvr_0_tester_2_timing_adapter_rx0
  reset
xcvr_0_tester_2_rx_clk out_clk  
  clk
xcvr_0_xcvr_custom_phy_0 rx_parallel_data2  
  in
out   xcvr_0_tester_2_data_format_adapter_1
  in


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort NO
inUseEmpty false
inSymbolsPerBeat 4
inUseReady false
outUseReady true
inReadyLatency 0
outReadyLatency 0
inErrorWidth 0
inErrorDescriptor
inUseValid false
outUseValid true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_2_rx_clk

altera_clock_bridge v15.1
xcvr_0_xcvr_custom_phy_0 rx_clkout2   xcvr_0_tester_2_rx_clk
  in_clk
out_clk   xcvr_0_tester_2_timing_adapter_rx0
  clk
out_clk   xcvr_0_tester_2_data_pattern_checker_0
  pattern_in_clk
out_clk   xcvr_0_tester_2_data_format_adapter_1
  clk
out_clk   xcvr_0_tester_2_freq_counter_0
  sample_clock


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_2_tx_clk

altera_clock_bridge v15.1
xcvr_0_xcvr_custom_phy_0 tx_clkout2   xcvr_0_tester_2_tx_clk
  in_clk
out_clk   xcvr_0_tester_2_timing_adapter_tx0
  clk
out_clk   xcvr_0_tester_2_data_pattern_generator_0
  pattern_out_clk
out_clk   xcvr_0_tester_2_data_format_adapter_0
  clk


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_2_data_format_adapter_0

data_format_adapter v15.1
xcvr_0_tester_2_tx_clk out_clk   xcvr_0_tester_2_data_format_adapter_0
  clk
xcvr_0_tester_2_clk_50 clk_reset  
  reset
xcvr_0_tester_2_data_pattern_generator_0 pattern_out  
  in
out   xcvr_0_tester_2_timing_adapter_tx0
  in


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort AUTO
inUseEmpty false
outUseEmptyPort AUTO
outUseEmpty false
inSymbolsPerBeat 4
outSymbolsPerBeat 4
inReadyLatency 0
inErrorWidth 0
inErrorDescriptor
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_2_data_format_adapter_1

data_format_adapter v15.1
xcvr_0_tester_2_rx_clk out_clk   xcvr_0_tester_2_data_format_adapter_1
  clk
xcvr_0_tester_2_clk_50 clk_reset  
  reset
xcvr_0_tester_2_timing_adapter_rx0 out  
  in
out   xcvr_0_tester_2_data_pattern_checker_0
  pattern_in


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort AUTO
inUseEmpty false
outUseEmptyPort AUTO
outUseEmpty false
inSymbolsPerBeat 4
outSymbolsPerBeat 4
inReadyLatency 0
inErrorWidth 0
inErrorDescriptor
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_2_timer_0

altera_avalon_timer v15.1
xcvr_0_tester_2_clk_50 clk   xcvr_0_tester_2_timer_0
  clk
clk_reset  
  reset
xcvr_0_tester_2_mm_bridge_0 m0  
  s1
xcvr_0_tester_2_master_driver_com_0 avalon_master  
  s1


Parameters

alwaysRun false
counterSize 64
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 50000000
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0.001
loadValue 49999
mult 0.001
ticksPerSec 1000.0
slave_address_width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 64
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0

xcvr_0_tester_2_master_driver_com_0

master_driver_com v1.0
xcvr_0_tester_2_clk_50 clk_reset   xcvr_0_tester_2_master_driver_com_0
  reset
clk  
  clock
xcvr_0_tester_2_mm_bridge_0 m0  
  csr
avalon_master   xcvr_0_tester_2_timer_0
  s1
avalon_master   xcvr_0_tester_2_data_pattern_checker_0
  csr_slave
avalon_master   xcvr_0_tester_2_data_pattern_generator_0
  csr_slave
avalon_master   xcvr_0_tester_2_freq_counter_0
  csr


Parameters

CHECKER_BASE 32
GENERATOR_BASE 0
TIMER_BASE 256
FREQ_BASE 512
DESERIALIZATION_FACTOR 40
NUM_OF_CH 1
ENABLE_PER_INFO 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_2_mm_bridge_0

altera_avalon_mm_bridge v15.1
xcvr_0_tester_2_clk_50 clk   xcvr_0_tester_2_mm_bridge_0
  clk
clk_reset  
  reset
xcvr_0_mm_bridge_0 m0  
  s0
m0   xcvr_0_tester_2_master_driver_com_0
  csr
m0   xcvr_0_tester_2_timer_0
  s1
m0   xcvr_0_tester_2_data_pattern_checker_0
  csr_slave
m0   xcvr_0_tester_2_data_pattern_generator_0
  csr_slave
m0   xcvr_0_tester_2_freq_counter_0
  csr


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 10
SYSINFO_ADDR_WIDTH 10
USE_AUTO_ADDRESS_WIDTH 0
AUTO_ADDRESS_WIDTH 10
HDL_ADDR_WIDTH 10
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 4
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
USE_RESPONSE 0
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_CLK_CLOCK_RATE 50000000
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_2_freq_counter_0

freq_counter v1.0
xcvr_0_tester_2_clk_50 clk_reset   xcvr_0_tester_2_freq_counter_0
  reset
clk  
  clock
xcvr_0_tester_2_mm_bridge_0 m0  
  csr
xcvr_0_tester_2_master_driver_com_0 avalon_master  
  csr
xcvr_0_tester_2_rx_clk out_clk  
  sample_clock


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 20000
DIV 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_3

xcvr_tester v1.0


Parameters

AUTO_GENERATION_ID 1447060235
AUTO_UNIQUE_ID q_sys_xcvr_0_tester_3
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CLK_50_CLOCK_RATE 50000000
AUTO_CLK_50_CLOCK_DOMAIN 6
AUTO_CLK_50_RESET_DOMAIN 6
AUTO_RX_CLK_IN_CLK_CLOCK_RATE 0
AUTO_RX_CLK_IN_CLK_CLOCK_DOMAIN 11
AUTO_RX_CLK_IN_CLK_RESET_DOMAIN 11
AUTO_TX_CLK_IN_CLK_CLOCK_RATE 0
AUTO_TX_CLK_IN_CLK_CLOCK_DOMAIN 15
AUTO_TX_CLK_IN_CLK_RESET_DOMAIN 15
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_3_clk_50

clock_source v15.1
xcvr_0_clk_50 clk   xcvr_0_tester_3_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk_reset   xcvr_0_tester_3_timing_adapter_tx0
  reset
clk_reset   xcvr_0_tester_3_timing_adapter_rx0
  reset
clk   xcvr_0_tester_3_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
clk   xcvr_0_tester_3_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk_reset   xcvr_0_tester_3_data_format_adapter_0
  reset
clk_reset   xcvr_0_tester_3_data_format_adapter_1
  reset
clk   xcvr_0_tester_3_timer_0
  clk
clk_reset  
  reset
clk_reset   xcvr_0_tester_3_master_driver_com_0
  reset
clk  
  clock
clk   xcvr_0_tester_3_mm_bridge_0
  clk
clk_reset  
  reset
clk_reset   xcvr_0_tester_3_freq_counter_0
  reset
clk  
  clock


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 50000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_3_data_pattern_generator_0

altera_avalon_data_pattern_generator v15.1
xcvr_0_tester_3_clk_50 clk   xcvr_0_tester_3_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
xcvr_0_tester_3_tx_clk out_clk  
  pattern_out_clk
xcvr_0_tester_3_mm_bridge_0 m0  
  csr_slave
xcvr_0_tester_3_master_driver_com_0 avalon_master  
  csr_slave
pattern_out   xcvr_0_tester_3_data_format_adapter_0
  in


Parameters

ST_DATA_W 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 50000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_3_data_pattern_checker_0

altera_avalon_data_pattern_checker v15.1
xcvr_0_tester_3_clk_50 clk   xcvr_0_tester_3_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
xcvr_0_tester_3_rx_clk out_clk  
  pattern_in_clk
xcvr_0_tester_3_data_format_adapter_1 out  
  pattern_in
xcvr_0_tester_3_mm_bridge_0 m0  
  csr_slave
xcvr_0_tester_3_master_driver_com_0 avalon_master  
  csr_slave


Parameters

ST_DATA_W 40
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 50000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_3_timing_adapter_tx0

timing_adapter v15.1
xcvr_0_tester_3_clk_50 clk_reset   xcvr_0_tester_3_timing_adapter_tx0
  reset
xcvr_0_tester_3_tx_clk out_clk  
  clk
xcvr_0_tester_3_data_format_adapter_0 out  
  in
out   xcvr_0_xcvr_custom_phy_0
  tx_parallel_data3


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort NO
inUseEmpty false
inSymbolsPerBeat 4
inUseReady true
outUseReady false
inReadyLatency 0
outReadyLatency 0
inErrorWidth 0
inErrorDescriptor
inUseValid true
outUseValid false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_3_timing_adapter_rx0

timing_adapter v15.1
xcvr_0_tester_3_clk_50 clk_reset   xcvr_0_tester_3_timing_adapter_rx0
  reset
xcvr_0_tester_3_rx_clk out_clk  
  clk
xcvr_0_xcvr_custom_phy_0 rx_parallel_data3  
  in
out   xcvr_0_tester_3_data_format_adapter_1
  in


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort NO
inUseEmpty false
inSymbolsPerBeat 4
inUseReady false
outUseReady true
inReadyLatency 0
outReadyLatency 0
inErrorWidth 0
inErrorDescriptor
inUseValid false
outUseValid true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_3_rx_clk

altera_clock_bridge v15.1
xcvr_0_xcvr_custom_phy_0 rx_clkout3   xcvr_0_tester_3_rx_clk
  in_clk
out_clk   xcvr_0_tester_3_timing_adapter_rx0
  clk
out_clk   xcvr_0_tester_3_data_pattern_checker_0
  pattern_in_clk
out_clk   xcvr_0_tester_3_data_format_adapter_1
  clk
out_clk   xcvr_0_tester_3_freq_counter_0
  sample_clock


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_3_tx_clk

altera_clock_bridge v15.1
xcvr_0_xcvr_custom_phy_0 tx_clkout3   xcvr_0_tester_3_tx_clk
  in_clk
out_clk   xcvr_0_tester_3_timing_adapter_tx0
  clk
out_clk   xcvr_0_tester_3_data_pattern_generator_0
  pattern_out_clk
out_clk   xcvr_0_tester_3_data_format_adapter_0
  clk


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_3_data_format_adapter_0

data_format_adapter v15.1
xcvr_0_tester_3_tx_clk out_clk   xcvr_0_tester_3_data_format_adapter_0
  clk
xcvr_0_tester_3_clk_50 clk_reset  
  reset
xcvr_0_tester_3_data_pattern_generator_0 pattern_out  
  in
out   xcvr_0_tester_3_timing_adapter_tx0
  in


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort AUTO
inUseEmpty false
outUseEmptyPort AUTO
outUseEmpty false
inSymbolsPerBeat 4
outSymbolsPerBeat 4
inReadyLatency 0
inErrorWidth 0
inErrorDescriptor
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_3_data_format_adapter_1

data_format_adapter v15.1
xcvr_0_tester_3_rx_clk out_clk   xcvr_0_tester_3_data_format_adapter_1
  clk
xcvr_0_tester_3_clk_50 clk_reset  
  reset
xcvr_0_tester_3_timing_adapter_rx0 out  
  in
out   xcvr_0_tester_3_data_pattern_checker_0
  pattern_in


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 10
inUsePackets false
inUseEmptyPort AUTO
inUseEmpty false
outUseEmptyPort AUTO
outUseEmpty false
inSymbolsPerBeat 4
outSymbolsPerBeat 4
inReadyLatency 0
inErrorWidth 0
inErrorDescriptor
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_3_timer_0

altera_avalon_timer v15.1
xcvr_0_tester_3_clk_50 clk   xcvr_0_tester_3_timer_0
  clk
clk_reset  
  reset
xcvr_0_tester_3_mm_bridge_0 m0  
  s1
xcvr_0_tester_3_master_driver_com_0 avalon_master  
  s1


Parameters

alwaysRun false
counterSize 64
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 50000000
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0.001
loadValue 49999
mult 0.001
ticksPerSec 1000.0
slave_address_width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 64
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0

xcvr_0_tester_3_master_driver_com_0

master_driver_com v1.0
xcvr_0_tester_3_clk_50 clk_reset   xcvr_0_tester_3_master_driver_com_0
  reset
clk  
  clock
xcvr_0_tester_3_mm_bridge_0 m0  
  csr
avalon_master   xcvr_0_tester_3_timer_0
  s1
avalon_master   xcvr_0_tester_3_data_pattern_checker_0
  csr_slave
avalon_master   xcvr_0_tester_3_data_pattern_generator_0
  csr_slave
avalon_master   xcvr_0_tester_3_freq_counter_0
  csr


Parameters

CHECKER_BASE 32
GENERATOR_BASE 0
TIMER_BASE 256
FREQ_BASE 512
DESERIALIZATION_FACTOR 40
NUM_OF_CH 1
ENABLE_PER_INFO 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_3_mm_bridge_0

altera_avalon_mm_bridge v15.1
xcvr_0_tester_3_clk_50 clk   xcvr_0_tester_3_mm_bridge_0
  clk
clk_reset  
  reset
xcvr_0_mm_bridge_0 m0  
  s0
m0   xcvr_0_tester_3_master_driver_com_0
  csr
m0   xcvr_0_tester_3_timer_0
  s1
m0   xcvr_0_tester_3_data_pattern_checker_0
  csr_slave
m0   xcvr_0_tester_3_data_pattern_generator_0
  csr_slave
m0   xcvr_0_tester_3_freq_counter_0
  csr


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 10
SYSINFO_ADDR_WIDTH 10
USE_AUTO_ADDRESS_WIDTH 0
AUTO_ADDRESS_WIDTH 10
HDL_ADDR_WIDTH 10
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 4
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
USE_RESPONSE 0
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_CLK_CLOCK_RATE 50000000
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_tester_3_freq_counter_0

freq_counter v1.0
xcvr_0_tester_3_clk_50 clk_reset   xcvr_0_tester_3_freq_counter_0
  reset
clk  
  clock
xcvr_0_tester_3_mm_bridge_0 m0  
  csr
xcvr_0_tester_3_master_driver_com_0 avalon_master  
  csr
xcvr_0_tester_3_rx_clk out_clk  
  sample_clock


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 20000
DIV 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_clk_50

clock_source v15.1
clk_50 clk   xcvr_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   xcvr_0_tester_3_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   xcvr_0_tester_2_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   xcvr_0_tester_1_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   xcvr_0_tester_0_clk_50
  clk_in
clk_reset  
  clk_in_reset
clk   xcvr_0_mm_bridge_0
  clk
clk_reset  
  reset


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 50000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

xcvr_0_mm_bridge_0

altera_avalon_mm_bridge v15.1
xcvr_0_clk_50 clk   xcvr_0_mm_bridge_0
  clk
clk_reset  
  reset
master_0 master  
  s0
m0   xcvr_0_tester_3_mm_bridge_0
  s0
m0   xcvr_0_tester_2_mm_bridge_0
  s0
m0   xcvr_0_tester_1_mm_bridge_0
  s0
m0   xcvr_0_tester_0_mm_bridge_0
  s0
m0   xcvr_0_alt_xcvr_reconfig_0
  reconfig_mgmt
m0   xcvr_0_xcvr_custom_phy_0
  phy_mgmt


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 15
SYSINFO_ADDR_WIDTH 15
USE_AUTO_ADDRESS_WIDTH 0
AUTO_ADDRESS_WIDTH 15
HDL_ADDR_WIDTH 15
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 4
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
USE_RESPONSE 0
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_CLK_CLOCK_RATE 50000000
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

clk_50

clock_source v15.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

product_info_0

product_info v1.0
clk_50 clk_reset   product_info_0
  reset
clk  
  clock
master_0 master  
  avalon_slave_0


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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