q_sys |
|
2023.09.15.14:15:35 | Datasheet |
clk_100 | q_sys |
clk_50 | |
cmos_0_clkin | |
xcvr_0_clk_100 | |
xcvr_0_clk_50 | |
xcvr_0_tester_0_clk_50 | |
xcvr_0_tester_1_clk_50 | |
xcvr_0_tester_2_clk_50 | |
xcvr_0_tester_3_clk_50 | |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_50 | clk | cmos_0_clkin | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | cmos_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | cmos_0_timer_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | cmos_0_master_driver_com_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | cmos_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | cmos_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | cmos_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | cmos_0_tx_clk | ||
in_clk | |||
clk | cmos_0_rx_clk | ||
in_clk |
Parameters
|
Software Assignments(none) |
cmos_0_master_driver_com_0 | avalon_master | cmos_0_data_pattern_checker_0 |
csr_slave | ||
cmos_0_mm_bridge_0 | m0 | |
csr_slave | ||
cmos_0_clkin | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
cmos_0_rx_clk | out_clk | |
pattern_in_clk |
Parameters
|
Software Assignments(none) |
cmos_0_master_driver_com_0 | avalon_master | cmos_0_data_pattern_generator_0 |
csr_slave | ||
cmos_0_mm_bridge_0 | m0 | |
csr_slave | ||
cmos_0_clkin | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
cmos_0_tx_clk | out_clk | |
pattern_out_clk |
Parameters
|
Software Assignments(none) |
cmos_0_master_driver_com_0 | avalon_master | cmos_0_freq_counter_0 |
csr | ||
cmos_0_mm_bridge_0 | m0 | |
csr | ||
cmos_0_clkin | clk | |
clock | ||
clk_reset | ||
reset | ||
cmos_0_rx_clk | out_clk | |
sample_clock |
Parameters
|
Software Assignments(none) |
cmos_0_mm_bridge_0 | m0 | cmos_0_master_driver_com_0 | |
csr | |||
cmos_0_clkin | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | cmos_0_freq_counter_0 | ||
csr | |||
avalon_master | cmos_0_data_pattern_checker_0 | ||
csr_slave | |||
avalon_master | cmos_0_data_pattern_generator_0 | ||
csr_slave | |||
avalon_master | cmos_0_timer_0 | ||
s1 |
Parameters
|
Software Assignments(none) |
cmos_0_clkin | clk | cmos_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | cmos_0_master_driver_com_0 | ||
csr | |||
m0 | cmos_0_freq_counter_0 | ||
csr | |||
m0 | cmos_0_data_pattern_checker_0 | ||
csr_slave | |||
m0 | cmos_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | cmos_0_timer_0 | ||
s1 |
Parameters
|
Software Assignments(none) |
cmos_0_clkin | clk | cmos_0_rx_clk | |
in_clk | |||
out_clk | cmos_0_data_pattern_checker_0 | ||
pattern_in_clk | |||
out_clk | cmos_0_freq_counter_0 | ||
sample_clock |
Parameters
|
Software Assignments(none) |
cmos_0_master_driver_com_0 | avalon_master | cmos_0_timer_0 |
s1 | ||
cmos_0_mm_bridge_0 | m0 | |
s1 | ||
cmos_0_clkin | clk | |
clk | ||
clk_reset | ||
reset |
Parameters
|
Software Assignments
|
cmos_0_clkin | clk | cmos_0_tx_clk | |
in_clk | |||
out_clk | cmos_0_data_pattern_generator_0 | ||
pattern_out_clk |
Parameters
|
Software Assignments(none) |
clk_50 | clk | master_0 | |
clk | |||
clk_reset | |||
clk_reset | |||
master | product_info_0 | ||
avalon_slave_0 | |||
master | cmos_0_mm_bridge_0 | ||
s0 | |||
master | xcvr_0_mm_bridge_0 | ||
s0 |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
xcvr_0_mm_bridge_0 | m0 | xcvr_0_alt_xcvr_reconfig_0 | |
reconfig_mgmt | |||
xcvr_0_clk_100 | clk | ||
mgmt_clk_clk | |||
clk_reset | |||
mgmt_rst_reset | |||
xcvr_0_xcvr_custom_phy_0 | reconfig_from_xcvr | ||
ch0_1_from_xcvr | |||
xcvr_0_xcvr_custom_phy_2 | reconfig_from_xcvr | ||
ch4_5_from_xcvr | |||
xcvr_0_xcvr_custom_phy_3 | reconfig_from_xcvr | ||
ch6_7_from_xcvr | |||
ch0_1_to_xcvr | xcvr_0_xcvr_custom_phy_0 | ||
reconfig_to_xcvr | |||
ch2_3_from_xcvr | xcvr_0_xcvr_custom_phy_1 | ||
reconfig_from_xcvr | |||
ch2_3_to_xcvr | |||
reconfig_to_xcvr | |||
ch4_5_to_xcvr | xcvr_0_xcvr_custom_phy_2 | ||
reconfig_to_xcvr | |||
ch6_7_to_xcvr | xcvr_0_xcvr_custom_phy_3 | ||
reconfig_to_xcvr |
Parameters
|
Software Assignments(none) |
clk_100 | clk | xcvr_0_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_alt_xcvr_reconfig_0 | ||
mgmt_clk_clk | |||
clk_reset | |||
mgmt_rst_reset | |||
clk | xcvr_0_xcvr_custom_phy_0 | ||
phy_mgmt_clk | |||
clk_reset | |||
phy_mgmt_clk_reset | |||
clk | xcvr_0_xcvr_custom_phy_1 | ||
phy_mgmt_clk | |||
clk_reset | |||
phy_mgmt_clk_reset | |||
clk | xcvr_0_xcvr_custom_phy_2 | ||
phy_mgmt_clk | |||
clk_reset | |||
phy_mgmt_clk_reset | |||
clk | xcvr_0_xcvr_custom_phy_3 | ||
phy_mgmt_clk | |||
clk_reset | |||
phy_mgmt_clk_reset |
Parameters
|
Software Assignments(none) |
clk_50 | clk | xcvr_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_3_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_tester_2_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_tester_1_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_tester_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset |
Parameters
|
Software Assignments(none) |
xcvr_0_clk_50 | clk | xcvr_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | xcvr_0_tester_3_mm_bridge_0 | ||
s0 | |||
m0 | xcvr_0_tester_2_mm_bridge_0 | ||
s0 | |||
m0 | xcvr_0_tester_1_mm_bridge_0 | ||
s0 | |||
m0 | xcvr_0_tester_0_mm_bridge_0 | ||
s0 | |||
m0 | xcvr_0_xcvr_custom_phy_0 | ||
phy_mgmt | |||
m0 | xcvr_0_xcvr_custom_phy_1 | ||
phy_mgmt | |||
m0 | xcvr_0_xcvr_custom_phy_2 | ||
phy_mgmt | |||
m0 | xcvr_0_xcvr_custom_phy_3 | ||
phy_mgmt | |||
m0 | xcvr_0_alt_xcvr_reconfig_0 | ||
reconfig_mgmt |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
xcvr_0_clk_50 | clk | xcvr_0_tester_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_tester_0_timer_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_0_master_driver_com_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_0_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_0_timing_adapter_tx0 | ||
reset | |||
clk_reset | xcvr_0_tester_0_timing_adapter_rx0 | ||
reset | |||
clk_reset | xcvr_0_tester_0_data_format_adapter_0 | ||
reset | |||
clk_reset | xcvr_0_tester_0_data_format_adapter_1 | ||
reset |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_data_pattern_generator_0 | pattern_out | xcvr_0_tester_0_data_format_adapter_0 | |
in | |||
xcvr_0_tester_0_tx_clk | out_clk | ||
clk | |||
xcvr_0_tester_0_clk_50 | clk_reset | ||
reset | |||
out | xcvr_0_tester_0_timing_adapter_tx0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_timing_adapter_rx0 | out | xcvr_0_tester_0_data_format_adapter_1 | |
in | |||
xcvr_0_tester_0_rx_clk | out_clk | ||
clk | |||
xcvr_0_tester_0_clk_50 | clk_reset | ||
reset | |||
out | xcvr_0_tester_0_data_pattern_checker_0 | ||
pattern_in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_master_driver_com_0 | avalon_master | xcvr_0_tester_0_data_pattern_checker_0 |
csr_slave | ||
xcvr_0_tester_0_mm_bridge_0 | m0 | |
csr_slave | ||
xcvr_0_tester_0_data_format_adapter_1 | out | |
pattern_in | ||
xcvr_0_tester_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
xcvr_0_tester_0_rx_clk | out_clk | |
pattern_in_clk |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_master_driver_com_0 | avalon_master | xcvr_0_tester_0_data_pattern_generator_0 | |
csr_slave | |||
xcvr_0_tester_0_mm_bridge_0 | m0 | ||
csr_slave | |||
xcvr_0_tester_0_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
xcvr_0_tester_0_tx_clk | out_clk | ||
pattern_out_clk | |||
pattern_out | xcvr_0_tester_0_data_format_adapter_0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_master_driver_com_0 | avalon_master | xcvr_0_tester_0_freq_counter_0 |
csr | ||
xcvr_0_tester_0_mm_bridge_0 | m0 | |
csr | ||
xcvr_0_tester_0_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
xcvr_0_tester_0_rx_clk | out_clk | |
sample_clock |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_mm_bridge_0 | m0 | xcvr_0_tester_0_master_driver_com_0 | |
csr | |||
xcvr_0_tester_0_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | xcvr_0_tester_0_freq_counter_0 | ||
csr | |||
avalon_master | xcvr_0_tester_0_data_pattern_checker_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_0_data_pattern_generator_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_0_timer_0 | ||
s1 |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_clk_50 | clk | xcvr_0_tester_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
xcvr_0_mm_bridge_0 | m0 | ||
s0 | |||
m0 | xcvr_0_tester_0_master_driver_com_0 | ||
csr | |||
m0 | xcvr_0_tester_0_freq_counter_0 | ||
csr | |||
m0 | xcvr_0_tester_0_data_pattern_checker_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_0_timer_0 | ||
s1 |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_0 | rx_clkout0 | xcvr_0_tester_0_rx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_0_timing_adapter_rx0 | ||
clk | |||
out_clk | xcvr_0_tester_0_data_format_adapter_1 | ||
clk | |||
out_clk | xcvr_0_tester_0_data_pattern_checker_0 | ||
pattern_in_clk | |||
out_clk | xcvr_0_tester_0_freq_counter_0 | ||
sample_clock |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_master_driver_com_0 | avalon_master | xcvr_0_tester_0_timer_0 |
s1 | ||
xcvr_0_tester_0_mm_bridge_0 | m0 | |
s1 | ||
xcvr_0_tester_0_clk_50 | clk | |
clk | ||
clk_reset | ||
reset |
Parameters
|
Software Assignments
|
xcvr_0_tester_0_rx_clk | out_clk | xcvr_0_tester_0_timing_adapter_rx0 | |
clk | |||
xcvr_0_tester_0_clk_50 | clk_reset | ||
reset | |||
xcvr_0_xcvr_custom_phy_0 | rx_parallel_data0 | ||
in | |||
out | xcvr_0_tester_0_data_format_adapter_1 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_data_format_adapter_0 | out | xcvr_0_tester_0_timing_adapter_tx0 | |
in | |||
xcvr_0_tester_0_tx_clk | out_clk | ||
clk | |||
xcvr_0_tester_0_clk_50 | clk_reset | ||
reset | |||
out | xcvr_0_xcvr_custom_phy_0 | ||
tx_parallel_data0 |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_0 | tx_clkout0 | xcvr_0_tester_0_tx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_0_timing_adapter_tx0 | ||
clk | |||
out_clk | xcvr_0_tester_0_data_format_adapter_0 | ||
clk | |||
out_clk | xcvr_0_tester_0_data_pattern_generator_0 | ||
pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
xcvr_0_clk_50 | clk | xcvr_0_tester_1_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_tester_1_timer_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_1_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_1_master_driver_com_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_1_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_1_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_1_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_1_timing_adapter_tx0 | ||
reset | |||
clk_reset | xcvr_0_tester_1_timing_adapter_rx0 | ||
reset | |||
clk_reset | xcvr_0_tester_1_data_format_adapter_0 | ||
reset | |||
clk_reset | xcvr_0_tester_1_data_format_adapter_1 | ||
reset |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_data_pattern_generator_0 | pattern_out | xcvr_0_tester_1_data_format_adapter_0 | |
in | |||
xcvr_0_tester_1_tx_clk | out_clk | ||
clk | |||
xcvr_0_tester_1_clk_50 | clk_reset | ||
reset | |||
out | xcvr_0_tester_1_timing_adapter_tx0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_timing_adapter_rx0 | out | xcvr_0_tester_1_data_format_adapter_1 | |
in | |||
xcvr_0_tester_1_rx_clk | out_clk | ||
clk | |||
xcvr_0_tester_1_clk_50 | clk_reset | ||
reset | |||
out | xcvr_0_tester_1_data_pattern_checker_0 | ||
pattern_in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_master_driver_com_0 | avalon_master | xcvr_0_tester_1_data_pattern_checker_0 |
csr_slave | ||
xcvr_0_tester_1_mm_bridge_0 | m0 | |
csr_slave | ||
xcvr_0_tester_1_data_format_adapter_1 | out | |
pattern_in | ||
xcvr_0_tester_1_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
xcvr_0_tester_1_rx_clk | out_clk | |
pattern_in_clk |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_master_driver_com_0 | avalon_master | xcvr_0_tester_1_data_pattern_generator_0 | |
csr_slave | |||
xcvr_0_tester_1_mm_bridge_0 | m0 | ||
csr_slave | |||
xcvr_0_tester_1_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
xcvr_0_tester_1_tx_clk | out_clk | ||
pattern_out_clk | |||
pattern_out | xcvr_0_tester_1_data_format_adapter_0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_master_driver_com_0 | avalon_master | xcvr_0_tester_1_freq_counter_0 |
csr | ||
xcvr_0_tester_1_mm_bridge_0 | m0 | |
csr | ||
xcvr_0_tester_1_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
xcvr_0_tester_1_rx_clk | out_clk | |
sample_clock |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_mm_bridge_0 | m0 | xcvr_0_tester_1_master_driver_com_0 | |
csr | |||
xcvr_0_tester_1_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | xcvr_0_tester_1_freq_counter_0 | ||
csr | |||
avalon_master | xcvr_0_tester_1_data_pattern_checker_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_1_data_pattern_generator_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_1_timer_0 | ||
s1 |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_clk_50 | clk | xcvr_0_tester_1_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
xcvr_0_mm_bridge_0 | m0 | ||
s0 | |||
m0 | xcvr_0_tester_1_master_driver_com_0 | ||
csr | |||
m0 | xcvr_0_tester_1_freq_counter_0 | ||
csr | |||
m0 | xcvr_0_tester_1_data_pattern_checker_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_1_data_pattern_generator_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_1_timer_0 | ||
s1 |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_1 | rx_clkout0 | xcvr_0_tester_1_rx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_1_timing_adapter_rx0 | ||
clk | |||
out_clk | xcvr_0_tester_1_data_format_adapter_1 | ||
clk | |||
out_clk | xcvr_0_tester_1_data_pattern_checker_0 | ||
pattern_in_clk | |||
out_clk | xcvr_0_tester_1_freq_counter_0 | ||
sample_clock |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_master_driver_com_0 | avalon_master | xcvr_0_tester_1_timer_0 |
s1 | ||
xcvr_0_tester_1_mm_bridge_0 | m0 | |
s1 | ||
xcvr_0_tester_1_clk_50 | clk | |
clk | ||
clk_reset | ||
reset |
Parameters
|
Software Assignments
|
xcvr_0_tester_1_rx_clk | out_clk | xcvr_0_tester_1_timing_adapter_rx0 | |
clk | |||
xcvr_0_tester_1_clk_50 | clk_reset | ||
reset | |||
xcvr_0_xcvr_custom_phy_1 | rx_parallel_data0 | ||
in | |||
out | xcvr_0_tester_1_data_format_adapter_1 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_data_format_adapter_0 | out | xcvr_0_tester_1_timing_adapter_tx0 | |
in | |||
xcvr_0_tester_1_tx_clk | out_clk | ||
clk | |||
xcvr_0_tester_1_clk_50 | clk_reset | ||
reset | |||
out | xcvr_0_xcvr_custom_phy_1 | ||
tx_parallel_data0 |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_1 | tx_clkout0 | xcvr_0_tester_1_tx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_1_timing_adapter_tx0 | ||
clk | |||
out_clk | xcvr_0_tester_1_data_format_adapter_0 | ||
clk | |||
out_clk | xcvr_0_tester_1_data_pattern_generator_0 | ||
pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
xcvr_0_clk_50 | clk | xcvr_0_tester_2_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_tester_2_timer_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_2_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_2_master_driver_com_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_2_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_2_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_2_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_2_timing_adapter_tx0 | ||
reset | |||
clk_reset | xcvr_0_tester_2_timing_adapter_rx0 | ||
reset | |||
clk_reset | xcvr_0_tester_2_data_format_adapter_0 | ||
reset | |||
clk_reset | xcvr_0_tester_2_data_format_adapter_1 | ||
reset |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_data_pattern_generator_0 | pattern_out | xcvr_0_tester_2_data_format_adapter_0 | |
in | |||
xcvr_0_tester_2_tx_clk | out_clk | ||
clk | |||
xcvr_0_tester_2_clk_50 | clk_reset | ||
reset | |||
out | xcvr_0_tester_2_timing_adapter_tx0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_timing_adapter_rx0 | out | xcvr_0_tester_2_data_format_adapter_1 | |
in | |||
xcvr_0_tester_2_rx_clk | out_clk | ||
clk | |||
xcvr_0_tester_2_clk_50 | clk_reset | ||
reset | |||
out | xcvr_0_tester_2_data_pattern_checker_0 | ||
pattern_in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_master_driver_com_0 | avalon_master | xcvr_0_tester_2_data_pattern_checker_0 |
csr_slave | ||
xcvr_0_tester_2_mm_bridge_0 | m0 | |
csr_slave | ||
xcvr_0_tester_2_data_format_adapter_1 | out | |
pattern_in | ||
xcvr_0_tester_2_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
xcvr_0_tester_2_rx_clk | out_clk | |
pattern_in_clk |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_master_driver_com_0 | avalon_master | xcvr_0_tester_2_data_pattern_generator_0 | |
csr_slave | |||
xcvr_0_tester_2_mm_bridge_0 | m0 | ||
csr_slave | |||
xcvr_0_tester_2_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
xcvr_0_tester_2_tx_clk | out_clk | ||
pattern_out_clk | |||
pattern_out | xcvr_0_tester_2_data_format_adapter_0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_master_driver_com_0 | avalon_master | xcvr_0_tester_2_freq_counter_0 |
csr | ||
xcvr_0_tester_2_mm_bridge_0 | m0 | |
csr | ||
xcvr_0_tester_2_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
xcvr_0_tester_2_rx_clk | out_clk | |
sample_clock |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_mm_bridge_0 | m0 | xcvr_0_tester_2_master_driver_com_0 | |
csr | |||
xcvr_0_tester_2_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | xcvr_0_tester_2_freq_counter_0 | ||
csr | |||
avalon_master | xcvr_0_tester_2_data_pattern_checker_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_2_data_pattern_generator_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_2_timer_0 | ||
s1 |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_clk_50 | clk | xcvr_0_tester_2_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
xcvr_0_mm_bridge_0 | m0 | ||
s0 | |||
m0 | xcvr_0_tester_2_master_driver_com_0 | ||
csr | |||
m0 | xcvr_0_tester_2_freq_counter_0 | ||
csr | |||
m0 | xcvr_0_tester_2_data_pattern_checker_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_2_data_pattern_generator_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_2_timer_0 | ||
s1 |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_2 | rx_clkout0 | xcvr_0_tester_2_rx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_2_timing_adapter_rx0 | ||
clk | |||
out_clk | xcvr_0_tester_2_data_format_adapter_1 | ||
clk | |||
out_clk | xcvr_0_tester_2_data_pattern_checker_0 | ||
pattern_in_clk | |||
out_clk | xcvr_0_tester_2_freq_counter_0 | ||
sample_clock |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_master_driver_com_0 | avalon_master | xcvr_0_tester_2_timer_0 |
s1 | ||
xcvr_0_tester_2_mm_bridge_0 | m0 | |
s1 | ||
xcvr_0_tester_2_clk_50 | clk | |
clk | ||
clk_reset | ||
reset |
Parameters
|
Software Assignments
|
xcvr_0_tester_2_rx_clk | out_clk | xcvr_0_tester_2_timing_adapter_rx0 | |
clk | |||
xcvr_0_tester_2_clk_50 | clk_reset | ||
reset | |||
xcvr_0_xcvr_custom_phy_2 | rx_parallel_data0 | ||
in | |||
out | xcvr_0_tester_2_data_format_adapter_1 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_data_format_adapter_0 | out | xcvr_0_tester_2_timing_adapter_tx0 | |
in | |||
xcvr_0_tester_2_tx_clk | out_clk | ||
clk | |||
xcvr_0_tester_2_clk_50 | clk_reset | ||
reset | |||
out | xcvr_0_xcvr_custom_phy_2 | ||
tx_parallel_data0 |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_2 | tx_clkout0 | xcvr_0_tester_2_tx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_2_timing_adapter_tx0 | ||
clk | |||
out_clk | xcvr_0_tester_2_data_format_adapter_0 | ||
clk | |||
out_clk | xcvr_0_tester_2_data_pattern_generator_0 | ||
pattern_out_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
xcvr_0_clk_50 | clk | xcvr_0_tester_3_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_tester_3_timer_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_3_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_3_master_driver_com_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_3_freq_counter_0 | ||
clock | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_3_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_3_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_3_timing_adapter_tx0 | ||
reset | |||
clk_reset | xcvr_0_tester_3_timing_adapter_rx0 | ||
reset | |||
clk_reset | xcvr_0_tester_3_data_format_adapter_0 | ||
reset | |||
clk_reset | xcvr_0_tester_3_data_format_adapter_1 | ||
reset |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_data_pattern_generator_0 | pattern_out | xcvr_0_tester_3_data_format_adapter_0 | |
in | |||
xcvr_0_tester_3_tx_clk | out_clk | ||
clk | |||
xcvr_0_tester_3_clk_50 | clk_reset | ||
reset | |||
out | xcvr_0_tester_3_timing_adapter_tx0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_timing_adapter_rx0 | out | xcvr_0_tester_3_data_format_adapter_1 | |
in | |||
xcvr_0_tester_3_rx_clk | out_clk | ||
clk | |||
xcvr_0_tester_3_clk_50 | clk_reset | ||
reset | |||
out | xcvr_0_tester_3_data_pattern_checker_0 | ||
pattern_in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_master_driver_com_0 | avalon_master | xcvr_0_tester_3_data_pattern_checker_0 |
csr_slave | ||
xcvr_0_tester_3_mm_bridge_0 | m0 | |
csr_slave | ||
xcvr_0_tester_3_data_format_adapter_1 | out | |
pattern_in | ||
xcvr_0_tester_3_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
xcvr_0_tester_3_rx_clk | out_clk | |
pattern_in_clk |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_master_driver_com_0 | avalon_master | xcvr_0_tester_3_data_pattern_generator_0 | |
csr_slave | |||
xcvr_0_tester_3_mm_bridge_0 | m0 | ||
csr_slave | |||
xcvr_0_tester_3_clk_50 | clk | ||
csr_clk | |||
clk_reset | |||
reset | |||
xcvr_0_tester_3_tx_clk | out_clk | ||
pattern_out_clk | |||
pattern_out | xcvr_0_tester_3_data_format_adapter_0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_master_driver_com_0 | avalon_master | xcvr_0_tester_3_freq_counter_0 |
csr | ||
xcvr_0_tester_3_mm_bridge_0 | m0 | |
csr | ||
xcvr_0_tester_3_clk_50 | clk | |
clock | ||
clk_reset | ||
reset | ||
xcvr_0_tester_3_rx_clk | out_clk | |
sample_clock |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_mm_bridge_0 | m0 | xcvr_0_tester_3_master_driver_com_0 | |
csr | |||
xcvr_0_tester_3_clk_50 | clk | ||
clock | |||
clk_reset | |||
reset | |||
avalon_master | xcvr_0_tester_3_freq_counter_0 | ||
csr | |||
avalon_master | xcvr_0_tester_3_data_pattern_checker_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_3_data_pattern_generator_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_3_timer_0 | ||
s1 |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_clk_50 | clk | xcvr_0_tester_3_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
xcvr_0_mm_bridge_0 | m0 | ||
s0 | |||
m0 | xcvr_0_tester_3_master_driver_com_0 | ||
csr | |||
m0 | xcvr_0_tester_3_freq_counter_0 | ||
csr | |||
m0 | xcvr_0_tester_3_data_pattern_checker_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_3_data_pattern_generator_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_3_timer_0 | ||
s1 |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_3 | rx_clkout0 | xcvr_0_tester_3_rx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_3_timing_adapter_rx0 | ||
clk | |||
out_clk | xcvr_0_tester_3_data_format_adapter_1 | ||
clk | |||
out_clk | xcvr_0_tester_3_data_pattern_checker_0 | ||
pattern_in_clk | |||
out_clk | xcvr_0_tester_3_freq_counter_0 | ||
sample_clock |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_master_driver_com_0 | avalon_master | xcvr_0_tester_3_timer_0 |
s1 | ||
xcvr_0_tester_3_mm_bridge_0 | m0 | |
s1 | ||
xcvr_0_tester_3_clk_50 | clk | |
clk | ||
clk_reset | ||
reset |
Parameters
|
Software Assignments
|
xcvr_0_tester_3_rx_clk | out_clk | xcvr_0_tester_3_timing_adapter_rx0 | |
clk | |||
xcvr_0_tester_3_clk_50 | clk_reset | ||
reset | |||
xcvr_0_xcvr_custom_phy_3 | rx_parallel_data0 | ||
in | |||
out | xcvr_0_tester_3_data_format_adapter_1 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_data_format_adapter_0 | out | xcvr_0_tester_3_timing_adapter_tx0 | |
in | |||
xcvr_0_tester_3_tx_clk | out_clk | ||
clk | |||
xcvr_0_tester_3_clk_50 | clk_reset | ||
reset | |||
out | xcvr_0_xcvr_custom_phy_3 | ||
tx_parallel_data0 |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_3 | tx_clkout0 | xcvr_0_tester_3_tx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_3_timing_adapter_tx0 | ||
clk | |||
out_clk | xcvr_0_tester_3_data_format_adapter_0 | ||
clk | |||
out_clk | xcvr_0_tester_3_data_pattern_generator_0 | ||
pattern_out_clk |
Parameters
|
Software Assignments(none) |
xcvr_0_mm_bridge_0 | m0 | xcvr_0_xcvr_custom_phy_0 | |
phy_mgmt | |||
xcvr_0_tester_0_timing_adapter_tx0 | out | ||
tx_parallel_data0 | |||
xcvr_0_clk_100 | clk | ||
phy_mgmt_clk | |||
clk_reset | |||
phy_mgmt_clk_reset | |||
xcvr_0_alt_xcvr_reconfig_0 | ch0_1_to_xcvr | ||
reconfig_to_xcvr | |||
rx_parallel_data0 | xcvr_0_tester_0_timing_adapter_rx0 | ||
in | |||
rx_clkout0 | xcvr_0_tester_0_rx_clk | ||
in_clk | |||
tx_clkout0 | xcvr_0_tester_0_tx_clk | ||
in_clk | |||
reconfig_from_xcvr | xcvr_0_alt_xcvr_reconfig_0 | ||
ch0_1_from_xcvr |
Parameters
|
Software Assignments(none) |
xcvr_0_mm_bridge_0 | m0 | xcvr_0_xcvr_custom_phy_1 | |
phy_mgmt | |||
xcvr_0_tester_1_timing_adapter_tx0 | out | ||
tx_parallel_data0 | |||
xcvr_0_clk_100 | clk | ||
phy_mgmt_clk | |||
clk_reset | |||
phy_mgmt_clk_reset | |||
xcvr_0_alt_xcvr_reconfig_0 | ch2_3_from_xcvr | ||
reconfig_from_xcvr | |||
ch2_3_to_xcvr | |||
reconfig_to_xcvr | |||
rx_parallel_data0 | xcvr_0_tester_1_timing_adapter_rx0 | ||
in | |||
rx_clkout0 | xcvr_0_tester_1_rx_clk | ||
in_clk | |||
tx_clkout0 | xcvr_0_tester_1_tx_clk | ||
in_clk |
Parameters
|
Software Assignments(none) |
xcvr_0_mm_bridge_0 | m0 | xcvr_0_xcvr_custom_phy_2 | |
phy_mgmt | |||
xcvr_0_tester_2_timing_adapter_tx0 | out | ||
tx_parallel_data0 | |||
xcvr_0_clk_100 | clk | ||
phy_mgmt_clk | |||
clk_reset | |||
phy_mgmt_clk_reset | |||
xcvr_0_alt_xcvr_reconfig_0 | ch4_5_to_xcvr | ||
reconfig_to_xcvr | |||
rx_parallel_data0 | xcvr_0_tester_2_timing_adapter_rx0 | ||
in | |||
rx_clkout0 | xcvr_0_tester_2_rx_clk | ||
in_clk | |||
tx_clkout0 | xcvr_0_tester_2_tx_clk | ||
in_clk | |||
reconfig_from_xcvr | xcvr_0_alt_xcvr_reconfig_0 | ||
ch4_5_from_xcvr |
Parameters
|
Software Assignments(none) |
xcvr_0_mm_bridge_0 | m0 | xcvr_0_xcvr_custom_phy_3 | |
phy_mgmt | |||
xcvr_0_tester_3_timing_adapter_tx0 | out | ||
tx_parallel_data0 | |||
xcvr_0_clk_100 | clk | ||
phy_mgmt_clk | |||
clk_reset | |||
phy_mgmt_clk_reset | |||
xcvr_0_alt_xcvr_reconfig_0 | ch6_7_to_xcvr | ||
reconfig_to_xcvr | |||
rx_parallel_data0 | xcvr_0_tester_3_timing_adapter_rx0 | ||
in | |||
rx_clkout0 | xcvr_0_tester_3_rx_clk | ||
in_clk | |||
tx_clkout0 | xcvr_0_tester_3_tx_clk | ||
in_clk | |||
reconfig_from_xcvr | xcvr_0_alt_xcvr_reconfig_0 | ||
ch6_7_from_xcvr |
Parameters
|
Software Assignments(none) |
generation took 0.02 seconds | rendering took 0.13 seconds |