Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
u0|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 |
22 |
1 |
2 |
1 |
21 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_007 |
22 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 |
22 |
1 |
2 |
1 |
21 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_006 |
22 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_005 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_004 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_003 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_017|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_017 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_016|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_016 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_015|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_015 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_014|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_014 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_013|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_013 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_012|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_012 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_011|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_011 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_010|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_010 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_009|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_009 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_008|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_008 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_007|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_007 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_006|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_006 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_005|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_005 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_004|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_004 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_003|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_003 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_002|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_002 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_001|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline_001 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|mux_pipeline |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_015|core |
94 |
0 |
0 |
0 |
92 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_015 |
97 |
3 |
0 |
3 |
92 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_014|core |
102 |
0 |
0 |
0 |
100 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_014 |
104 |
2 |
0 |
2 |
100 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_013|core |
94 |
0 |
0 |
0 |
92 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_013 |
97 |
3 |
0 |
3 |
92 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_012|core |
102 |
0 |
0 |
0 |
100 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_012 |
104 |
2 |
0 |
2 |
100 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_011|core |
112 |
0 |
0 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_011 |
115 |
3 |
0 |
3 |
110 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_010|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_010 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_009|core |
112 |
0 |
0 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_009 |
115 |
3 |
0 |
3 |
110 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_008|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_008 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_007|core |
112 |
0 |
0 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_007 |
115 |
3 |
0 |
3 |
110 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_006|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_006 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_005|core |
112 |
0 |
0 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_005 |
115 |
3 |
0 |
3 |
110 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_004|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_004 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_003|core |
112 |
0 |
0 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_003 |
115 |
3 |
0 |
3 |
110 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_002|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_002 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_001|core |
112 |
0 |
0 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline_001 |
115 |
3 |
0 |
3 |
110 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|agent_pipeline |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|limiter_pipeline_001|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|limiter_pipeline_001 |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|limiter_pipeline|core |
120 |
0 |
0 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|limiter_pipeline |
122 |
2 |
0 |
2 |
118 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|flash_uas_cmd_width_adapter |
123 |
3 |
0 |
3 |
100 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|max_uas_cmd_width_adapter |
123 |
3 |
0 |
3 |
100 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|flash_uas_rsp_width_adapter|uncompressor |
46 |
4 |
0 |
4 |
39 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|flash_uas_rsp_width_adapter |
105 |
3 |
0 |
3 |
118 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|max_uas_rsp_width_adapter|uncompressor |
46 |
4 |
0 |
4 |
39 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|max_uas_rsp_width_adapter |
105 |
3 |
0 |
3 |
118 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001|arb|adder |
32 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001|arb |
12 |
0 |
4 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001 |
939 |
0 |
0 |
0 |
125 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux |
120 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_007 |
120 |
1 |
2 |
1 |
118 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_006 |
120 |
1 |
2 |
1 |
118 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_005 |
120 |
1 |
2 |
1 |
118 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_004 |
120 |
1 |
2 |
1 |
118 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_003 |
120 |
1 |
2 |
1 |
118 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_002 |
120 |
1 |
2 |
1 |
118 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_001 |
120 |
1 |
2 |
1 |
118 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux |
121 |
4 |
2 |
4 |
235 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_007 |
120 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_006 |
120 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_005 |
120 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_004 |
120 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_003 |
120 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_002 |
120 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_001 |
120 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux |
237 |
0 |
0 |
0 |
119 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_demux_001 |
127 |
64 |
2 |
64 |
937 |
64 |
64 |
64 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_demux |
120 |
1 |
2 |
1 |
118 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|flash_uas_burst_adapter|altera_merlin_burst_adapter_uncompressed_only.burst_adapter |
102 |
3 |
5 |
3 |
100 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|flash_uas_burst_adapter |
102 |
0 |
0 |
0 |
100 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|max_uas_burst_adapter|altera_merlin_burst_adapter_uncompressed_only.burst_adapter |
102 |
3 |
5 |
3 |
100 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|max_uas_burst_adapter |
102 |
0 |
0 |
0 |
100 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|master_0_master_limiter |
238 |
0 |
0 |
0 |
236 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_009|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_009 |
94 |
0 |
2 |
0 |
100 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_008|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_008 |
94 |
0 |
2 |
0 |
100 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_007|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_007 |
112 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_006|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_006 |
112 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_005|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_005 |
112 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_004|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_004 |
112 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_003|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_003 |
112 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_002|the_default_decode |
0 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_002 |
112 |
0 |
2 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_001|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_001 |
112 |
0 |
5 |
0 |
118 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router |
112 |
11 |
5 |
11 |
118 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|flash_uas_agent_rdata_fifo |
63 |
41 |
0 |
41 |
20 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|flash_uas_agent_rsp_fifo |
134 |
39 |
0 |
39 |
93 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|flash_uas_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|flash_uas_agent |
237 |
22 |
29 |
22 |
261 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|max_uas_agent_rdata_fifo |
63 |
41 |
0 |
41 |
20 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|max_uas_agent_rsp_fifo |
134 |
39 |
0 |
39 |
93 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|max_uas_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|max_uas_agent |
237 |
22 |
29 |
22 |
261 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|i2c_cont_bridge_0_slv_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|i2c_cont_bridge_0_slv_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|i2c_cont_bridge_0_slv_agent |
305 |
39 |
45 |
39 |
332 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|pio_pb_s1_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|pio_pb_s1_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|pio_pb_s1_agent |
305 |
39 |
45 |
39 |
332 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|pio_dipsw_s1_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|pio_dipsw_s1_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|pio_dipsw_s1_agent |
305 |
39 |
45 |
39 |
332 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|pio_led_s1_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|pio_led_s1_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|pio_led_s1_agent |
305 |
39 |
45 |
39 |
332 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|product_info_0_avalon_slave_0_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|product_info_0_avalon_slave_0_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|product_info_0_avalon_slave_0_agent |
305 |
39 |
45 |
39 |
332 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|opencores_i2c_0_avalon_slave_0_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|opencores_i2c_0_avalon_slave_0_agent|uncompressor |
46 |
1 |
0 |
1 |
44 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|opencores_i2c_0_avalon_slave_0_agent |
305 |
39 |
45 |
39 |
332 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|master_0_master_agent |
195 |
35 |
86 |
35 |
144 |
35 |
35 |
35 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|i2c_cont_bridge_0_avalon_master_agent |
195 |
35 |
86 |
35 |
144 |
35 |
35 |
35 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|flash_uas_translator |
80 |
4 |
5 |
4 |
69 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|max_uas_translator |
80 |
4 |
26 |
4 |
48 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|i2c_cont_bridge_0_slv_translator |
115 |
5 |
22 |
5 |
79 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|pio_pb_s1_translator |
115 |
6 |
33 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|pio_dipsw_s1_translator |
115 |
6 |
33 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|pio_led_s1_translator |
115 |
6 |
33 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|product_info_0_avalon_slave_0_translator |
115 |
6 |
30 |
6 |
38 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|opencores_i2c_0_avalon_slave_0_translator |
91 |
29 |
56 |
29 |
47 |
29 |
29 |
29 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|master_0_master_translator |
116 |
13 |
2 |
13 |
109 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|i2c_cont_bridge_0_avalon_master_translator |
95 |
37 |
1 |
37 |
108 |
37 |
37 |
37 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0 |
325 |
0 |
1 |
0 |
250 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|product_info_0 |
6 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|pio_pb |
7 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|pio_led |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
u0|pio_dipsw |
12 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|pin_sharer|arbiter|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|pin_sharer|arbiter|arb |
5 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|pin_sharer|arbiter |
5 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|pin_sharer|pin_sharer|tb_data_mux |
34 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|pin_sharer|pin_sharer|tb_data_outen_mux |
4 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|pin_sharer|pin_sharer|tb_address_mux |
56 |
21 |
1 |
21 |
27 |
21 |
21 |
21 |
0 |
0 |
0 |
0 |
0 |
u0|pin_sharer|pin_sharer |
96 |
0 |
0 |
0 |
88 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|pin_sharer |
94 |
0 |
0 |
0 |
85 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|opencores_i2c_0|i2c_master_top_inst|byte_controller|bit_controller |
27 |
2 |
0 |
2 |
8 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|opencores_i2c_0|i2c_master_top_inst|byte_controller |
35 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|opencores_i2c_0|i2c_master_top_inst |
19 |
1 |
0 |
1 |
14 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|opencores_i2c_0 |
15 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
u0|max|tda |
59 |
13 |
1 |
13 |
44 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|max|slave_translator |
54 |
6 |
0 |
6 |
43 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|max|tdt |
51 |
1 |
1 |
1 |
50 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|max |
49 |
0 |
0 |
0 |
45 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|p2b_adapter |
14 |
8 |
2 |
8 |
20 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|b2p_adapter |
22 |
0 |
2 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|transacto|p2m |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|transacto |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|p2b |
22 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|b2p |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|fifo |
53 |
41 |
0 |
41 |
10 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|timing_adt |
12 |
0 |
3 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser|crosser |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser |
13 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|output_stage |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser |
14 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_inserter |
12 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_remover |
12 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming |
20 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming |
19 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|jtag_phy_embedded_in_jtag_master|node |
4 |
3 |
0 |
3 |
8 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
u0|master_0|jtag_phy_embedded_in_jtag_master |
38 |
27 |
0 |
27 |
11 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
u0|master_0 |
36 |
0 |
0 |
0 |
70 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|i2c_cont_bridge_0 |
80 |
4 |
48 |
4 |
79 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|fm |
53 |
0 |
0 |
0 |
50 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
u0|flash|tda |
80 |
13 |
1 |
13 |
65 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|flash|slave_translator |
75 |
6 |
0 |
6 |
64 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|flash|tdt |
72 |
1 |
1 |
1 |
71 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|flash |
70 |
0 |
0 |
0 |
66 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0 |
13 |
0 |
0 |
0 |
41 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |