q_sys_lvds

2023.09.14.14:39:11 Datasheet
Overview
  clk_50  q_sys_lvds
  clk_rx 
  clk_tx 

All Components
   data_pattern_checker_0 altera_avalon_data_pattern_checker 22.1
   data_pattern_checker_1 altera_avalon_data_pattern_checker 22.1
   data_pattern_checker_2 altera_avalon_data_pattern_checker 22.1
   data_pattern_generator_0 altera_avalon_data_pattern_generator 22.1
   data_pattern_generator_1 altera_avalon_data_pattern_generator 22.1
   data_pattern_generator_2 altera_avalon_data_pattern_generator 22.1
   freq_counter_0 freq_counter 1.0
   freq_counter_1 freq_counter 1.0
   freq_counter_2 freq_counter 1.0
   master_driver_com_0 master_driver_com 1.0
   master_driver_com_1 master_driver_com 1.0
   master_driver_com_2 master_driver_com 1.0
   mm_bridge_0 altera_avalon_mm_bridge 22.1
   timer_0 altera_avalon_timer 22.1
   timer_1 altera_avalon_timer 22.1
   timer_2 altera_avalon_timer 22.1
Memory Map
master_driver_com_0 master_driver_com_1 master_driver_com_2
 avalon_master  avalon_master  avalon_master
  data_pattern_checker_0
csr_slave  0x00001020
  data_pattern_checker_1
csr_slave  0x00002020
  data_pattern_checker_2
csr_slave  0x00003020
  data_pattern_generator_0
csr_slave  0x00001000
  data_pattern_generator_1
csr_slave  0x00002000
  data_pattern_generator_2
csr_slave  0x00003000
  freq_counter_0
csr  0x00001200
  freq_counter_1
csr  0x00002200
  freq_counter_2
csr  0x00003200
  master_driver_com_0
csr 
  master_driver_com_1
csr 
  master_driver_com_2
csr 
  timer_0
s1  0x00001100
  timer_1
s1  0x00002100
  timer_2
s1  0x00003100

clk_50

clock_source v22.1


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

clk_rx

clock_source v22.1
clk_50 clk_reset   clk_rx
  clk_in_reset
clk   master_driver_com_2
  clock
clk   data_pattern_checker_2
  pattern_in_clk
clk   data_pattern_checker_1
  pattern_in_clk
clk   data_pattern_checker_0
  pattern_in_clk
clk   freq_counter_0
  sample_clock
clk   freq_counter_1
  sample_clock
clk   freq_counter_2
  sample_clock


Parameters

clockFrequency 50000000
clockFrequencyKnown false
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

clk_tx

clock_source v22.1
clk_50 clk_reset   clk_tx
  clk_in_reset
clk   data_pattern_generator_0
  pattern_out_clk
clk   data_pattern_generator_1
  pattern_out_clk
clk   data_pattern_generator_2
  pattern_out_clk


Parameters

clockFrequency 50000000
clockFrequencyKnown false
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

data_pattern_checker_0

altera_avalon_data_pattern_checker v22.1
master_driver_com_0 avalon_master   data_pattern_checker_0
  csr_slave
mm_bridge_0 m0  
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset
clk_rx clk  
  pattern_in_clk


Parameters

ST_DATA_W 32
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

data_pattern_checker_1

altera_avalon_data_pattern_checker v22.1
master_driver_com_1 avalon_master   data_pattern_checker_1
  csr_slave
mm_bridge_0 m0  
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset
clk_rx clk  
  pattern_in_clk


Parameters

ST_DATA_W 40
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

data_pattern_checker_2

altera_avalon_data_pattern_checker v22.1
master_driver_com_2 avalon_master   data_pattern_checker_2
  csr_slave
mm_bridge_0 m0  
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset
clk_rx clk  
  pattern_in_clk


Parameters

ST_DATA_W 64
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

data_pattern_generator_0

altera_avalon_data_pattern_generator v22.1
master_driver_com_0 avalon_master   data_pattern_generator_0
  csr_slave
mm_bridge_0 m0  
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset
clk_tx clk  
  pattern_out_clk


Parameters

ST_DATA_W 32
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

data_pattern_generator_1

altera_avalon_data_pattern_generator v22.1
master_driver_com_1 avalon_master   data_pattern_generator_1
  csr_slave
mm_bridge_0 m0  
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset
clk_tx clk  
  pattern_out_clk


Parameters

ST_DATA_W 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

data_pattern_generator_2

altera_avalon_data_pattern_generator v22.1
master_driver_com_2 avalon_master   data_pattern_generator_2
  csr_slave
mm_bridge_0 m0  
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset
clk_tx clk  
  pattern_out_clk


Parameters

ST_DATA_W 64
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

freq_counter_0

freq_counter v1.0
master_driver_com_0 avalon_master   freq_counter_0
  csr
mm_bridge_0 m0  
  csr
clk_50 clk  
  clock
clk_reset  
  reset
clk_rx clk  
  sample_clock


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 20000
DIV 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

freq_counter_1

freq_counter v1.0
master_driver_com_1 avalon_master   freq_counter_1
  csr
mm_bridge_0 m0  
  csr
clk_50 clk  
  clock
clk_reset  
  reset
clk_rx clk  
  sample_clock


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 20000
DIV 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

freq_counter_2

freq_counter v1.0
master_driver_com_2 avalon_master   freq_counter_2
  csr
mm_bridge_0 m0  
  csr
clk_50 clk  
  clock
clk_reset  
  reset
clk_rx clk  
  sample_clock


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 20000
DIV 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

master_driver_com_0

master_driver_com v1.0
mm_bridge_0 m0   master_driver_com_0
  csr
clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   freq_counter_0
  csr
avalon_master   data_pattern_checker_0
  csr_slave
avalon_master   data_pattern_generator_0
  csr_slave
avalon_master   timer_0
  s1


Parameters

CHECKER_BASE 4128
GENERATOR_BASE 4096
TIMER_BASE 4352
FREQ_BASE 4608
DESERIALIZATION_FACTOR 8
NUM_OF_CH 4
ENABLE_PER_INFO 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

master_driver_com_1

master_driver_com v1.0
mm_bridge_0 m0   master_driver_com_1
  csr
clk_50 clk  
  clock
clk_reset  
  reset
avalon_master   freq_counter_1
  csr
avalon_master   data_pattern_generator_1
  csr_slave
avalon_master   data_pattern_checker_1
  csr_slave
avalon_master   timer_1
  s1


Parameters

CHECKER_BASE 8224
GENERATOR_BASE 8192
TIMER_BASE 8448
FREQ_BASE 8704
DESERIALIZATION_FACTOR 8
NUM_OF_CH 5
ENABLE_PER_INFO 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

master_driver_com_2

master_driver_com v1.0
mm_bridge_0 m0   master_driver_com_2
  csr
clk_rx clk  
  clock
clk_50 clk_reset  
  reset
avalon_master   freq_counter_2
  csr
avalon_master   data_pattern_checker_2
  csr_slave
avalon_master   data_pattern_generator_2
  csr_slave
avalon_master   timer_2
  s1


Parameters

CHECKER_BASE 12320
GENERATOR_BASE 12288
TIMER_BASE 12544
FREQ_BASE 12800
DESERIALIZATION_FACTOR 8
NUM_OF_CH 8
ENABLE_PER_INFO 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mm_bridge_0

altera_avalon_mm_bridge v22.1
clk_50 clk   mm_bridge_0
  clk
clk_reset  
  reset
m0   master_driver_com_0
  csr
m0   master_driver_com_1
  csr
m0   master_driver_com_2
  csr
m0   freq_counter_0
  csr
m0   freq_counter_1
  csr
m0   freq_counter_2
  csr
m0   data_pattern_generator_0
  csr_slave
m0   data_pattern_generator_1
  csr_slave
m0   data_pattern_generator_2
  csr_slave
m0   data_pattern_checker_0
  csr_slave
m0   data_pattern_checker_1
  csr_slave
m0   data_pattern_checker_2
  csr_slave
m0   timer_0
  s1
m0   timer_1
  s1
m0   timer_2
  s1


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 14
SYSINFO_ADDR_WIDTH 14
USE_AUTO_ADDRESS_WIDTH 0
AUTO_ADDRESS_WIDTH 14
HDL_ADDR_WIDTH 14
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 4
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
USE_RESPONSE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

timer_0

altera_avalon_timer v22.1
master_driver_com_0 avalon_master   timer_0
  s1
mm_bridge_0 m0  
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

alwaysRun false
counterSize 64
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 100000000
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0.001
loadValue 99999
mult 0.001
ticksPerSec 1000.0
slave_address_width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 64
FIXED_PERIOD 0
FREQ 100000000
LOAD_VALUE 99999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0
TIMER_DEVICE_TYPE 1

timer_1

altera_avalon_timer v22.1
master_driver_com_1 avalon_master   timer_1
  s1
mm_bridge_0 m0  
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

alwaysRun false
counterSize 64
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 100000000
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0.001
loadValue 99999
mult 0.001
ticksPerSec 1000.0
slave_address_width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 64
FIXED_PERIOD 0
FREQ 100000000
LOAD_VALUE 99999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0
TIMER_DEVICE_TYPE 1

timer_2

altera_avalon_timer v22.1
master_driver_com_2 avalon_master   timer_2
  s1
mm_bridge_0 m0  
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

alwaysRun false
counterSize 64
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 100000000
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0.001
loadValue 99999
mult 0.001
ticksPerSec 1000.0
slave_address_width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 64
FIXED_PERIOD 0
FREQ 100000000
LOAD_VALUE 99999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0
TIMER_DEVICE_TYPE 1
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