q_sys

2023.07.24.14:20:38 Datasheet
Overview
  clk_0  q_sys

All Components
   flash altera_generic_tristate_controller 22.1
   i2c_cont_bridge_0 i2c_cont_bridge 1.0
   max altera_generic_tristate_controller 22.1
   opencores_i2c_0 opencores_i2c 9.1
   pio_dipsw altera_avalon_pio 22.1
   pio_led altera_avalon_pio 22.1
   pio_pb altera_avalon_pio 22.1
   product_info_0 product_info 1.0
Memory Map
i2c_cont_bridge_0 master_0
 avalon_master  master
  flash
uas  0x08000000
  i2c_cont_bridge_0
slv  0x00001000
  max
uas  0x00600000
  opencores_i2c_0
avalon_slave_0  0x00000060 0x00000060
  pio_dipsw
s1  0x00000030
  pio_led
s1  0x00000040
  pio_pb
s1  0x00000020
  product_info_0
avalon_slave_0  0x00000000

clk_0

clock_source v22.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

flash

altera_generic_tristate_controller v22.1
master_0 master   flash
  uas
clk_0 clk  
  clk
clk_reset  
  reset
tcm   pin_sharer
  tcs0


Parameters

TCM_ADDRESS_W 27
TCM_DATA_W 16
TCM_BYTEENABLE_W 2
TCM_READ_WAIT 100
TCM_WRITE_WAIT 100
TCM_SETUP_WAIT 25
TCM_DATA_HOLD 20
TCM_MAX_PENDING_READ_TRANSACTIONS 3
TCM_TURNAROUND_TIME 2
TCM_TIMING_UNITS 0
TCM_READLATENCY 2
TCM_SYMBOLS_PER_WORD 2
USE_READDATA 1
USE_WRITEDATA 1
USE_READ 1
USE_WRITE 1
USE_BEGINTRANSFER 0
USE_BYTEENABLE 0
USE_CHIPSELECT 1
USE_LOCK 0
USE_ADDRESS 1
USE_WAITREQUEST 0
USE_WRITEBYTEENABLE 0
USE_OUTPUTENABLE 0
USE_RESETREQUEST 0
USE_IRQ 0
USE_RESET_OUTPUT 0
ACTIVE_LOW_READ 1
ACTIVE_LOW_LOCK 0
ACTIVE_LOW_WRITE 1
ACTIVE_LOW_CHIPSELECT 1
ACTIVE_LOW_BYTEENABLE 0
ACTIVE_LOW_OUTPUTENABLE 0
ACTIVE_LOW_WRITEBYTEENABLE 0
ACTIVE_LOW_WAITREQUEST 0
ACTIVE_LOW_BEGINTRANSFER 0
ACTIVE_LOW_RESETREQUEST 0
ACTIVE_LOW_IRQ 0
ACTIVE_LOW_RESET_OUTPUT 0
CHIPSELECT_THROUGH_READLATENCY 0
IS_MEMORY_DEVICE 1
MODULE_ASSIGNMENT_KEYS embeddedsw.configuration.hwClassnameDriverSupportList,embeddedsw.configuration.hwClassnameDriverSupportDefault,embeddedsw.CMacro.SETUP_VALUE,embeddedsw.CMacro.WAIT_VALUE,embeddedsw.CMacro.HOLD_VALUE,embeddedsw.CMacro.TIMING_UNITS,embeddedsw.CMacro.SIZE,embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH,embeddedsw.memoryInfo.HAS_BYTE_LANE,embeddedsw.memoryInfo.IS_FLASH,embeddedsw.memoryInfo.GENERATE_DAT_SYM,embeddedsw.memoryInfo.GENERATE_FLASH,embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR,embeddedsw.memoryInfo.FLASH_INSTALL_DIR
MODULE_ASSIGNMENT_VALUES altera_avalon_lan91c111:altera_avalon_cfi_flash,altera_avalon_cfi_flash,25,100,20,ns,33554432u,16,1,1,1,1,SIM_DIR,APP_DIR
INTERFACE_ASSIGNMENT_KEYS embeddedsw.configuration.isFlash,embeddedsw.configuration.isMemoryDevice,embeddedsw.configuration.isNonVolatileStorage
INTERFACE_ASSIGNMENT_VALUES 1,1,1
CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CLK_CLOCK_DOMAIN 1
AUTO_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

HOLD_VALUE 20
SETUP_VALUE 25
SIZE 33554432u
TIMING_UNITS ns
WAIT_VALUE 100

fm

altera_tristate_conduit_bridge v22.1
clk_0 clk   fm
  clk
clk_reset  
  reset
pin_sharer tcm  
  tcs


Parameters

INTERFACE_INFO <info><slave name="tcs"><master name="pin_sharer.tcm"><pin role="" width="1" type="Invalid" output_name="" output_enable_name="" input_name="" /><pin role="max_oen" width="1" type="Output" output_name="max_oen" output_enable_name="" input_name="" /><pin role="max_wen" width="1" type="Output" output_name="max_wen" output_enable_name="" input_name="" /><pin role="max_csn" width="1" type="Output" output_name="max_csn" output_enable_name="" input_name="" /><pin role="tb_address" width="27" type="Output" output_name="tb_address" output_enable_name="" input_name="" /><pin role="flash_oen" width="1" type="Output" output_name="flash_oen" output_enable_name="" input_name="" /><pin role="flash_wen" width="1" type="Output" output_name="flash_wen" output_enable_name="" input_name="" /><pin role="tb_data" width="16" type="Bidirectional" output_name="tb_data" output_enable_name="tb_data_outen" input_name="tb_data_in" /><pin role="flash_csn" width="1" type="Output" output_name="flash_csn" output_enable_name="" input_name="" /></master></slave></info>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

i2c_cont_bridge_0

i2c_cont_bridge v1.0
master_0 master   i2c_cont_bridge_0
  slv
clk_0 clk  
  clock
clk_reset  
  reset
avalon_master   opencores_i2c_0
  avalon_slave_0


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

master_0

altera_jtag_avalon_master v22.1
clk_0 clk   master_0
  clk
clk_reset  
  clk_reset
master   product_info_0
  avalon_slave_0
master   opencores_i2c_0
  avalon_slave_0
master   pio_led
  s1
master   pio_dipsw
  s1
master   pio_pb
  s1
master   i2c_cont_bridge_0
  slv
master   max
  uas
master   flash
  uas


Parameters

USE_PLI 0
PLI_PORT 50000
COMPONENT_CLOCK 0
FAST_VER 0
FIFO_DEPTHS 2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

max

altera_generic_tristate_controller v22.1
master_0 master   max
  uas
clk_0 clk  
  clk
clk_reset  
  reset
tcm   pin_sharer
  tcs1


Parameters

TCM_ADDRESS_W 6
TCM_DATA_W 16
TCM_BYTEENABLE_W 2
TCM_READ_WAIT 100
TCM_WRITE_WAIT 100
TCM_SETUP_WAIT 60
TCM_DATA_HOLD 20
TCM_MAX_PENDING_READ_TRANSACTIONS 3
TCM_TURNAROUND_TIME 2
TCM_TIMING_UNITS 0
TCM_READLATENCY 2
TCM_SYMBOLS_PER_WORD 2
USE_READDATA 1
USE_WRITEDATA 1
USE_READ 1
USE_WRITE 1
USE_BEGINTRANSFER 0
USE_BYTEENABLE 0
USE_CHIPSELECT 1
USE_LOCK 0
USE_ADDRESS 1
USE_WAITREQUEST 0
USE_WRITEBYTEENABLE 0
USE_OUTPUTENABLE 0
USE_RESETREQUEST 0
USE_IRQ 0
USE_RESET_OUTPUT 0
ACTIVE_LOW_READ 1
ACTIVE_LOW_LOCK 0
ACTIVE_LOW_WRITE 1
ACTIVE_LOW_CHIPSELECT 1
ACTIVE_LOW_BYTEENABLE 0
ACTIVE_LOW_OUTPUTENABLE 0
ACTIVE_LOW_WRITEBYTEENABLE 0
ACTIVE_LOW_WAITREQUEST 0
ACTIVE_LOW_BEGINTRANSFER 0
ACTIVE_LOW_RESETREQUEST 0
ACTIVE_LOW_IRQ 0
ACTIVE_LOW_RESET_OUTPUT 0
CHIPSELECT_THROUGH_READLATENCY 0
IS_MEMORY_DEVICE 1
MODULE_ASSIGNMENT_KEYS embeddedsw.configuration.hwClassnameDriverSupportList,embeddedsw.configuration.hwClassnameDriverSupportDefault,embeddedsw.CMacro.SETUP_VALUE,embeddedsw.CMacro.WAIT_VALUE,embeddedsw.CMacro.HOLD_VALUE,embeddedsw.CMacro.TIMING_UNITS,embeddedsw.CMacro.SIZE,embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH,embeddedsw.memoryInfo.HAS_BYTE_LANE,embeddedsw.memoryInfo.IS_FLASH,embeddedsw.memoryInfo.GENERATE_DAT_SYM,embeddedsw.memoryInfo.GENERATE_FLASH,embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR,embeddedsw.memoryInfo.FLASH_INSTALL_DIR
MODULE_ASSIGNMENT_VALUES altera_avalon_lan91c111:altera_avalon_cfi_flash,altera_avalon_cfi_flash,60,100,20,ns,16777216u,16,1,1,1,1,SIM_DIR,APP_DIR
INTERFACE_ASSIGNMENT_KEYS embeddedsw.configuration.isFlash,embeddedsw.configuration.isMemoryDevice,embeddedsw.configuration.isNonVolatileStorage
INTERFACE_ASSIGNMENT_VALUES 1,1,1
CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CLK_CLOCK_DOMAIN 1
AUTO_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

HOLD_VALUE 20
SETUP_VALUE 60
SIZE 16777216u
TIMING_UNITS ns
WAIT_VALUE 100

opencores_i2c_0

opencores_i2c v9.1
i2c_cont_bridge_0 avalon_master   opencores_i2c_0
  avalon_slave_0
master_0 master  
  avalon_slave_0
clk_0 clk  
  clock
clk_reset  
  clock_reset


Parameters

AUTO_CLOCK_CLOCK_RATE 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

pin_sharer

altera_tristate_conduit_pin_sharer v22.1
clk_0 clk   pin_sharer
  clk
clk_reset  
  reset
flash tcm  
  tcs0
max tcm  
  tcs1
tcm   fm
  tcs


Parameters

INTERFACE_INFO <info><slave name="tcs0"><master name="flash.tcm"><pin role="write_n" width="1" type="Output" output_name="tcm_write_n_out" output_enable_name="" input_name="" /><pin role="read_n" width="1" type="Output" output_name="tcm_read_n_out" output_enable_name="" input_name="" /><pin role="chipselect_n" width="1" type="Output" output_name="tcm_chipselect_n_out" output_enable_name="" input_name="" /><pin role="" width="1" type="Invalid" output_name="" output_enable_name="" input_name="" /><pin role="address" width="27" type="Output" output_name="tcm_address_out" output_enable_name="" input_name="" /><pin role="data" width="16" type="Bidirectional" output_name="tcm_data_out" output_enable_name="tcm_data_outen" input_name="tcm_data_in" /></master></slave><slave name="tcs1"><master name="max.tcm"><pin role="write_n" width="1" type="Output" output_name="tcm_write_n_out" output_enable_name="" input_name="" /><pin role="read_n" width="1" type="Output" output_name="tcm_read_n_out" output_enable_name="" input_name="" /><pin role="chipselect_n" width="1" type="Output" output_name="tcm_chipselect_n_out" output_enable_name="" input_name="" /><pin role="" width="1" type="Invalid" output_name="" output_enable_name="" input_name="" /><pin role="address" width="6" type="Output" output_name="tcm_address_out" output_enable_name="" input_name="" /><pin role="data" width="16" type="Bidirectional" output_name="tcm_data_out" output_enable_name="tcm_data_outen" input_name="tcm_data_in" /></master></slave></info>
NUM_INTERFACES 2
MODULE_ORIGIN_LIST max.tcm,max.tcm,max.tcm,max.tcm,max.tcm,flash.tcm,flash.tcm,flash.tcm,flash.tcm,flash.tcm
SIGNAL_ORIGIN_LIST address,read_n,write_n,data,chipselect_n,address,read_n,write_n,data,chipselect_n
SIGNAL_ORIGIN_TYPE Output,Output,Output,Bidirectional,Output,Output,Output,Output,Bidirectional,Output
SIGNAL_ORIGIN_WIDTH 6,1,1,16,1,27,1,1,16,1
SHARED_SIGNAL_LIST tb_address,max_oen,max_wen,tb_data,max_csn,tb_address,flash_oen,flash_wen,tb_data,flash_csn
SIGNAL_OUTPUT_NAMES tcm_address_out,tcm_read_n_out,tcm_write_n_out,tcm_data_out,tcm_chipselect_n_out,tcm_address_out,tcm_read_n_out,tcm_write_n_out,tcm_data_out,tcm_chipselect_n_out
SIGNAL_INPUT_NAMES ,,,tcm_data_in,,,,,tcm_data_in
SIGNAL_OUTPUT_ENABLE_NAMES ,,,tcm_data_outen,,,,,tcm_data_outen
REALTIME_MODULE_ORIGIN_LIST max.tcm,max.tcm,max.tcm,max.tcm,max.tcm,flash.tcm,flash.tcm,flash.tcm,flash.tcm,flash.tcm
REALTIME_SIGNAL_ORIGIN_LIST address,read_n,write_n,data,chipselect_n,address,read_n,write_n,data,chipselect_n
REALTIME_SHARED_SIGNAL_LIST tb_address,max_oen,max_wen,tb_data,max_csn,tb_address,flash_oen,flash_wen,tb_data,flash_csn
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGTFD9E5F35C7
AUTO_DEVICE_SPEEDGRADE 7_H5
AUTO_CLK_CLOCK_RATE 50000000
AUTO_CLK_CLOCK_DOMAIN 1
AUTO_CLK_RESET_DOMAIN 1
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

pio_dipsw

altera_avalon_pio v22.1
master_0 master   pio_dipsw
  s1
clk_0 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
clockRate 50000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 8
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_led

altera_avalon_pio v22.1
master_0 master   pio_led
  s1
clk_0 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
clockRate 50000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 8
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_pb

altera_avalon_pio v22.1
master_0 master   pio_pb
  s1
clk_0 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 3
clockRate 50000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 3
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

product_info_0

product_info v1.0
master_0 master   product_info_0
  avalon_slave_0
clk_0 clk  
  clock_reset
clk_reset  
  clock_reset_reset


Parameters

AUTO_DEVICE_FAMILY CYCLONEV
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)
generation took 0.00 seconds rendering took 0.04 seconds