q_sys |
|
2014.12.30.15:07:16 | Datasheet |
clk_100 | q_sys |
lvds_0_clk_50 | |
lvds_0_clk_tx | |
lvds_0_clk_rx | |
cmos_0_clkin | |
xcvr_0_clk_100 | |
xcvr_0_tester_0_clk_50 | |
xcvr_0_tester_1_clk_50 | |
xcvr_0_tester_2_clk_50 | |
xcvr_0_tester_3_clk_50 | |
xcvr_0_clk_50 | |
clk_50 | |
Parameters
|
Software Assignments(none) |
clk_50 | clk | master_0 | |
clk | |||
clk_reset | |||
clk_reset | |||
master | cmos_0_mm_bridge_0 | ||
s0 | |||
master | lvds_0_mm_bridge_0 | ||
s0 | |||
master | xcvr_0_mm_bridge_0 | ||
s0 | |||
master | product_info_0 | ||
avalon_slave_0 |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_50 | clk | lvds_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | lvds_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | lvds_0_data_pattern_generator_1 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | lvds_0_data_pattern_generator_2 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | lvds_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | lvds_0_data_pattern_checker_2 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | lvds_0_data_pattern_checker_1 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk_reset | lvds_0_clk_tx | ||
clk_in_reset | |||
clk_reset | lvds_0_clk_rx | ||
clk_in_reset | |||
clk_reset | lvds_0_timer_0 | ||
reset | |||
clk | |||
clk | |||
clk_reset | lvds_0_master_driver_com_0 | ||
reset | |||
clk | |||
clock | |||
clk | lvds_0_timer_1 | ||
clk | |||
clk_reset | |||
reset | |||
clk_reset | lvds_0_master_driver_com_1 | ||
reset | |||
clk | |||
clock | |||
clk | lvds_0_timer_2 | ||
clk | |||
clk_reset | |||
reset | |||
clk_reset | lvds_0_master_driver_com_2 | ||
reset | |||
clk | lvds_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk_reset | lvds_0_freq_counter_0 | ||
reset | |||
clk | |||
clock | |||
clk_reset | lvds_0_freq_counter_1 | ||
reset | |||
clk | |||
clock | |||
clk_reset | lvds_0_freq_counter_2 | ||
reset | |||
clk | |||
clock |
Parameters
|
Software Assignments(none) |
lvds_0_clk_tx | clk | lvds_0_data_pattern_generator_0 |
pattern_out_clk | ||
lvds_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
lvds_0_master_driver_com_0 | avalon_master | |
csr_slave | ||
lvds_0_mm_bridge_0 | m0 | |
csr_slave |
Parameters
|
Software Assignments(none) |
lvds_0_clk_tx | clk | lvds_0_data_pattern_generator_1 |
pattern_out_clk | ||
lvds_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
lvds_0_master_driver_com_1 | avalon_master | |
csr_slave | ||
lvds_0_mm_bridge_0 | m0 | |
csr_slave |
Parameters
|
Software Assignments(none) |
lvds_0_clk_tx | clk | lvds_0_data_pattern_generator_2 |
pattern_out_clk | ||
lvds_0_clk_50 | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
lvds_0_master_driver_com_2 | avalon_master | |
csr_slave | ||
lvds_0_mm_bridge_0 | m0 | |
csr_slave |
Parameters
|
Software Assignments(none) |
lvds_0_clk_50 | clk | lvds_0_data_pattern_checker_0 |
csr_clk | ||
clk_reset | ||
reset | ||
lvds_0_clk_rx | clk | |
pattern_in_clk | ||
lvds_0_master_driver_com_0 | avalon_master | |
csr_slave | ||
lvds_0_mm_bridge_0 | m0 | |
csr_slave |
Parameters
|
Software Assignments(none) |
lvds_0_clk_50 | clk | lvds_0_data_pattern_checker_1 |
csr_clk | ||
clk_reset | ||
reset | ||
lvds_0_clk_rx | clk | |
pattern_in_clk | ||
lvds_0_master_driver_com_1 | avalon_master | |
csr_slave | ||
lvds_0_mm_bridge_0 | m0 | |
csr_slave |
Parameters
|
Software Assignments(none) |
lvds_0_clk_50 | clk | lvds_0_data_pattern_checker_2 |
csr_clk | ||
clk_reset | ||
reset | ||
lvds_0_clk_rx | clk | |
pattern_in_clk | ||
lvds_0_master_driver_com_2 | avalon_master | |
csr_slave | ||
lvds_0_mm_bridge_0 | m0 | |
csr_slave |
Parameters
|
Software Assignments(none) |
lvds_0_clk_50 | clk_reset | lvds_0_clk_tx | |
clk_in_reset | |||
clk | lvds_0_data_pattern_generator_0 | ||
pattern_out_clk | |||
clk | lvds_0_data_pattern_generator_1 | ||
pattern_out_clk | |||
clk | lvds_0_data_pattern_generator_2 | ||
pattern_out_clk |
Parameters
|
Software Assignments(none) |
lvds_0_clk_50 | clk_reset | lvds_0_clk_rx | |
clk_in_reset | |||
clk | lvds_0_data_pattern_checker_2 | ||
pattern_in_clk | |||
clk | lvds_0_data_pattern_checker_1 | ||
pattern_in_clk | |||
clk | lvds_0_data_pattern_checker_0 | ||
pattern_in_clk | |||
clk | lvds_0_master_driver_com_2 | ||
clock | |||
clk | lvds_0_freq_counter_0 | ||
sample_clock | |||
clk | lvds_0_freq_counter_1 | ||
sample_clock | |||
clk | lvds_0_freq_counter_2 | ||
sample_clock |
Parameters
|
Software Assignments(none) |
lvds_0_clk_50 | clk_reset | lvds_0_timer_0 |
reset | ||
clk | ||
clk | ||
lvds_0_master_driver_com_0 | avalon_master | |
s1 | ||
lvds_0_mm_bridge_0 | m0 | |
s1 |
Parameters
|
Software Assignments
|
lvds_0_clk_50 | clk_reset | lvds_0_master_driver_com_0 | |
reset | |||
clk | |||
clock | |||
lvds_0_mm_bridge_0 | m0 | ||
csr | |||
avalon_master | lvds_0_timer_0 | ||
s1 | |||
avalon_master | lvds_0_data_pattern_checker_0 | ||
csr_slave | |||
avalon_master | lvds_0_data_pattern_generator_0 | ||
csr_slave | |||
avalon_master | lvds_0_freq_counter_0 | ||
csr |
Parameters
|
Software Assignments(none) |
lvds_0_clk_50 | clk | lvds_0_timer_1 |
clk | ||
clk_reset | ||
reset | ||
lvds_0_master_driver_com_1 | avalon_master | |
s1 | ||
lvds_0_mm_bridge_0 | m0 | |
s1 |
Parameters
|
Software Assignments
|
lvds_0_clk_50 | clk_reset | lvds_0_master_driver_com_1 | |
reset | |||
clk | |||
clock | |||
lvds_0_mm_bridge_0 | m0 | ||
csr | |||
avalon_master | lvds_0_timer_1 | ||
s1 | |||
avalon_master | lvds_0_data_pattern_generator_1 | ||
csr_slave | |||
avalon_master | lvds_0_data_pattern_checker_1 | ||
csr_slave | |||
avalon_master | lvds_0_freq_counter_1 | ||
csr |
Parameters
|
Software Assignments(none) |
lvds_0_clk_50 | clk | lvds_0_timer_2 |
clk | ||
clk_reset | ||
reset | ||
lvds_0_master_driver_com_2 | avalon_master | |
s1 | ||
lvds_0_mm_bridge_0 | m0 | |
s1 |
Parameters
|
Software Assignments
|
lvds_0_clk_50 | clk_reset | lvds_0_master_driver_com_2 | |
reset | |||
lvds_0_clk_rx | clk | ||
clock | |||
lvds_0_mm_bridge_0 | m0 | ||
csr | |||
avalon_master | lvds_0_timer_2 | ||
s1 | |||
avalon_master | lvds_0_data_pattern_checker_2 | ||
csr_slave | |||
avalon_master | lvds_0_data_pattern_generator_2 | ||
csr_slave | |||
avalon_master | lvds_0_freq_counter_2 | ||
csr |
Parameters
|
Software Assignments(none) |
lvds_0_clk_50 | clk | lvds_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | lvds_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | lvds_0_data_pattern_generator_1 | ||
csr_slave | |||
m0 | lvds_0_data_pattern_generator_2 | ||
csr_slave | |||
m0 | lvds_0_data_pattern_checker_0 | ||
csr_slave | |||
m0 | lvds_0_data_pattern_checker_1 | ||
csr_slave | |||
m0 | lvds_0_data_pattern_checker_2 | ||
csr_slave | |||
m0 | lvds_0_timer_0 | ||
s1 | |||
m0 | lvds_0_master_driver_com_0 | ||
csr | |||
m0 | lvds_0_timer_1 | ||
s1 | |||
m0 | lvds_0_master_driver_com_1 | ||
csr | |||
m0 | lvds_0_timer_2 | ||
s1 | |||
m0 | lvds_0_master_driver_com_2 | ||
csr | |||
m0 | lvds_0_freq_counter_0 | ||
csr | |||
m0 | lvds_0_freq_counter_1 | ||
csr | |||
m0 | lvds_0_freq_counter_2 | ||
csr |
Parameters
|
Software Assignments(none) |
lvds_0_clk_50 | clk_reset | lvds_0_freq_counter_0 |
reset | ||
clk | ||
clock | ||
lvds_0_master_driver_com_0 | avalon_master | |
csr | ||
lvds_0_mm_bridge_0 | m0 | |
csr | ||
lvds_0_clk_rx | clk | |
sample_clock |
Parameters
|
Software Assignments(none) |
lvds_0_clk_50 | clk_reset | lvds_0_freq_counter_1 |
reset | ||
clk | ||
clock | ||
lvds_0_mm_bridge_0 | m0 | |
csr | ||
lvds_0_master_driver_com_1 | avalon_master | |
csr | ||
lvds_0_clk_rx | clk | |
sample_clock |
Parameters
|
Software Assignments(none) |
lvds_0_clk_50 | clk_reset | lvds_0_freq_counter_2 |
reset | ||
clk | ||
clock | ||
lvds_0_mm_bridge_0 | m0 | |
csr | ||
lvds_0_master_driver_com_2 | avalon_master | |
csr | ||
lvds_0_clk_rx | clk | |
sample_clock |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_50 | clk | cmos_0_clkin | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | cmos_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | cmos_0_tx_clk | ||
in_clk | |||
clk | cmos_0_rx_clk | ||
in_clk | |||
clk | cmos_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | cmos_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk_reset | cmos_0_master_driver_com_0 | ||
reset | |||
clk | |||
clock | |||
clk | cmos_0_timer_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk_reset | cmos_0_freq_counter_0 | ||
reset | |||
clk | |||
clock |
Parameters
|
Software Assignments(none) |
cmos_0_tx_clk | out_clk | cmos_0_data_pattern_generator_0 |
pattern_out_clk | ||
cmos_0_mm_bridge_0 | m0 | |
csr_slave | ||
cmos_0_clkin | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
cmos_0_master_driver_com_0 | avalon_master | |
csr_slave |
Parameters
|
Software Assignments(none) |
cmos_0_rx_clk | out_clk | cmos_0_data_pattern_checker_0 |
pattern_in_clk | ||
cmos_0_mm_bridge_0 | m0 | |
csr_slave | ||
cmos_0_clkin | clk | |
csr_clk | ||
clk_reset | ||
reset | ||
cmos_0_master_driver_com_0 | avalon_master | |
csr_slave |
Parameters
|
Software Assignments(none) |
cmos_0_clkin | clk | cmos_0_rx_clk | |
in_clk | |||
out_clk | cmos_0_data_pattern_checker_0 | ||
pattern_in_clk | |||
out_clk | cmos_0_freq_counter_0 | ||
sample_clock |
Parameters
|
Software Assignments(none) |
cmos_0_clkin | clk | cmos_0_tx_clk | |
in_clk | |||
out_clk | cmos_0_data_pattern_generator_0 | ||
pattern_out_clk |
Parameters
|
Software Assignments(none) |
cmos_0_clkin | clk | cmos_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | cmos_0_data_pattern_checker_0 | ||
csr_slave | |||
m0 | cmos_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | cmos_0_master_driver_com_0 | ||
csr | |||
m0 | cmos_0_timer_0 | ||
s1 | |||
m0 | cmos_0_freq_counter_0 | ||
csr |
Parameters
|
Software Assignments(none) |
cmos_0_clkin | clk_reset | cmos_0_master_driver_com_0 | |
reset | |||
clk | |||
clock | |||
cmos_0_mm_bridge_0 | m0 | ||
csr | |||
avalon_master | cmos_0_data_pattern_checker_0 | ||
csr_slave | |||
avalon_master | cmos_0_data_pattern_generator_0 | ||
csr_slave | |||
avalon_master | cmos_0_timer_0 | ||
s1 | |||
avalon_master | cmos_0_freq_counter_0 | ||
csr |
Parameters
|
Software Assignments(none) |
cmos_0_clkin | clk | cmos_0_timer_0 |
clk | ||
clk_reset | ||
reset | ||
cmos_0_mm_bridge_0 | m0 | |
s1 | ||
cmos_0_master_driver_com_0 | avalon_master | |
s1 |
Parameters
|
Software Assignments
|
cmos_0_clkin | clk_reset | cmos_0_freq_counter_0 |
reset | ||
clk | ||
clock | ||
cmos_0_master_driver_com_0 | avalon_master | |
csr | ||
cmos_0_mm_bridge_0 | m0 | |
csr | ||
cmos_0_rx_clk | out_clk | |
sample_clock |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
clk_100 | clk | xcvr_0_clk_100 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk_reset | xcvr_0_xcvr_custom_phy_0 | ||
phy_mgmt_clk_reset | |||
clk | |||
phy_mgmt_clk | |||
clk | xcvr_0_alt_xcvr_reconfig_0 | ||
mgmt_clk_clk | |||
clk_reset | |||
mgmt_rst_reset |
Parameters
|
Software Assignments(none) |
xcvr_0_clk_100 | clk_reset | xcvr_0_xcvr_custom_phy_0 | |
phy_mgmt_clk_reset | |||
clk | |||
phy_mgmt_clk | |||
xcvr_0_tester_0_timing_adapter_tx0 | out | ||
tx_parallel_data0 | |||
xcvr_0_tester_1_timing_adapter_tx0 | out | ||
tx_parallel_data1 | |||
xcvr_0_tester_2_timing_adapter_tx0 | out | ||
tx_parallel_data2 | |||
xcvr_0_tester_3_timing_adapter_tx0 | out | ||
tx_parallel_data3 | |||
xcvr_0_mm_bridge_0 | m0 | ||
phy_mgmt | |||
reconfig_to_xcvr | xcvr_0_alt_xcvr_reconfig_0 | ||
reconfig_to_xcvr | |||
reconfig_from_xcvr | |||
reconfig_from_xcvr | |||
rx_clkout0 | xcvr_0_tester_0_rx_clk | ||
in_clk | |||
tx_clkout0 | xcvr_0_tester_0_tx_clk | ||
in_clk | |||
rx_parallel_data0 | xcvr_0_tester_0_timing_adapter_rx0 | ||
in | |||
rx_clkout1 | xcvr_0_tester_1_rx_clk | ||
in_clk | |||
tx_clkout1 | xcvr_0_tester_1_tx_clk | ||
in_clk | |||
rx_clkout2 | xcvr_0_tester_2_rx_clk | ||
in_clk | |||
tx_clkout2 | xcvr_0_tester_2_tx_clk | ||
in_clk | |||
rx_clkout3 | xcvr_0_tester_3_rx_clk | ||
in_clk | |||
tx_clkout3 | xcvr_0_tester_3_tx_clk | ||
in_clk | |||
rx_parallel_data1 | xcvr_0_tester_1_timing_adapter_rx0 | ||
in | |||
rx_parallel_data2 | xcvr_0_tester_2_timing_adapter_rx0 | ||
in | |||
rx_parallel_data3 | xcvr_0_tester_3_timing_adapter_rx0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_0 | reconfig_to_xcvr | xcvr_0_alt_xcvr_reconfig_0 |
reconfig_to_xcvr | ||
reconfig_from_xcvr | ||
reconfig_from_xcvr | ||
xcvr_0_clk_100 | clk | |
mgmt_clk_clk | ||
clk_reset | ||
mgmt_rst_reset | ||
xcvr_0_mm_bridge_0 | m0 | |
reconfig_mgmt |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
xcvr_0_clk_50 | clk | xcvr_0_tester_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk_reset | xcvr_0_tester_0_timing_adapter_tx0 | ||
reset | |||
clk_reset | xcvr_0_tester_0_timing_adapter_rx0 | ||
reset | |||
clk | xcvr_0_tester_0_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_0_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_0_data_format_adapter_0 | ||
reset | |||
clk_reset | xcvr_0_tester_0_data_format_adapter_1 | ||
reset | |||
clk | xcvr_0_tester_0_timer_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_0_master_driver_com_0 | ||
reset | |||
clk | |||
clock | |||
clk | xcvr_0_tester_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_0_freq_counter_0 | ||
reset | |||
clk | |||
clock |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_clk_50 | clk | xcvr_0_tester_0_data_pattern_generator_0 | |
csr_clk | |||
clk_reset | |||
reset | |||
xcvr_0_tester_0_tx_clk | out_clk | ||
pattern_out_clk | |||
xcvr_0_tester_0_mm_bridge_0 | m0 | ||
csr_slave | |||
xcvr_0_tester_0_master_driver_com_0 | avalon_master | ||
csr_slave | |||
pattern_out | xcvr_0_tester_0_data_format_adapter_0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_clk_50 | clk | xcvr_0_tester_0_data_pattern_checker_0 |
csr_clk | ||
clk_reset | ||
reset | ||
xcvr_0_tester_0_rx_clk | out_clk | |
pattern_in_clk | ||
xcvr_0_tester_0_data_format_adapter_1 | out | |
pattern_in | ||
xcvr_0_tester_0_mm_bridge_0 | m0 | |
csr_slave | ||
xcvr_0_tester_0_master_driver_com_0 | avalon_master | |
csr_slave |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_clk_50 | clk_reset | xcvr_0_tester_0_timing_adapter_tx0 | |
reset | |||
xcvr_0_tester_0_tx_clk | out_clk | ||
clk | |||
xcvr_0_tester_0_data_format_adapter_0 | out | ||
in | |||
out | xcvr_0_xcvr_custom_phy_0 | ||
tx_parallel_data0 |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_clk_50 | clk_reset | xcvr_0_tester_0_timing_adapter_rx0 | |
reset | |||
xcvr_0_tester_0_rx_clk | out_clk | ||
clk | |||
xcvr_0_xcvr_custom_phy_0 | rx_parallel_data0 | ||
in | |||
out | xcvr_0_tester_0_data_format_adapter_1 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_0 | rx_clkout0 | xcvr_0_tester_0_rx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_0_timing_adapter_rx0 | ||
clk | |||
out_clk | xcvr_0_tester_0_data_pattern_checker_0 | ||
pattern_in_clk | |||
out_clk | xcvr_0_tester_0_data_format_adapter_1 | ||
clk | |||
out_clk | xcvr_0_tester_0_freq_counter_0 | ||
sample_clock |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_0 | tx_clkout0 | xcvr_0_tester_0_tx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_0_timing_adapter_tx0 | ||
clk | |||
out_clk | xcvr_0_tester_0_data_pattern_generator_0 | ||
pattern_out_clk | |||
out_clk | xcvr_0_tester_0_data_format_adapter_0 | ||
clk |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_tx_clk | out_clk | xcvr_0_tester_0_data_format_adapter_0 | |
clk | |||
xcvr_0_tester_0_clk_50 | clk_reset | ||
reset | |||
xcvr_0_tester_0_data_pattern_generator_0 | pattern_out | ||
in | |||
out | xcvr_0_tester_0_timing_adapter_tx0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_rx_clk | out_clk | xcvr_0_tester_0_data_format_adapter_1 | |
clk | |||
xcvr_0_tester_0_clk_50 | clk_reset | ||
reset | |||
xcvr_0_tester_0_timing_adapter_rx0 | out | ||
in | |||
out | xcvr_0_tester_0_data_pattern_checker_0 | ||
pattern_in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_clk_50 | clk | xcvr_0_tester_0_timer_0 |
clk | ||
clk_reset | ||
reset | ||
xcvr_0_tester_0_mm_bridge_0 | m0 | |
s1 | ||
xcvr_0_tester_0_master_driver_com_0 | avalon_master | |
s1 |
Parameters
|
Software Assignments
|
xcvr_0_tester_0_clk_50 | clk_reset | xcvr_0_tester_0_master_driver_com_0 | |
reset | |||
clk | |||
clock | |||
xcvr_0_tester_0_mm_bridge_0 | m0 | ||
csr | |||
avalon_master | xcvr_0_tester_0_timer_0 | ||
s1 | |||
avalon_master | xcvr_0_tester_0_data_pattern_checker_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_0_data_pattern_generator_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_0_freq_counter_0 | ||
csr |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_clk_50 | clk | xcvr_0_tester_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
xcvr_0_mm_bridge_0 | m0 | ||
s0 | |||
m0 | xcvr_0_tester_0_master_driver_com_0 | ||
csr | |||
m0 | xcvr_0_tester_0_timer_0 | ||
s1 | |||
m0 | xcvr_0_tester_0_data_pattern_checker_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_0_data_pattern_generator_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_0_freq_counter_0 | ||
csr |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_0_clk_50 | clk_reset | xcvr_0_tester_0_freq_counter_0 |
reset | ||
clk | ||
clock | ||
xcvr_0_tester_0_mm_bridge_0 | m0 | |
csr | ||
xcvr_0_tester_0_master_driver_com_0 | avalon_master | |
csr | ||
xcvr_0_tester_0_rx_clk | out_clk | |
sample_clock |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
xcvr_0_clk_50 | clk | xcvr_0_tester_1_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk_reset | xcvr_0_tester_1_timing_adapter_tx0 | ||
reset | |||
clk_reset | xcvr_0_tester_1_timing_adapter_rx0 | ||
reset | |||
clk | xcvr_0_tester_1_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_1_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_1_data_format_adapter_0 | ||
reset | |||
clk_reset | xcvr_0_tester_1_data_format_adapter_1 | ||
reset | |||
clk | xcvr_0_tester_1_timer_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_1_master_driver_com_0 | ||
reset | |||
clk | |||
clock | |||
clk | xcvr_0_tester_1_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_1_freq_counter_0 | ||
reset | |||
clk | |||
clock |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_clk_50 | clk | xcvr_0_tester_1_data_pattern_generator_0 | |
csr_clk | |||
clk_reset | |||
reset | |||
xcvr_0_tester_1_tx_clk | out_clk | ||
pattern_out_clk | |||
xcvr_0_tester_1_mm_bridge_0 | m0 | ||
csr_slave | |||
xcvr_0_tester_1_master_driver_com_0 | avalon_master | ||
csr_slave | |||
pattern_out | xcvr_0_tester_1_data_format_adapter_0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_clk_50 | clk | xcvr_0_tester_1_data_pattern_checker_0 |
csr_clk | ||
clk_reset | ||
reset | ||
xcvr_0_tester_1_rx_clk | out_clk | |
pattern_in_clk | ||
xcvr_0_tester_1_data_format_adapter_1 | out | |
pattern_in | ||
xcvr_0_tester_1_mm_bridge_0 | m0 | |
csr_slave | ||
xcvr_0_tester_1_master_driver_com_0 | avalon_master | |
csr_slave |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_clk_50 | clk_reset | xcvr_0_tester_1_timing_adapter_tx0 | |
reset | |||
xcvr_0_tester_1_tx_clk | out_clk | ||
clk | |||
xcvr_0_tester_1_data_format_adapter_0 | out | ||
in | |||
out | xcvr_0_xcvr_custom_phy_0 | ||
tx_parallel_data1 |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_clk_50 | clk_reset | xcvr_0_tester_1_timing_adapter_rx0 | |
reset | |||
xcvr_0_tester_1_rx_clk | out_clk | ||
clk | |||
xcvr_0_xcvr_custom_phy_0 | rx_parallel_data1 | ||
in | |||
out | xcvr_0_tester_1_data_format_adapter_1 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_0 | rx_clkout1 | xcvr_0_tester_1_rx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_1_timing_adapter_rx0 | ||
clk | |||
out_clk | xcvr_0_tester_1_data_pattern_checker_0 | ||
pattern_in_clk | |||
out_clk | xcvr_0_tester_1_data_format_adapter_1 | ||
clk | |||
out_clk | xcvr_0_tester_1_freq_counter_0 | ||
sample_clock |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_0 | tx_clkout1 | xcvr_0_tester_1_tx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_1_timing_adapter_tx0 | ||
clk | |||
out_clk | xcvr_0_tester_1_data_pattern_generator_0 | ||
pattern_out_clk | |||
out_clk | xcvr_0_tester_1_data_format_adapter_0 | ||
clk |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_tx_clk | out_clk | xcvr_0_tester_1_data_format_adapter_0 | |
clk | |||
xcvr_0_tester_1_clk_50 | clk_reset | ||
reset | |||
xcvr_0_tester_1_data_pattern_generator_0 | pattern_out | ||
in | |||
out | xcvr_0_tester_1_timing_adapter_tx0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_rx_clk | out_clk | xcvr_0_tester_1_data_format_adapter_1 | |
clk | |||
xcvr_0_tester_1_clk_50 | clk_reset | ||
reset | |||
xcvr_0_tester_1_timing_adapter_rx0 | out | ||
in | |||
out | xcvr_0_tester_1_data_pattern_checker_0 | ||
pattern_in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_clk_50 | clk | xcvr_0_tester_1_timer_0 |
clk | ||
clk_reset | ||
reset | ||
xcvr_0_tester_1_mm_bridge_0 | m0 | |
s1 | ||
xcvr_0_tester_1_master_driver_com_0 | avalon_master | |
s1 |
Parameters
|
Software Assignments
|
xcvr_0_tester_1_clk_50 | clk_reset | xcvr_0_tester_1_master_driver_com_0 | |
reset | |||
clk | |||
clock | |||
xcvr_0_tester_1_mm_bridge_0 | m0 | ||
csr | |||
avalon_master | xcvr_0_tester_1_timer_0 | ||
s1 | |||
avalon_master | xcvr_0_tester_1_data_pattern_checker_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_1_data_pattern_generator_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_1_freq_counter_0 | ||
csr |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_clk_50 | clk | xcvr_0_tester_1_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
xcvr_0_mm_bridge_0 | m0 | ||
s0 | |||
m0 | xcvr_0_tester_1_master_driver_com_0 | ||
csr | |||
m0 | xcvr_0_tester_1_timer_0 | ||
s1 | |||
m0 | xcvr_0_tester_1_data_pattern_checker_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_1_data_pattern_generator_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_1_freq_counter_0 | ||
csr |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_1_clk_50 | clk_reset | xcvr_0_tester_1_freq_counter_0 |
reset | ||
clk | ||
clock | ||
xcvr_0_tester_1_mm_bridge_0 | m0 | |
csr | ||
xcvr_0_tester_1_master_driver_com_0 | avalon_master | |
csr | ||
xcvr_0_tester_1_rx_clk | out_clk | |
sample_clock |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
xcvr_0_clk_50 | clk | xcvr_0_tester_2_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk_reset | xcvr_0_tester_2_timing_adapter_tx0 | ||
reset | |||
clk_reset | xcvr_0_tester_2_timing_adapter_rx0 | ||
reset | |||
clk | xcvr_0_tester_2_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_2_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_2_data_format_adapter_0 | ||
reset | |||
clk_reset | xcvr_0_tester_2_data_format_adapter_1 | ||
reset | |||
clk | xcvr_0_tester_2_timer_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_2_master_driver_com_0 | ||
reset | |||
clk | |||
clock | |||
clk | xcvr_0_tester_2_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_2_freq_counter_0 | ||
reset | |||
clk | |||
clock |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_clk_50 | clk | xcvr_0_tester_2_data_pattern_generator_0 | |
csr_clk | |||
clk_reset | |||
reset | |||
xcvr_0_tester_2_tx_clk | out_clk | ||
pattern_out_clk | |||
xcvr_0_tester_2_mm_bridge_0 | m0 | ||
csr_slave | |||
xcvr_0_tester_2_master_driver_com_0 | avalon_master | ||
csr_slave | |||
pattern_out | xcvr_0_tester_2_data_format_adapter_0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_clk_50 | clk | xcvr_0_tester_2_data_pattern_checker_0 |
csr_clk | ||
clk_reset | ||
reset | ||
xcvr_0_tester_2_rx_clk | out_clk | |
pattern_in_clk | ||
xcvr_0_tester_2_data_format_adapter_1 | out | |
pattern_in | ||
xcvr_0_tester_2_mm_bridge_0 | m0 | |
csr_slave | ||
xcvr_0_tester_2_master_driver_com_0 | avalon_master | |
csr_slave |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_clk_50 | clk_reset | xcvr_0_tester_2_timing_adapter_tx0 | |
reset | |||
xcvr_0_tester_2_tx_clk | out_clk | ||
clk | |||
xcvr_0_tester_2_data_format_adapter_0 | out | ||
in | |||
out | xcvr_0_xcvr_custom_phy_0 | ||
tx_parallel_data2 |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_clk_50 | clk_reset | xcvr_0_tester_2_timing_adapter_rx0 | |
reset | |||
xcvr_0_tester_2_rx_clk | out_clk | ||
clk | |||
xcvr_0_xcvr_custom_phy_0 | rx_parallel_data2 | ||
in | |||
out | xcvr_0_tester_2_data_format_adapter_1 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_0 | rx_clkout2 | xcvr_0_tester_2_rx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_2_timing_adapter_rx0 | ||
clk | |||
out_clk | xcvr_0_tester_2_data_pattern_checker_0 | ||
pattern_in_clk | |||
out_clk | xcvr_0_tester_2_data_format_adapter_1 | ||
clk | |||
out_clk | xcvr_0_tester_2_freq_counter_0 | ||
sample_clock |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_0 | tx_clkout2 | xcvr_0_tester_2_tx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_2_timing_adapter_tx0 | ||
clk | |||
out_clk | xcvr_0_tester_2_data_pattern_generator_0 | ||
pattern_out_clk | |||
out_clk | xcvr_0_tester_2_data_format_adapter_0 | ||
clk |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_tx_clk | out_clk | xcvr_0_tester_2_data_format_adapter_0 | |
clk | |||
xcvr_0_tester_2_clk_50 | clk_reset | ||
reset | |||
xcvr_0_tester_2_data_pattern_generator_0 | pattern_out | ||
in | |||
out | xcvr_0_tester_2_timing_adapter_tx0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_rx_clk | out_clk | xcvr_0_tester_2_data_format_adapter_1 | |
clk | |||
xcvr_0_tester_2_clk_50 | clk_reset | ||
reset | |||
xcvr_0_tester_2_timing_adapter_rx0 | out | ||
in | |||
out | xcvr_0_tester_2_data_pattern_checker_0 | ||
pattern_in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_clk_50 | clk | xcvr_0_tester_2_timer_0 |
clk | ||
clk_reset | ||
reset | ||
xcvr_0_tester_2_mm_bridge_0 | m0 | |
s1 | ||
xcvr_0_tester_2_master_driver_com_0 | avalon_master | |
s1 |
Parameters
|
Software Assignments
|
xcvr_0_tester_2_clk_50 | clk_reset | xcvr_0_tester_2_master_driver_com_0 | |
reset | |||
clk | |||
clock | |||
xcvr_0_tester_2_mm_bridge_0 | m0 | ||
csr | |||
avalon_master | xcvr_0_tester_2_timer_0 | ||
s1 | |||
avalon_master | xcvr_0_tester_2_data_pattern_checker_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_2_data_pattern_generator_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_2_freq_counter_0 | ||
csr |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_clk_50 | clk | xcvr_0_tester_2_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
xcvr_0_mm_bridge_0 | m0 | ||
s0 | |||
m0 | xcvr_0_tester_2_master_driver_com_0 | ||
csr | |||
m0 | xcvr_0_tester_2_timer_0 | ||
s1 | |||
m0 | xcvr_0_tester_2_data_pattern_checker_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_2_data_pattern_generator_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_2_freq_counter_0 | ||
csr |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_2_clk_50 | clk_reset | xcvr_0_tester_2_freq_counter_0 |
reset | ||
clk | ||
clock | ||
xcvr_0_tester_2_mm_bridge_0 | m0 | |
csr | ||
xcvr_0_tester_2_master_driver_com_0 | avalon_master | |
csr | ||
xcvr_0_tester_2_rx_clk | out_clk | |
sample_clock |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
xcvr_0_clk_50 | clk | xcvr_0_tester_3_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk_reset | xcvr_0_tester_3_timing_adapter_tx0 | ||
reset | |||
clk_reset | xcvr_0_tester_3_timing_adapter_rx0 | ||
reset | |||
clk | xcvr_0_tester_3_data_pattern_checker_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk | xcvr_0_tester_3_data_pattern_generator_0 | ||
csr_clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_3_data_format_adapter_0 | ||
reset | |||
clk_reset | xcvr_0_tester_3_data_format_adapter_1 | ||
reset | |||
clk | xcvr_0_tester_3_timer_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_3_master_driver_com_0 | ||
reset | |||
clk | |||
clock | |||
clk | xcvr_0_tester_3_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk_reset | xcvr_0_tester_3_freq_counter_0 | ||
reset | |||
clk | |||
clock |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_clk_50 | clk | xcvr_0_tester_3_data_pattern_generator_0 | |
csr_clk | |||
clk_reset | |||
reset | |||
xcvr_0_tester_3_tx_clk | out_clk | ||
pattern_out_clk | |||
xcvr_0_tester_3_mm_bridge_0 | m0 | ||
csr_slave | |||
xcvr_0_tester_3_master_driver_com_0 | avalon_master | ||
csr_slave | |||
pattern_out | xcvr_0_tester_3_data_format_adapter_0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_clk_50 | clk | xcvr_0_tester_3_data_pattern_checker_0 |
csr_clk | ||
clk_reset | ||
reset | ||
xcvr_0_tester_3_rx_clk | out_clk | |
pattern_in_clk | ||
xcvr_0_tester_3_data_format_adapter_1 | out | |
pattern_in | ||
xcvr_0_tester_3_mm_bridge_0 | m0 | |
csr_slave | ||
xcvr_0_tester_3_master_driver_com_0 | avalon_master | |
csr_slave |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_clk_50 | clk_reset | xcvr_0_tester_3_timing_adapter_tx0 | |
reset | |||
xcvr_0_tester_3_tx_clk | out_clk | ||
clk | |||
xcvr_0_tester_3_data_format_adapter_0 | out | ||
in | |||
out | xcvr_0_xcvr_custom_phy_0 | ||
tx_parallel_data3 |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_clk_50 | clk_reset | xcvr_0_tester_3_timing_adapter_rx0 | |
reset | |||
xcvr_0_tester_3_rx_clk | out_clk | ||
clk | |||
xcvr_0_xcvr_custom_phy_0 | rx_parallel_data3 | ||
in | |||
out | xcvr_0_tester_3_data_format_adapter_1 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_0 | rx_clkout3 | xcvr_0_tester_3_rx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_3_timing_adapter_rx0 | ||
clk | |||
out_clk | xcvr_0_tester_3_data_pattern_checker_0 | ||
pattern_in_clk | |||
out_clk | xcvr_0_tester_3_data_format_adapter_1 | ||
clk | |||
out_clk | xcvr_0_tester_3_freq_counter_0 | ||
sample_clock |
Parameters
|
Software Assignments(none) |
xcvr_0_xcvr_custom_phy_0 | tx_clkout3 | xcvr_0_tester_3_tx_clk | |
in_clk | |||
out_clk | xcvr_0_tester_3_timing_adapter_tx0 | ||
clk | |||
out_clk | xcvr_0_tester_3_data_pattern_generator_0 | ||
pattern_out_clk | |||
out_clk | xcvr_0_tester_3_data_format_adapter_0 | ||
clk |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_tx_clk | out_clk | xcvr_0_tester_3_data_format_adapter_0 | |
clk | |||
xcvr_0_tester_3_clk_50 | clk_reset | ||
reset | |||
xcvr_0_tester_3_data_pattern_generator_0 | pattern_out | ||
in | |||
out | xcvr_0_tester_3_timing_adapter_tx0 | ||
in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_rx_clk | out_clk | xcvr_0_tester_3_data_format_adapter_1 | |
clk | |||
xcvr_0_tester_3_clk_50 | clk_reset | ||
reset | |||
xcvr_0_tester_3_timing_adapter_rx0 | out | ||
in | |||
out | xcvr_0_tester_3_data_pattern_checker_0 | ||
pattern_in |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_clk_50 | clk | xcvr_0_tester_3_timer_0 |
clk | ||
clk_reset | ||
reset | ||
xcvr_0_tester_3_mm_bridge_0 | m0 | |
s1 | ||
xcvr_0_tester_3_master_driver_com_0 | avalon_master | |
s1 |
Parameters
|
Software Assignments
|
xcvr_0_tester_3_clk_50 | clk_reset | xcvr_0_tester_3_master_driver_com_0 | |
reset | |||
clk | |||
clock | |||
xcvr_0_tester_3_mm_bridge_0 | m0 | ||
csr | |||
avalon_master | xcvr_0_tester_3_timer_0 | ||
s1 | |||
avalon_master | xcvr_0_tester_3_data_pattern_checker_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_3_data_pattern_generator_0 | ||
csr_slave | |||
avalon_master | xcvr_0_tester_3_freq_counter_0 | ||
csr |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_clk_50 | clk | xcvr_0_tester_3_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
xcvr_0_mm_bridge_0 | m0 | ||
s0 | |||
m0 | xcvr_0_tester_3_master_driver_com_0 | ||
csr | |||
m0 | xcvr_0_tester_3_timer_0 | ||
s1 | |||
m0 | xcvr_0_tester_3_data_pattern_checker_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_3_data_pattern_generator_0 | ||
csr_slave | |||
m0 | xcvr_0_tester_3_freq_counter_0 | ||
csr |
Parameters
|
Software Assignments(none) |
xcvr_0_tester_3_clk_50 | clk_reset | xcvr_0_tester_3_freq_counter_0 |
reset | ||
clk | ||
clock | ||
xcvr_0_tester_3_mm_bridge_0 | m0 | |
csr | ||
xcvr_0_tester_3_master_driver_com_0 | avalon_master | |
csr | ||
xcvr_0_tester_3_rx_clk | out_clk | |
sample_clock |
Parameters
|
Software Assignments(none) |
clk_50 | clk | xcvr_0_clk_50 | |
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_tester_3_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_tester_2_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_tester_1_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_tester_0_clk_50 | ||
clk_in | |||
clk_reset | |||
clk_in_reset | |||
clk | xcvr_0_mm_bridge_0 | ||
clk | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
xcvr_0_clk_50 | clk | xcvr_0_mm_bridge_0 | |
clk | |||
clk_reset | |||
reset | |||
master_0 | master | ||
s0 | |||
m0 | xcvr_0_tester_3_mm_bridge_0 | ||
s0 | |||
m0 | xcvr_0_tester_2_mm_bridge_0 | ||
s0 | |||
m0 | xcvr_0_tester_1_mm_bridge_0 | ||
s0 | |||
m0 | xcvr_0_tester_0_mm_bridge_0 | ||
s0 | |||
m0 | xcvr_0_alt_xcvr_reconfig_0 | ||
reconfig_mgmt | |||
m0 | xcvr_0_xcvr_custom_phy_0 | ||
phy_mgmt |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
generation took 0.03 seconds | rendering took 0.49 seconds |