2023.06.13.13:55:54 |
Datasheet |
Overview
Memory Map
clk_50
clock_source v22.1
Parameters
clockFrequency |
100000000 |
clockFrequencyKnown |
true |
inputClockFrequency |
0 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
data_format_adapter_0
data_format_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
AUTO |
inUseEmpty |
false |
outUseEmptyPort |
AUTO |
outUseEmpty |
false |
inSymbolsPerBeat |
4 |
outSymbolsPerBeat |
4 |
inReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
data_format_adapter_1
data_format_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
AUTO |
inUseEmpty |
false |
outUseEmptyPort |
AUTO |
outUseEmpty |
false |
inSymbolsPerBeat |
4 |
outSymbolsPerBeat |
4 |
inReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
data_pattern_checker_0
altera_avalon_data_pattern_checker v22.1
Parameters
ST_DATA_W |
40 |
NUM_CYCLES_FOR_LOCK |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
100000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
data_pattern_generator_0
altera_avalon_data_pattern_generator v22.1
Parameters
ST_DATA_W |
40 |
BYPASS_ENABLED |
false |
AVALON_ENABLED |
true |
FREQ_CNTER_ENABLED |
false |
CROSS_CLK_SYNC_DEPTH |
2 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_DEVICE |
5CGTFD9E5F35C7 |
AUTO_DEVICE_SPEEDGRADE |
7_H5 |
AUTO_CSR_CLK_CLOCK_RATE |
100000000 |
AUTO_CSR_CLK_CLOCK_DOMAIN |
1 |
AUTO_CSR_CLK_RESET_DOMAIN |
1 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
freq_counter_0
freq_counter v1.0
Parameters
SYSTEM_CLK_FREQ_PICO_SEC |
20000 |
DIV |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
master_driver_com_0
master_driver_com v1.0
Parameters
CHECKER_BASE |
32 |
GENERATOR_BASE |
0 |
TIMER_BASE |
256 |
FREQ_BASE |
512 |
DESERIALIZATION_FACTOR |
40 |
NUM_OF_CH |
1 |
ENABLE_PER_INFO |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
mm_bridge_0
altera_avalon_mm_bridge v22.1
Parameters
DATA_WIDTH |
32 |
SYMBOL_WIDTH |
8 |
ADDRESS_WIDTH |
10 |
SYSINFO_ADDR_WIDTH |
10 |
USE_AUTO_ADDRESS_WIDTH |
0 |
AUTO_ADDRESS_WIDTH |
10 |
HDL_ADDR_WIDTH |
10 |
ADDRESS_UNITS |
SYMBOLS |
BURSTCOUNT_WIDTH |
1 |
MAX_BURST_SIZE |
1 |
MAX_PENDING_RESPONSES |
4 |
LINEWRAPBURSTS |
0 |
PIPELINE_COMMAND |
1 |
PIPELINE_RESPONSE |
1 |
USE_RESPONSE |
0 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
rx_clk
altera_clock_bridge v22.1
Parameters
DERIVED_CLOCK_RATE |
0 |
EXPLICIT_CLOCK_RATE |
0 |
NUM_CLOCK_OUTPUTS |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
timer_0
altera_avalon_timer v22.1
Parameters
alwaysRun |
false |
counterSize |
64 |
fixedPeriod |
false |
period |
1 |
periodUnits |
MSEC |
resetOutput |
false |
snapshot |
true |
timeoutPulseOutput |
false |
systemFrequency |
100000000 |
watchdogPulse |
2 |
timerPreset |
FULL_FEATURED |
periodUnitsString |
ms |
valueInSecond |
0.001 |
loadValue |
99999 |
mult |
0.001 |
ticksPerSec |
1000.0 |
slave_address_width |
4 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments
ALWAYS_RUN |
0 |
COUNTER_SIZE |
64 |
FIXED_PERIOD |
0 |
FREQ |
100000000 |
LOAD_VALUE |
99999 |
MULT |
0.001 |
PERIOD |
1 |
PERIOD_UNITS |
ms |
RESET_OUTPUT |
0 |
SNAPSHOT |
1 |
TICKS_PER_SEC |
1000 |
TIMEOUT_PULSE_OUTPUT |
0 |
TIMER_DEVICE_TYPE |
1 |
|
timing_adapter_rx0
timing_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
NO |
inUseEmpty |
false |
inSymbolsPerBeat |
4 |
inUseReady |
false |
outUseReady |
true |
inReadyLatency |
0 |
outReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
inUseValid |
false |
outUseValid |
true |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
timing_adapter_tx0
timing_adapter v22.1
Parameters
inChannelWidth |
0 |
inMaxChannel |
0 |
inBitsPerSymbol |
10 |
inUsePackets |
false |
inUseEmptyPort |
NO |
inUseEmpty |
false |
inSymbolsPerBeat |
4 |
inUseReady |
true |
outUseReady |
false |
inReadyLatency |
0 |
outReadyLatency |
0 |
inErrorWidth |
0 |
inErrorDescriptor |
|
inUseValid |
true |
outUseValid |
false |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
tx_clk
altera_clock_bridge v22.1
Parameters
DERIVED_CLOCK_RATE |
0 |
EXPLICIT_CLOCK_RATE |
0 |
NUM_CLOCK_OUTPUTS |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
generation took 0.01 seconds |
rendering took 0.03 seconds |