LPDDR4_1x16_1EMIF_emif_hps_ph2_0

2024.04.05.16:44:37 Datasheet
Overview

Memory Map
  emif_hps_ph2_0
s0_axi4 
s0_axil 

emif_hps_ph2_0

emif_hps_ph2 v6.1.0


Parameters

MEM_TECHNOLOGY_AUTO_BOOL false
MEM_TECHNOLOGY MEM_TECHNOLOGY_LPDDR4
HPS_EMIF_CONFIG_AUTO_BOOL false
HPS_EMIF_CONFIG HPS_EMIF_1x16
MEM_FORMAT MEM_FORMAT_DISCRETE
MEM_TOPOLOGY MEM_TOPOLOGY_FLYBY
MEM_NUM_RANKS 1
MEM_NUM_CHANNELS 1
MEM_DEVICE_DQ_WIDTH 16
MEM_COMPS_PER_RANK 1
MEM_AC_MIRRORING_AUTO_BOOL true
MEM_AC_MIRRORING_AUTO false
CTRL_ECC_MODE_AUTO_BOOL true
CTRL_ECC_MODE_AUTO CTRL_ECC_MODE_DISABLED
MEM_TOTAL_DQ_WIDTH 16
PHY_AC_PLACEMENT_AUTO_BOOL true
PHY_AC_PLACEMENT_AUTO PHY_AC_PLACEMENT_AUTO
PHY_MEMCLK_FREQ_MHZ_AUTO_BOOL true
PHY_MEMCLK_FREQ_MHZ_AUTO 1333.0
MEM_PRESET_FILE_EN false
MEM_PRESET_ID_AUTO_BOOL false
MEM_PRESET_ID LPDDR4-2667 CL24 Component Single-Channel 1R 1CPR 16Gb (16Gb Total) x16 CK 1333.0 MHz
PHY_REFCLK_FREQ_MHZ_AUTO_BOOL true
PHY_REFCLK_FREQ_MHZ_AUTO 199.95
PHY_IO_VOLTAGE 1.1
GRP_PHY_AC_AUTO_BOOL true
GRP_PHY_AC_X_R_S_AC_OUTPUT_OHM_AUTO RTT_PHY_OUT_40_CAL
GRP_PHY_CLK_AUTO_BOOL true
GRP_PHY_CLK_X_R_S_CK_OUTPUT_OHM_AUTO RTT_PHY_OUT_40_CAL
GRP_PHY_DATA_AUTO_BOOL true
GRP_PHY_DATA_X_DQ_IO_STD_TYPE_AUTO PHY_IO_STD_TYPE_LVSTL
GRP_PHY_DATA_X_R_S_DQ_OUTPUT_OHM_AUTO RTT_PHY_OUT_40_CAL
GRP_PHY_DATA_X_DQ_SLEW_RATE_AUTO PHY_SLEW_RATE_FASTEST
GRP_PHY_DATA_X_R_T_DQ_INPUT_OHM_AUTO RTT_PHY_IN_50_CAL
GRP_PHY_DATA_X_DQ_VREF_AUTO 17.5
GRP_PHY_IN_AUTO_BOOL true
GRP_PHY_IN_X_R_T_REFCLK_INPUT_OHM_AUTO LVDS_DIFF_TERM_ON
GRP_PHY_DFE_AUTO_BOOL true
GRP_MEM_ODT_DQ_AUTO_BOOL true
GRP_MEM_ODT_DQ_X_TGT_WR_AUTO MEM_RTT_COMM_5
GRP_MEM_ODT_DQ_X_RON_AUTO MEM_DRIVE_STRENGTH_6
GRP_MEM_DQ_VREF_AUTO_BOOL true
GRP_MEM_DQ_VREF_X_RANGE_AUTO MEM_VREF_RANGE_LP4_1
GRP_MEM_DQ_VREF_X_VALUE_AUTO 18.0
GRP_MEM_ODT_CA_AUTO_BOOL true
GRP_MEM_ODT_CA_X_CA_COMM_AUTO MEM_RTT_COMM_3
GRP_MEM_ODT_CA_X_CA_ENABLE_AUTO MEM_RTT_COMM_EN_TRUE
GRP_MEM_ODT_CA_X_CS_ENABLE_AUTO MEM_RTT_COMM_EN_TRUE
GRP_MEM_ODT_CA_X_CK_ENABLE_AUTO MEM_RTT_COMM_EN_TRUE
GRP_MEM_VREF_CA_AUTO_BOOL true
GRP_MEM_VREF_CA_X_CA_RANGE_AUTO MEM_CA_VREF_RANGE_LP4_2
GRP_MEM_VREF_CA_X_CA_VALUE_AUTO 27.2
GRP_MEM_DFE_AUTO_BOOL true
USER_EXTRA_PARAMETERS
DEBUG_TOOLS_EN false
AXI_SIDEBAND_ACCESS_MODE_AUTO_BOOL true
AXI_SIDEBAND_ACCESS_MODE_AUTO NOC
INSTANCE_ID_IP0 0
EX_DESIGN_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GEN_SYNTH true
EX_DESIGN_GEN_SIM true
EX_DESIGN_CORE_CLK_FREQ_MHZ_AUTO_BOOL true
EX_DESIGN_CORE_CLK_FREQ_MHZ_AUTO 200
EX_DESIGN_CORE_REFCLK_FREQ_MHZ 100
EX_DESIGN_HYDRA_REMOTE CONFIG_INTF_MODE_REMOTE_JTAG
EX_DESIGN_PMON_ENABLED false
EX_DESIGN_HYDRA_PROG emif_tg_emulation
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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