LPDDR4_2x16_1EMIF

2024.04.05.17:16:38 Datasheet
Overview

Memory Map
intel_agilex_5_soc_0
 io96b0_csr_axi  io96b0_ch0_axi  io96b0_ch1_axi
  emif_hps_ph2_0
s0_axi4  0x0000_0000_0000_0000 - 0x0000_00ff_ffff_ffff
s1_axi4  0x0000_0000_0000_0000 - 0x0000_00ff_ffff_ffff
s0_axil  0x0000_0000 - 0x07ff_ffff

clock_in

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_hps_ph2_0

emif_hps_ph2 v6.1.0
intel_agilex_5_soc_0 io96b0_ch0_axi   emif_hps_ph2_0
  s0_axi4
io96b0_ch1_axi  
  s1_axi4
io96b0_csr_axi  
  s0_axil
s0_axil_clk   intel_agilex_5_soc_0
  io96b0_csr_axi_clk
usr_clk_0  
  io96b0_ch0_axi_clk
usr_clk_1  
  io96b0_ch1_axi_clk
s0_axil_rst_n  
  io96b0_csr_axi_rst
usr_rst_n_0  
  io96b0_ch0_axi_rst
usr_rst_n_1  
  io96b0_ch1_axi_rst


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_agilex_5_soc_0

intel_agilex_5_soc v3.0.0
emif_hps_ph2_0 s0_axil_clk   intel_agilex_5_soc_0
  io96b0_csr_axi_clk
usr_clk_0  
  io96b0_ch0_axi_clk
usr_clk_1  
  io96b0_ch1_axi_clk
s0_axil_rst_n  
  io96b0_csr_axi_rst
usr_rst_n_0  
  io96b0_ch0_axi_rst
usr_rst_n_1  
  io96b0_ch1_axi_rst
io96b0_ch0_axi   emif_hps_ph2_0
  s0_axi4
io96b0_ch1_axi  
  s1_axi4
io96b0_csr_axi  
  s0_axil


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_in

altera_reset_bridge v19.2.0
clock_in out_clk   reset_in
  clk


Parameters

generateLegacySim false
  

Software Assignments

(none)
generation took 0.00 seconds rendering took 0.03 seconds